From 64a99ef412eea19d61de97b583b285b54f2b7fae Mon Sep 17 00:00:00 2001
From: hongshuqing <hongshuqing@espressif.com>
Date: Mon, 19 Feb 2024 14:33:40 +0800
Subject: [PATCH] fix: fix s3 bbpll cali fail bug

---
 components/hal/esp32s3/include/hal/clk_tree_ll.h | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h
index c62334c8c8..b3c611fa29 100644
--- a/components/hal/esp32s3/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32s3/include/hal/clk_tree_ll.h
@@ -305,7 +305,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
     uint8_t dr3;
     uint8_t dchgp;
     uint8_t dcur;
-    uint8_t dbias;
+    uint8_t dbias = 3;
 
     if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
         /* Configure 480M PLL */
@@ -317,7 +317,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 0;
             dchgp = 5;
             dcur = 3;
-            dbias = 2;
             break;
         case RTC_XTAL_FREQ_32M:
             div_ref = 1;
@@ -326,7 +325,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 1;
             dchgp = 4;
             dcur = 0;
-            dbias = 2;
             break;
         default:
             div_ref = 0;
@@ -335,7 +333,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 0;
             dchgp = 5;
             dcur = 3;
-            dbias = 2;
             break;
         }
         REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
@@ -349,7 +346,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 0;
             dchgp = 5;
             dcur = 3;
-            dbias = 2;
             break;
         case RTC_XTAL_FREQ_32M:
             div_ref = 1;
@@ -358,7 +354,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 0;
             dchgp = 5;
             dcur = 3;
-            dbias = 2;
             break;
         default:
             div_ref = 0;
@@ -367,7 +362,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
             dr3 = 0;
             dchgp = 5;
             dcur = 3;
-            dbias = 2;
             break;
         }
         REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);