diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index 254481caae..1e639d7ddb 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -207,6 +207,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y
 
+config SOC_IDCACHE_PER_CORE
+    bool
+    default y
+
 config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
     int
     default 5
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index d9e3bc66bc..532137aea1 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -133,7 +133,8 @@
 
 
 /*-------------------------- CACHE/MMU CAPS ----------------------------------*/
-#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data within one core
+#define SOC_IDCACHE_PER_CORE                    1   //Independent Cache unit pre core
 #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM       5
 
 
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index f0a96f6032..e3638ace97 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -203,13 +203,16 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
     // with non-iram interrupts and the scheduler disabled. None of these CPUs will
     // touch external RAM or flash this way, so we can safely disable caches.
     spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
+#if SOC_IDCACHE_PER_CORE
+    //only needed if cache(s) is per core
     spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
+#endif
 }
 
 void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 {
     const int cpuid = xPortGetCoreID();
-    const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
+
 #ifndef NDEBUG
     // Sanity check: flash operation ends on the same CPU as it has started
     assert(cpuid == s_flash_op_cpu);
@@ -220,7 +223,11 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
 
     // Re-enable cache on both CPUs. After this, cache (flash and external RAM) should work again.
     spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
+#if SOC_IDCACHE_PER_CORE
+    //only needed if cache(s) is per core
+    const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
     spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
+#endif
 
     if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
         // Signal to spi_flash_op_block_task that flash operation is complete