blackbeard420/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf synced 2025-03-09 17:19:09 -04:00
Code Issues Projects Releases Wiki Activity

Merge branch 'feature/s2_ulp_riscv_adc_v5.0' into 'release/v5.0'

Browse Source 
ulp-riscv: enable ULP-RISCV ADC example for esp32s2 (v5.0)

See merge request espressif/esp-idf!23372
This commit is contained in:
Jiang Jiang Jian 2023-06-13 20:18:13 +08:00
commit 69b3835cee
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
examples/system/.build-test-rules.yml
View File

@ -160,7 +160,7 @@ examples/system/ulp_fsm/ulp_adc:
examples/system/ulp_riscv/adc:
enable:
- if: IDF_TARGET in ["esp32s3"]
- if: IDF_TARGET in ["esp32s2", "esp32s3"]
temporary: true
reason: the other targets are not tested yet

4
examples/system/ulp_riscv/adc/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32-S3 |
| ----------------- | -------- |
| Supported Targets | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- |
# ULP-RISC-V ADC Example