mirror of
https://github.com/espressif/esp-idf
synced 2025-03-09 17:19:09 -04:00
Add handling of FPU for Xtensa CPU in gdbstub.
This commit is contained in:
Dmitry Yakovlev
parent
8d75f0d198
commit
6b56caba16
@ -62,11 +62,11 @@ void esp_gdbstub_panic_handler(void *in_frame)
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esp_gdbstub_send_end();
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} else if (s_scratch.state == GDBSTUB_NOT_STARTED) {
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s_scratch.state = GDBSTUB_STARTED;
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/* Save the paniced frame and get the list of tasks */
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/* Save the panicked frame and get the list of tasks */
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memcpy(&s_scratch.paniced_frame, frame, sizeof(*frame));
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init_task_info();
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find_paniced_task_index();
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/* Current task is the paniced task */
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/* Current task is the panicked task */
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if (s_scratch.paniced_task_index == GDBSTUB_CUR_TASK_INDEX_UNKNOWN) {
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set_active_task(0);
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} else {
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@ -144,7 +144,7 @@ static inline void disable_all_wdts(void)
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}
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#if SOC_TIMER_GROUPS >= 2
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/* Interupt WDT is the Main Watchdog Timer of Timer Group 1 */
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/* Interrupt WDT is the Main Watchdog Timer of Timer Group 1 */
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if (true == wdt1_context_enabled) {
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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@ -173,7 +173,7 @@ static inline void enable_all_wdts(void)
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wdt_hal_write_protect_enable(&wdt0_context);
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}
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#if SOC_TIMER_GROUPS >= 2
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/* Interupt WDT is the Main Watchdog Timer of Timer Group 1 */
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/* Interrupt WDT is the Main Watchdog Timer of Timer Group 1 */
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if (false == wdt1_context_enabled) {
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_enable(&wdt1_context);
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@ -208,7 +208,7 @@ static bool process_gdb_kill = false;
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static bool gdb_debug_int = false;
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/**
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* @breef Handle UART interrupt
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* @brief Handle UART interrupt
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*
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* Handle UART interrupt for gdbstub. The function disable WDT.
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* If Ctrl+C combination detected (0x03), then application will start to process incoming GDB messages.
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@ -658,7 +658,8 @@ static void handle_C_command(const unsigned char *cmd, int len)
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esp_gdbstub_send_str_packet("OK");
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}
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/** Set Register ... */
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/* Set Register ... */
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static void handle_P_command(const unsigned char *cmd, int len)
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{
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uint32_t reg_index = 0;
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@ -684,7 +685,7 @@ static void handle_P_command(const unsigned char *cmd, int len)
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p_addr_ptr[0] = addr_ptr[3];
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esp_gdbstub_set_register((esp_gdbstub_frame_t *)temp_regs_frame, reg_index, p_address);
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/* Convert current regioster file to GDB*/
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/* Convert current register file to GDB*/
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esp_gdbstub_frame_to_regfile((esp_gdbstub_frame_t *)temp_regs_frame, gdb_local_regfile);
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/* Sen OK response*/
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esp_gdbstub_send_str_packet("OK");
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@ -12,6 +12,7 @@
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#include "esp_cpu.h"
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#include "esp_ipc_isr.h"
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#include "esp_private/crosscore_int.h"
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#include <xtensa_context.h>
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#if !XCHAL_HAVE_WINDOWED
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#warning "gdbstub_xtensa: revisit the implementation for Call0 ABI"
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@ -38,13 +39,54 @@ static void update_regfile_common(esp_gdbstub_gdb_regfile_t *dst)
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RSR(CONFIGID1, dst->configid1);
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}
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#if XCHAL_HAVE_FP
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/** @brief Read FPU registers to memory
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*/
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static void gdbstub_read_fpu_regs(void *data)
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{
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float *ptr0;
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void *ptr1;
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asm volatile ("mov %0, %1" : "=a" (ptr0) : "a" (data));
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asm volatile ("rur.FCR %0" : "=a" (ptr1));
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asm volatile ("s32i %0, %1, 64" : "=a" (ptr1) : "a" (ptr0));
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asm volatile ("rur.FSR %0" : "=a" (ptr1));
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asm volatile ("s32i %0, %1, 68" : "=a" (ptr1) : "a" (ptr0));
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asm volatile ("ssi f0, %0, 0" :: "a" (ptr0)); //*(ptr0 + 0) = f0;
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asm volatile ("ssi f1, %0, 4" :: "a" (ptr0)); //*(ptr0 + 4) = f1;
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asm volatile ("ssi f2, %0, 8" :: "a" (ptr0)); //...
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asm volatile ("ssi f3, %0, 12" :: "a" (ptr0));
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asm volatile ("ssi f4, %0, 16" :: "a" (ptr0));
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asm volatile ("ssi f5, %0, 20" :: "a" (ptr0));
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asm volatile ("ssi f6, %0, 24" :: "a" (ptr0));
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asm volatile ("ssi f7, %0, 28" :: "a" (ptr0));
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asm volatile ("ssi f8, %0, 32" :: "a" (ptr0));
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asm volatile ("ssi f9, %0, 36" :: "a" (ptr0));
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asm volatile ("ssi f10, %0, 40" :: "a" (ptr0));
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asm volatile ("ssi f11, %0, 44" :: "a" (ptr0));
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asm volatile ("ssi f12, %0, 48" :: "a" (ptr0));
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asm volatile ("ssi f13, %0, 52" :: "a" (ptr0));
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asm volatile ("ssi f14, %0, 56" :: "a" (ptr0));
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asm volatile ("ssi f15, %0, 60" :: "a" (ptr0));
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}
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#endif // XCHAL_HAVE_FP
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extern const uint32_t offset_pxEndOfStack;
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extern const uint32_t offset_cpsa; /* Offset to start of the CPSA area on the stack. See uxInitialiseStackCPSA(). */
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extern uint32_t _xt_coproc_owner_sa[2];
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void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst)
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{
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init_regfile(dst);
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const uint32_t *a_regs = (const uint32_t *) &frame->a0;
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if (!(esp_ptr_executable(esp_cpu_pc_to_addr(frame->pc)) && (frame->pc & 0xC0000000U))) {
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/* Xtensa ABI sets the 2 MSBs of the PC according to the windowed call size
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* Incase the PC is invalid, GDB will fail to translate addresses to function names
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* In case the PC is invalid, GDB will fail to translate addresses to function names
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* Hence replacing the PC to a placeholder address in case of invalid PC
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*/
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dst->pc = (uint32_t)&_invalid_pc_placeholder;
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@ -59,6 +101,36 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_
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dst->a[i] = 0xDEADBEEF;
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}
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#if XCHAL_HAVE_FP
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extern void *pxCurrentTCBs[2];
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void *current_tcb_ptr = pxCurrentTCBs[0];
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uint32_t *current_fpu_ptr = NULL;
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#if !CONFIG_FREERTOS_UNICORE
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current_tcb_ptr = pxCurrentTCBs[esp_cpu_get_core_id()];
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#endif
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uint32_t cp_enabled;
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RSR(CPENABLE, cp_enabled);
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// Check if the co-processor is enabled
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if (cp_enabled) {
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gdbstub_read_fpu_regs(dst->f);
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} else {
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current_tcb_ptr += offset_pxEndOfStack;
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current_tcb_ptr = *(void **)current_tcb_ptr;
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current_tcb_ptr -= offset_cpsa;
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// Operation (&~0xf) required in .macro get_cpsa_from_tcb reg_A reg_B
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current_tcb_ptr = (void*)((uint32_t)current_tcb_ptr&~0xf);
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current_fpu_ptr = *(uint32_t **)(current_tcb_ptr + XT_CP_ASA);
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dst->fcr = current_fpu_ptr[0];
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dst->fsr = current_fpu_ptr[1];
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for (int i = 0; i < 16; i++) {
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dst->f[i] = current_fpu_ptr[i + 2];
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}
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}
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#endif //XCHAL_HAVE_FP
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#if XCHAL_HAVE_LOOPS
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dst->lbeg = frame->lbeg;
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dst->lend = frame->lend;
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@ -72,6 +144,84 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_
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#ifdef CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
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/* Represents FreeRTOS TCB structure */
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typedef struct {
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uint8_t *top_of_stack;
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/* Other members aren't needed */
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} dummy_tcb_t;
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void esp_gdbstub_tcb_frame_to_regfile(dummy_tcb_t *tcb, esp_gdbstub_gdb_regfile_t *dst)
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{
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const XtExcFrame *frame = (XtExcFrame *) tcb->top_of_stack;
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init_regfile(dst);
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const uint32_t *a_regs = (const uint32_t *) &frame->a0;
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if (!(esp_ptr_executable(esp_cpu_pc_to_addr(frame->pc)) && (frame->pc & 0xC0000000U))) {
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/* Xtensa ABI sets the 2 MSBs of the PC according to the windowed call size
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* In case the PC is invalid, GDB will fail to translate addresses to function names
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* Hence replacing the PC to a placeholder address in case of invalid PC
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*/
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dst->pc = (uint32_t)&_invalid_pc_placeholder;
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} else {
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dst->pc = (uint32_t)esp_cpu_pc_to_addr(frame->pc);
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}
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for (int i = 0; i < 16; i++) {
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dst->a[i] = a_regs[i];
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}
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for (int i = 16; i < 64; i++) {
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dst->a[i] = 0xDEADBEEF;
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}
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#if XCHAL_HAVE_FP
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uint32_t *current_xt_coproc_owner_sa = (uint32_t *)_xt_coproc_owner_sa[0];
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#if !CONFIG_FREERTOS_UNICORE
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current_xt_coproc_owner_sa = (uint32_t *)_xt_coproc_owner_sa[esp_cpu_get_core_id()];
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#endif
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uint32_t cp_enabled;
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RSR(CPENABLE, cp_enabled);
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void *current_tcb_ptr = tcb;
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uint32_t *current_fpu_ptr = NULL;
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{
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current_tcb_ptr += offset_pxEndOfStack;
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current_tcb_ptr = *(void **)current_tcb_ptr;
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current_tcb_ptr -= offset_cpsa;
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// Operation (&~0xf) required in .macro get_cpsa_from_tcb reg_A reg_B
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current_tcb_ptr = (void*)((uint32_t)current_tcb_ptr&~0xf);
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current_fpu_ptr = *(uint32_t **)(current_tcb_ptr + XT_CP_ASA);
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bool use_fpu_regs = ((false == cp_enabled) && (current_xt_coproc_owner_sa[0] == 1) && (current_fpu_ptr == (uint32_t*)current_xt_coproc_owner_sa[2]));
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dst->fcr = current_fpu_ptr[0];
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dst->fsr = current_fpu_ptr[1];
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for (int i = 0; i < 16; i++) {
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dst->f[i] = current_fpu_ptr[i + 2];
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}
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/* We have situation when FPU is in use, but the context not stored
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to the memory, and we have to read from CPU registers.
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*/
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if (use_fpu_regs) {
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gdbstub_read_fpu_regs(dst->f);
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}
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}
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#endif // XCHAL_HAVE_FP
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#if XCHAL_HAVE_LOOPS
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dst->lbeg = frame->lbeg;
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dst->lend = frame->lend;
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dst->lcount = frame->lcount;
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#endif
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dst->ps = (frame->ps & PS_UM) ? (frame->ps & ~PS_EXCM) : frame->ps;
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dst->sar = frame->sar;
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update_regfile_common(dst);
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}
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static void solicited_frame_to_regfile(const XtSolFrame *frame, esp_gdbstub_gdb_regfile_t *dst)
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{
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init_regfile(dst);
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@ -94,20 +244,12 @@ static void solicited_frame_to_regfile(const XtSolFrame *frame, esp_gdbstub_gdb_
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update_regfile_common(dst);
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}
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/* Represents FreeRTOS TCB structure */
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typedef struct {
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uint8_t *top_of_stack;
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/* Other members aren't needed */
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} dummy_tcb_t;
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void esp_gdbstub_tcb_to_regfile(TaskHandle_t tcb, esp_gdbstub_gdb_regfile_t *dst)
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{
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const dummy_tcb_t *dummy_tcb = (const dummy_tcb_t *) tcb;
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dummy_tcb_t *dummy_tcb = (dummy_tcb_t *) tcb;
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const XtExcFrame *frame = (XtExcFrame *) dummy_tcb->top_of_stack;
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if (frame->exit != 0) {
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esp_gdbstub_frame_to_regfile(frame, dst);
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esp_gdbstub_tcb_frame_to_regfile(dummy_tcb, dst);
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} else {
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const XtSolFrame *taskFrame = (const XtSolFrame *) dummy_tcb->top_of_stack;
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solicited_frame_to_regfile(taskFrame, dst);
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@ -206,14 +348,80 @@ void esp_gdbstub_trigger_cpu(void)
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* Set register in frame with address to value
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*
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* */
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void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value)
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{
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switch (reg_index) {
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case 0:
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uint32_t temp_fpu_value = value;
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float *ptr0;
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asm volatile ("mov %0, %1" : "=a" (ptr0) : "a" (&temp_fpu_value));
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if (reg_index == 0) {
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frame->pc = value;
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break;
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default:
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} else if (reg_index > 0 && (reg_index <= 27)) {
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(&frame->a0)[reg_index - 1] = value;
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break;
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}
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#if XCHAL_HAVE_FP
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void *ptr1;
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uint32_t cp_enabled;
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RSR(CPENABLE, cp_enabled);
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if (cp_enabled != 0) {
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if (reg_index == 87) {
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asm volatile ("lsi f0, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 88) {
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asm volatile ("lsi f1, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 89) {
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asm volatile ("lsi f2, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 90) {
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asm volatile ("lsi f3, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 91) {
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asm volatile ("lsi f4, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 92) {
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asm volatile ("lsi f5, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 93) {
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asm volatile ("lsi f6, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 94) {
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asm volatile ("lsi f7, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 95) {
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asm volatile ("lsi f8, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 96) {
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asm volatile ("lsi f9, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 97) {
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asm volatile ("lsi f10, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 98) {
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asm volatile ("lsi f11, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 99) {
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asm volatile ("lsi f12, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 100) {
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asm volatile ("lsi f13, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 101) {
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asm volatile ("lsi f14, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 102) {
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asm volatile ("lsi f15, %0, 0" :: "a" (ptr0));
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}
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if (reg_index == 103) {
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asm volatile ("l32i %0, %1, 0" : "=a" (ptr1) : "a" (ptr0));
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asm volatile ("wur.FCR %0" : "=a" (ptr1));
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}
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if (reg_index == 104) {
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asm volatile ("l32i %0, %1, 0" : "=a" (ptr1) : "a" (ptr0));
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asm volatile ("wur.FSR %0" : "=a" (ptr1));
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}
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}
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#endif // XCHAL_HAVE_FP
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}
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