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feat(esp_hw_support): Add locking layer for the ECC peripheral

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This commit is contained in:
harshal.patil 2023-09-20 09:58:10 +05:30
parent 2007f2f4cc
commit 6fdbd027c5
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GPG Key ID: 5B5EC97C35B9A2E5
6 changed files with 85 additions and 6 deletions
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27
components/esp_hw_support/include/soc/esp32c2/esp_crypto_lock.h Normal file
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@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Acquire lock for the ECC cryptography peripheral.
*
*/
void esp_crypto_ecc_lock_acquire(void);
/**
* @brief Release lock for the ECC cryptography peripheral.
*
*/
void esp_crypto_ecc_lock_release(void);
#ifdef __cplusplus
}
#endif

12
components/esp_hw_support/include/soc/esp32h2/esp_crypto_lock.h
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@ -63,6 +63,18 @@ void esp_crypto_mpi_lock_acquire(void);
*/
void esp_crypto_mpi_lock_release(void);
/**
* @brief Acquire lock for the ECC cryptography peripheral.
*
*/
void esp_crypto_ecc_lock_acquire(void);
/**
* @brief Release lock for the ECC cryptography peripheral.
*
*/
void esp_crypto_ecc_lock_release(void);
#ifdef __cplusplus
}
#endif

3
components/esp_hw_support/port/esp32c2/CMakeLists.txt
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@ -9,7 +9,8 @@ set(srcs "rtc_clk_init.c"
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "sar_periph_ctrl.c")
list(APPEND srcs "esp_crypto_lock.c"
"sar_periph_ctrl.c")
endif()

26
components/esp_hw_support/port/esp32c2/esp_crypto_lock.c Normal file
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@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/lock.h>
#include "esp_crypto_lock.h"
/* Lock overview:
ECC: independent
*/
/* Lock for ECC peripheral */
static _lock_t s_crypto_ecc_lock;
void esp_crypto_ecc_lock_acquire(void)
{
_lock_acquire(&s_crypto_ecc_lock);
}
void esp_crypto_ecc_lock_release(void)
{
_lock_release(&s_crypto_ecc_lock);
}

14
components/esp_hw_support/port/esp32h2/esp_crypto_lock.c
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@ -12,6 +12,7 @@
SHA: peripheral independent, but DMA is shared with AES
AES: peripheral independent, but DMA is shared with SHA
MPI/RSA: independent
ECC: independent
HMAC: needs SHA
DS: needs HMAC (which needs SHA), AES and MPI
*/
@ -28,6 +29,9 @@ static _lock_t s_crypto_mpi_lock;
/* Single lock for SHA and AES, sharing a reserved GDMA channel */
static _lock_t s_crypto_sha_aes_lock;
/* Lock for ECC peripheral */
static _lock_t s_crypto_ecc_lock;
void esp_crypto_hmac_lock_acquire(void)
{
_lock_acquire(&s_crypto_hmac_lock);
@ -73,3 +77,13 @@ void esp_crypto_mpi_lock_release(void)
{
_lock_release(&s_crypto_mpi_lock);
}
void esp_crypto_ecc_lock_acquire(void)
{
_lock_acquire(&s_crypto_ecc_lock);
}
void esp_crypto_ecc_lock_release(void)
{
_lock_release(&s_crypto_ecc_lock);
}

9
components/mbedtls/port/ecc/esp_ecc.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,15 +7,14 @@
#include <string.h>
#include <stdio.h>
#include "esp_crypto_lock.h"
#include "esp_private/periph_ctrl.h"
#include "ecc_impl.h"
#include "hal/ecc_hal.h"
static _lock_t s_crypto_ecc_lock;
static void esp_ecc_acquire_hardware(void)
{
_lock_acquire(&s_crypto_ecc_lock);
esp_crypto_ecc_lock_acquire();
periph_module_enable(PERIPH_ECC_MODULE);
}
@ -24,7 +23,7 @@ static void esp_ecc_release_hardware(void)
{
periph_module_disable(PERIPH_ECC_MODULE);
_lock_release(&s_crypto_ecc_lock);
esp_crypto_ecc_lock_release();
}
int esp_ecc_point_multiply(const ecc_point_t *point, const uint8_t *scalar, ecc_point_t *result, bool verify_first)