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https://github.com/espressif/esp-idf
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feat(efuse): Adds 3 bit for PSRAM_CAP efuse field
This commit is contained in:
Konstantin Kondrashov
parent
e6a97d2c56
commit
70b652052e
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table e0674ff40a1e124670c6eecf33410e76
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// md5_digest_table f8f32987a955792b4fe4534ea428268f
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -769,7 +769,8 @@ static const esp_efuse_desc_t FLASH_VENDOR[] = {
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};
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static const esp_efuse_desc_t PSRAM_CAP[] = {
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{EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"},
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{EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"},
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{EFUSE_BLK1, 179, 1}, // [] PSRAM capacity bit 3,
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};
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static const esp_efuse_desc_t PSRAM_TEMP[] = {
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@ -1869,7 +1870,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
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};
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const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
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&PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
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&PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"}
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&PSRAM_CAP[1], // [] PSRAM capacity bit 3
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NULL
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};
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@ -9,7 +9,7 @@
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 7127dd097e72bb90d0b790d460993126
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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@ -203,7 +203,8 @@ BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VE
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FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
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FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
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FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
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PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
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PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"}
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, EFUSE_BLK1, 179, 1, [] PSRAM capacity bit 3
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PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
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PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
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K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO
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Can't render this file because it contains an unexpected character in line 8 and column 53.
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -10,7 +10,7 @@ extern "C" {
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#include "esp_efuse.h"
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// md5_digest_table e0674ff40a1e124670c6eecf33410e76
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// md5_digest_table f8f32987a955792b4fe4534ea428268f
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -917,13 +917,27 @@ extern "C" {
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#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
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#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU
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#define EFUSE_DIG_DBIAS_HVT_S 11
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/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0;
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/** EFUSE_RESERVED_1_176 : R; bitpos: [18:16]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_1_176 0x0000007FU
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#define EFUSE_RESERVED_1_176 0x00000007U
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#define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S)
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#define EFUSE_RESERVED_1_176_V 0x0000007FU
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#define EFUSE_RESERVED_1_176_V 0x00000007U
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#define EFUSE_RESERVED_1_176_S 16
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/** EFUSE_PSRAM_CAP_3 : R; bitpos: [19]; default: 0;
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* PSRAM capacity bit 3
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*/
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#define EFUSE_PSRAM_CAP_3 (BIT(19))
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#define EFUSE_PSRAM_CAP_3_M (EFUSE_PSRAM_CAP_3_V << EFUSE_PSRAM_CAP_3_S)
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#define EFUSE_PSRAM_CAP_3_V 0x00000001U
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#define EFUSE_PSRAM_CAP_3_S 19
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/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_1_180 0x00000007U
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#define EFUSE_RESERVED_1_180_M (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S)
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#define EFUSE_RESERVED_1_180_V 0x00000007U
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#define EFUSE_RESERVED_1_180_S 20
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/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
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* WAFER_VERSION_MINOR most significant bit
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*/
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@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -672,10 +672,18 @@ typedef union {
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* BLOCK1 digital dbias when hvt
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*/
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uint32_t dig_dbias_hvt:5;
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/** reserved_1_176 : R; bitpos: [22:16]; default: 0;
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/** reserved_1_176 : R; bitpos: [18:16]; default: 0;
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* reserved
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*/
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uint32_t reserved_1_176:7;
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uint32_t reserved_1_176:3;
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/** psram_cap_3 : R; bitpos: [19]; default: 0;
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* PSRAM capacity bit 3
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*/
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uint32_t psram_cap_3:1;
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/** reserved_1_180 : R; bitpos: [22:20]; default: 0;
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* reserved
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*/
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uint32_t reserved_1_180:3;
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/** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
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* WAFER_VERSION_MINOR most significant bit
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*/
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