From dd5230866b441b0486ea98e69d0ac93bd6abc727 Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:53:54 +0800 Subject: [PATCH 1/9] change(ble): Update lib_esp32h2 to 3422b706 (cherry picked from commit fe5a12e7e74de53b8d3c6d5088419deb9a69f704) Co-authored-by: zhouxiao --- components/bt/controller/lib_esp32h2/esp32h2-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index 59c26f308e..f7ae7f056b 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit 59c26f308e18809cc02351febcbecad542a365c9 +Subproject commit f7ae7f056be96586e0915d9744d6233dc3ee5eef From 85a13050524dfac5165ea2c5e3ba74b39c7ac2ba Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:53:57 +0800 Subject: [PATCH 2/9] change(ble): Update lib_esp32c6 to 3422b706 (cherry picked from commit 4fc95fa91f178aeed607d0366e7b91a0ea018ac6) Co-authored-by: zhouxiao --- components/bt/controller/lib_esp32c6/esp32c6-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 2c3b919de8..04332117af 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 2c3b919de82278768a98f66c02c63a148026a613 +Subproject commit 04332117afd5d5ed479560f1191a816eceba34a2 From c2762f92067b1d52dda87b99ef6931571c495c5e Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:53:59 +0800 Subject: [PATCH 3/9] change(ble): Update lib_esp32c2 to 2a00fb0b (cherry picked from commit 7cd3fe6953ce455dcde3bc499d0f09a5c5cd57d7) Co-authored-by: zhouxiao --- components/bt/controller/lib_esp32c2/esp32c2-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index 339d66ea3d..c04f6f7c49 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit 339d66ea3dce6e97bee6ce41aa3d06761efcaad2 +Subproject commit c04f6f7c4958b7343acf1b1d0c3cc27a48b177a0 From 5095bba00016952f0ea5e523883636e51b2ed6a6 Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:54:01 +0800 Subject: [PATCH 4/9] feat(ble): support for putting ble code into flash on ESP32-H2 (cherry picked from commit 5a9acdc379ac2ed560ac6e92ddcc89696eaea6f5) Co-authored-by: zwl --- components/bt/controller/esp32h2/Kconfig.in | 8 ++++++++ components/bt/controller/esp32h2/bt.c | 18 ++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/components/bt/controller/esp32h2/Kconfig.in b/components/bt/controller/esp32h2/Kconfig.in index 4b281d029c..c8936bdbec 100644 --- a/components/bt/controller/esp32h2/Kconfig.in +++ b/components/bt/controller/esp32h2/Kconfig.in @@ -698,3 +698,11 @@ config BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS Enabling this option will add stricter verification of the Access Address in the CONNECT_IND PDU. This improves security by ensuring that only connection requests with valid Access Addresses are accepted. If disabled, only basic checks are applied, improving compatibility. + +config BT_CTRL_RUN_IN_FLASH_ONLY + bool "Reduce BLE IRAM usage (READ DOCS FIRST) (EXPERIMENTAL)" + default n + help + Move most IRAM into flash. This will increase the usage of flash and reduce ble performance. + Because the code is moved to the flash, the execution speed of the code is reduced. + To have a small impact on performance, you need to enable flash suspend (SPI_FLASH_AUTO_SUSPEND). diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index c8805228d2..1c55b0e6f0 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -125,6 +125,10 @@ extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, extern void r_ble_rtc_wake_up_state_clr(void); extern int os_msys_init(void); extern void os_msys_deinit(void); +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY +extern void r_ble_ll_scan_start_time_init_compensation(uint32_t init_compensation); +extern void r_priv_sdk_config_insert_proc_time_set(uint16_t insert_proc_time); +#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY #if CONFIG_FREERTOS_USE_TICKLESS_IDLE extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); @@ -495,8 +499,11 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in) { - int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, - arg, (intr_handle_t *)ret_handle_in); +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY + int rc = esp_intr_alloc(source, flags, handler, arg, (intr_handle_t *)ret_handle_in); +#else + int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in); +#endif return rc; } @@ -1020,7 +1027,10 @@ esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) #if CONFIG_SW_COEXIST_ENABLE coex_enable(); #endif // CONFIG_SW_COEXIST_ENABLE - +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY + r_ble_ll_scan_start_time_init_compensation(500); + r_priv_sdk_config_insert_proc_time_set(500); +#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY if (r_ble_controller_enable(mode) != 0) { ret = ESP_FAIL; goto error; From bfcb67058a979b58681ed8865a93322f44d3efd0 Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:54:03 +0800 Subject: [PATCH 5/9] fix(ble): fixed esp_ble_tx_power_set api issue on ESP32-C2 (cherry picked from commit 6a752eeb89a48ee5c1d5e07b8f2ea297ca1c268d) Co-authored-by: zwl --- components/bt/controller/esp32c2/bt.c | 32 +++++++++++++++++++++------ 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index f42246b72c..cdf88a2045 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1145,12 +1145,20 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ switch (power_type) { case ESP_BLE_PWR_TYPE_DEFAULT: - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; + case ESP_BLE_PWR_TYPE_ADV: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0xFF, power_level) == 0) { + stat = ESP_OK; + } + break; + case ESP_BLE_PWR_TYPE_SCAN: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1177,9 +1185,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type esp_err_t stat = ESP_FAIL; switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1202,11 +1214,15 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) int tx_level = 0; switch (power_type) { - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; + case ESP_BLE_PWR_TYPE_ADV: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0); + break; + case ESP_BLE_PWR_TYPE_SCAN: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1235,9 +1251,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: From 502648625e8346ec51777bc5185164f428b62a29 Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:54:06 +0800 Subject: [PATCH 6/9] fix(ble): fixed esp_ble_tx_power_set api issue on ESP32-C6 (cherry picked from commit 8d6ec1283875d0ea1993473d078bbc2dad47be9d) Co-authored-by: zwl --- components/bt/controller/esp32c6/bt.c | 30 +++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index a64f033abe..ab9ae34a3b 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -1203,12 +1203,20 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ switch (power_type) { case ESP_BLE_PWR_TYPE_DEFAULT: - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; + case ESP_BLE_PWR_TYPE_ADV: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0xFF, power_level) == 0) { + stat = ESP_OK; + } + break; + case ESP_BLE_PWR_TYPE_SCAN: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1236,9 +1244,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type esp_err_t stat = ESP_FAIL; switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1261,11 +1273,15 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) int tx_level = 0; switch (power_type) { - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; + case ESP_BLE_PWR_TYPE_ADV: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0); + break; + case ESP_BLE_PWR_TYPE_SCAN: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1295,9 +1311,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: From 304c40c89a7dc40c9f6ccf1aef034df19efd946e Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:54:08 +0800 Subject: [PATCH 7/9] fix(ble): fixed esp_ble_tx_power_set api issue on ESP32-H2 (cherry picked from commit d2b62f21301f01f7585100c08551fdaa1b52ef5c) Co-authored-by: zwl --- components/bt/controller/esp32h2/bt.c | 30 +++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 1c55b0e6f0..f90c55e420 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -1191,12 +1191,20 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ switch (power_type) { case ESP_BLE_PWR_TYPE_DEFAULT: - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { stat = ESP_OK; } break; + case ESP_BLE_PWR_TYPE_ADV: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0xFF, power_level) == 0) { + stat = ESP_OK; + } + break; + case ESP_BLE_PWR_TYPE_SCAN: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1224,9 +1232,13 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type esp_err_t stat = ESP_FAIL; switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + stat = ESP_OK; + } + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0, power_level) == 0) { stat = ESP_OK; } break; @@ -1249,11 +1261,15 @@ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) int tx_level = 0; switch (power_type) { - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: case ESP_BLE_PWR_TYPE_DEFAULT: tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); break; + case ESP_BLE_PWR_TYPE_ADV: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_ADV, 0); + break; + case ESP_BLE_PWR_TYPE_SCAN: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); + break; case ESP_BLE_PWR_TYPE_CONN_HDL0: case ESP_BLE_PWR_TYPE_CONN_HDL1: case ESP_BLE_PWR_TYPE_CONN_HDL2: @@ -1283,9 +1299,11 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po switch (power_type) { case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + break; case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_SCAN, 0); break; case ESP_BLE_ENHANCED_PWR_TYPE_ADV: case ESP_BLE_ENHANCED_PWR_TYPE_CONN: From 16595a5a9a885ed903cd58afe2e3db4527623a2f Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Tue, 14 Jan 2025 14:54:10 +0800 Subject: [PATCH 8/9] fix(ble): fixed ld file for c2eco0 and c2eco4 (cherry picked from commit 937fe2a6e3102ff9a44da2e2288c7df7588a271c) Co-authored-by: zhouxiao --- components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld | 6 +++--- components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld index a71f2a1cf2..dbc528eaaf 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld @@ -192,7 +192,7 @@ r_ble_ll_conn_chk_csm_flags = 0x40000d48; r_ble_ll_conn_chk_phy_upd_start = 0x40000d4c; r_ble_ll_conn_comp_event_send = 0x40000d50; r_ble_ll_conn_connect_ind_pdu_make = 0x40000d54; -r_ble_ll_conn_create = 0x40000d58; +//r_ble_ll_conn_create = 0x40000d58; r_ble_ll_conn_create_cancel = 0x40000d5c; r_ble_ll_conn_created = 0x40000d60; r_ble_ll_conn_cth_flow_enable = 0x40000d64; @@ -322,7 +322,7 @@ r_ble_ll_event_dbuf_overflow = 0x40000f50; r_ble_ll_event_send = 0x40000f54; r_ble_ll_event_tx_pkt = 0x40000f58; r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c; -r_ble_ll_ext_conn_create = 0x40000f60; +//r_ble_ll_ext_conn_create = 0x40000f60; r_ble_ll_ext_scan_parse_adv_info = 0x40000f64; r_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68; r_ble_ll_flush_pkt_queue = 0x40000f6c; @@ -706,7 +706,7 @@ r_ble_lll_conn_process_in_isr = 0x40001550; r_ble_lll_conn_recv_ack = 0x40001554; r_ble_lll_conn_recv_valid_packet = 0x40001558; r_ble_lll_conn_reset_pending_sched = 0x4000155c; -r_ble_lll_conn_rx_pkt_isr = 0x40001560; +//r_ble_lll_conn_rx_pkt_isr = 0x40001560; r_ble_lll_conn_sched_next_anchor = 0x40001564; r_ble_lll_conn_sched_next_event = 0x40001568; r_ble_lll_conn_set_slave_flow_control = 0x4000156c; diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld index 52c45ef817..4a17dd1354 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld @@ -611,7 +611,7 @@ r_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638; r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c; r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640; r_ble_lll_rfmgmt_is_enabled = 0x40001660; -r_ble_lll_rfmgmt_release = 0x40001664; +//r_ble_lll_rfmgmt_release = 0x40001664; r_ble_lll_rfmgmt_scan_changed = 0x40001670; r_ble_lll_rfmgmt_sched_changed = 0x40001674; r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; From 565c4d0b73d7b8e85b748908b034bfb73e0fa131 Mon Sep 17 00:00:00 2001 From: zwl Date: Fri, 3 Jan 2025 16:46:58 +0800 Subject: [PATCH 9/9] feat(ble): support for putting ble code into flash on ESP32-C6 --- components/bt/CMakeLists.txt | 2 +- components/bt/controller/esp32c6/Kconfig.in | 8 ++++++++ components/bt/controller/esp32c6/bt.c | 20 +++++++++++++++----- components/bt/linker_esp_ble_controller.lf | 14 +++++++++++++- 4 files changed, 37 insertions(+), 7 deletions(-) diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 8f1fc2f529..0c44bf8128 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -893,7 +893,7 @@ if(CONFIG_BT_ENABLED) if(CONFIG_IDF_TARGET_ESP32C6) add_prebuilt_library(libble_app "controller/lib_${target}/${target}-bt-lib/esp32c6/libble_app.a") else() - if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY) + if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY AND CONFIG_IDF_TARGET_ESP32C2) add_prebuilt_library(libble_app "controller/lib_${target}/${target}-bt-lib/libble_app_flash.a") else() add_prebuilt_library(libble_app "controller/lib_${target}/${target}-bt-lib/libble_app.a") diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in index 421b4f5917..12db967d04 100644 --- a/components/bt/controller/esp32c6/Kconfig.in +++ b/components/bt/controller/esp32c6/Kconfig.in @@ -697,3 +697,11 @@ config BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS Enabling this option will add stricter verification of the Access Address in the CONNECT_IND PDU. This improves security by ensuring that only connection requests with valid Access Addresses are accepted. If disabled, only basic checks are applied, improving compatibility. + +config BT_CTRL_RUN_IN_FLASH_ONLY + bool "Reduce BLE IRAM usage (READ DOCS FIRST) (EXPERIMENTAL)" + default n + help + Move most IRAM into flash. This will increase the usage of flash and reduce ble performance. + Because the code is moved to the flash, the execution speed of the code is reduced. + To have a small impact on performance, you need to enable flash suspend (SPI_FLASH_AUTO_SUSPEND). diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index ab9ae34a3b..6da8876982 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -131,6 +131,10 @@ extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, extern void r_ble_rtc_wake_up_state_clr(void); extern int os_msys_init(void); extern void os_msys_deinit(void); +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY +extern void r_ble_ll_scan_start_time_init_compensation(uint32_t init_compensation); +extern void r_priv_sdk_config_insert_proc_time_set(uint16_t insert_proc_time); +#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY #if CONFIG_FREERTOS_USE_TICKLESS_IDLE extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra); extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead); @@ -495,11 +499,13 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer return rc; } -static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, - void *arg, void **ret_handle_in) +static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in) { - int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, - arg, (intr_handle_t *)ret_handle_in); +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY + int rc = esp_intr_alloc(source, flags, handler, arg, (intr_handle_t *)ret_handle_in); +#else + int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in); +#endif return rc; } @@ -1043,6 +1049,10 @@ esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) coex_enable(); #endif // CONFIG_SW_COEXIST_ENABLE +#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY + r_ble_ll_scan_start_time_init_compensation(500); + r_priv_sdk_config_insert_proc_time_set(500); +#endif // CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY if (r_ble_controller_enable(mode) != 0) { ret = ESP_FAIL; goto error; diff --git a/components/bt/linker_esp_ble_controller.lf b/components/bt/linker_esp_ble_controller.lf index d6bd1df10c..0af407f8eb 100644 --- a/components/bt/linker_esp_ble_controller.lf +++ b/components/bt/linker_esp_ble_controller.lf @@ -1,8 +1,21 @@ +[sections:bt_iram_text] +entries: + .iram1+ + +[sections:high_perf_iram_text] +entries: + .high_perf_code_iram1+ + [scheme:bt_default] entries: bt_bss -> dram0_bss bt_common -> dram0_bss data -> dram0_data + high_perf_iram_text -> iram0_text + if BT_CTRL_RUN_IN_FLASH_ONLY = y: + bt_iram_text -> flash_text + else: + bt_iram_text -> iram0_text # For the following fragments, order matters for # 'ALIGN(4) ALIGN(4, post) SURROUND(sym)', which generates: @@ -27,7 +40,6 @@ entries: bt_common -> dram0_bss ALIGN(4) ALIGN(4, post) SURROUND(bt_common), data -> dram0_data ALIGN(4) ALIGN(4, post) SURROUND(bt_data) - [mapping:ble_app] archive: libble_app.a entries: