Merge branch 'bugfix/esp32s3_lightsleep_psram_leakage_current_v4.3' into 'release/v4.3'

backport v4.3: fix SPIRAM leakage when its CS pin has no hardware pullup

See merge request espressif/esp-idf!15224

components/bootloader_support/include/bootloader_common.h

@@ -105,6 +105,15 @@ bool bootloader_common_label_search(const char *list, char *label);
  */
 void bootloader_configure_spi_pins(int drv);
 
+/**
+ * @brief Get flash CS IO
+ *
+ * Can be determined by eFuse values, or the default value
+ *
+ * @return Flash CS IO
+ */
+uint8_t bootloader_flash_get_cs_io(void);
+
 /**
  * @brief Calculates a sha-256 for a given partition or returns a appended digest.
  *

components/bootloader_support/src/bootloader_common.c

@@ -29,6 +29,7 @@
 #include "esp_rom_crc.h"
 #include "esp_rom_gpio.h"
 #include "esp_rom_sys.h"
+#include "esp_rom_efuse.h"
 #include "esp_flash_partitions.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_common.h"
@@ -192,8 +193,19 @@ void bootloader_common_vddsdio_configure(void)
 #endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
 }
 
-
 RESET_REASON bootloader_common_get_reset_reason(int cpu_no)
 {
     return rtc_get_reset_reason(cpu_no);
 }
+
+uint8_t bootloader_flash_get_cs_io(void)
+{
+    uint8_t cs_io;
+    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+    if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
+        cs_io = SPI_CS0_GPIO_NUM;
+    } else {
+        cs_io = (spiconfig >> 18) & 0x3f;
+    }
+    return cs_io;
+}

components/esp32/include/esp32/spiram.h

@@ -89,6 +89,15 @@ size_t esp_spiram_get_size(void);
  */
 void esp_spiram_writeback_cache(void);
 
+/**
+ * @brief get psram CS IO
+ *
+ * This interface should be called after PSRAM is enabled, otherwise it will
+ * return an invalid value -1/0xff.
+ *
+ * @return psram CS IO or -1/0xff if psram not enabled
+ */
+uint8_t esp_spiram_get_cs_io(void);
 
 
 /**

components/esp32/spiram.c

@@ -296,4 +296,8 @@ bool esp_spiram_is_initialized(void)
     return spiram_inited;
 }
 
+uint8_t esp_spiram_get_cs_io(void)
+{
+    return psram_get_cs_io();
+}
 #endif

components/esp32/spiram_psram.c

@@ -203,6 +203,13 @@ typedef struct {
 
 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
 
+static uint8_t s_psram_cs_io = (uint8_t)-1;
+
+uint8_t psram_get_cs_io(void)
+{
+    return s_psram_cs_io;
+}
+
 static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
 {
     int i;
@@ -844,6 +851,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
         ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
         abort();
     }
+    s_psram_cs_io = psram_io.psram_cs_io;
 
     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
     if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {

components/esp32/spiram_psram.h

@@ -67,4 +67,11 @@ psram_size_t psram_get_size(void);
  */
 esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
 
+/**
+ * @brief get psram CS IO
+ *
+ * @return psram CS IO
+ */
+uint8_t psram_get_cs_io(void);
+
 #endif

components/esp32s2/include/esp32s2/spiram.h

@@ -78,6 +78,15 @@ size_t esp_spiram_get_size(void);
  */
 void esp_spiram_writeback_cache(void);
 
+/**
+ * @brief get psram CS IO
+ *
+ * This interface should be called after PSRAM is enabled, otherwise it will
+ * return an invalid value -1/0xff.
+ *
+ * @return psram CS IO or -1/0xff if psram not enabled
+ */
+uint8_t esp_spiram_get_cs_io(void);
 
 
 /**

components/esp32s2/spiram.c

@@ -376,6 +376,11 @@ void IRAM_ATTR esp_spiram_writeback_cache(void)
 
 
 
+uint8_t esp_spiram_get_cs_io(void)
+{
+    return psram_get_cs_io();
+}
+
 /*
  Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
  true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
@@ -414,4 +419,5 @@ bool esp_spiram_test(void)
         return true;
     }
 }
+
 #endif

components/esp32s2/spiram_psram.c

@@ -168,6 +168,13 @@ static uint32_t s_psram_id = 0;
 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
 extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
 
+static uint8_t s_psram_cs_io = (uint8_t)-1;
+
+uint8_t psram_get_cs_io(void)
+{
+    return s_psram_cs_io;
+}
+
 static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
 {
     if (mode == PSRAM_CMD_QPI) {
@@ -375,6 +382,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
         psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio();
     }
     esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
+    s_psram_cs_io = psram_io.psram_cs_io;
 }
 
 psram_size_t psram_get_size(void)

components/esp32s2/spiram_psram.h

@@ -76,5 +76,11 @@ typedef enum {
 
 esp_err_t esp_spiram_wrap_set(spiram_wrap_mode_t mode);
 
+/**
+ * @brief get psram CS IO
+ *
+ * @return psram CS IO
+ */
+uint8_t psram_get_cs_io(void);
 
 #endif

components/esp_system/Kconfig

@@ -100,6 +100,23 @@ menu "ESP System Settings"
             If enabled, the CPU will be powered down in light sleep. Enabling this option will consume
             1.68 KB of internal RAM and will reduce sleep current consumption by about 100 uA.
 
+    config ESP_SYSTEM_PSRAM_LEAKAGE_WORKAROUND
+        bool "PSRAM leakage current workaround in light sleep"
+        depends on SPIRAM
+        help
+            When the CS pin of SPIRAM is not pulled up, the sleep current will
+            increase during light sleep. If the CS pin of SPIRAM has an external
+            pull-up, you do not need to select this option, otherwise, you
+            should enable this option.
+
+    config ESP_SYSTEM_FLASH_LEAKAGE_WORKAROUND
+        bool "Flash leakage current workaround in light sleep"
+        help
+            When the CS pin of Flash is not pulled up, the sleep current will
+            increase during light sleep. If the CS pin of Flash has an external
+            pull-up, you do not need to select this option, otherwise, you
+            should enable this option.
+
     menu "Memory protection"
 
         config ESP_SYSTEM_MEMPROT_FEATURE

components/esp_system/sleep_modes.c

@@ -29,6 +29,7 @@
 #include "soc/soc_caps.h"
 #include "driver/rtc_io.h"
 #include "hal/rtc_io_hal.h"
+#include "bootloader_common.h"
 
 #include "driver/uart.h"
 
@@ -53,6 +54,7 @@
 #include "esp32/clk.h"
 #include "esp32/rom/rtc.h"
 #include "esp_private/gpio.h"
+#include "esp32/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/clk.h"
 #include "esp32s2/rom/cache.h"
@@ -60,11 +62,13 @@
 #include "esp32s2/brownout.h"
 #include "soc/extmem_reg.h"
 #include "esp_private/gpio.h"
+#include "esp32s2/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"
 #include "soc/extmem_reg.h"
+#include "esp32s3/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
 #include "esp32c3/rom/cache.h"
@@ -418,6 +422,12 @@ void esp_sleep_config_gpio_isolate(void)
             gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
         }
     }
+#if CONFIG_ESP_SYSTEM_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
+    gpio_sleep_set_pull_mode(esp_spiram_get_cs_io(), GPIO_PULLUP_ONLY);
+#endif
+#if CONFIG_ESP_SYSTEM_FLASH_LEAKAGE_WORKAROUND
+    gpio_sleep_set_pull_mode(bootloader_flash_get_cs_io(), GPIO_PULLUP_ONLY);
+#endif
 }
 
 void esp_sleep_enable_gpio_switch(bool enable)