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feat(esp32h21): support GPIO on esp32h21

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This commit is contained in:
gaoxu 2025-02-17 15:19:10 +08:00
parent 046279155d
commit 760f134d84
16 changed files with 357 additions and 127 deletions
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7
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -535,6 +535,9 @@ TEST_CASE("GPIO_set_output_level_get_input_level_test", "[gpio]")
TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "get level error! the level should be high!");
}
#if !CONFIG_IDF_ENV_FPGA
// On FPGA do not support GPIO pull down
// This test routes constant-high/low signal to pins, another way is to directly connect TEST_GPIO_EXT_IN_IO to
// 3.3v or GND pin
TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
@ -662,6 +665,8 @@ TEST_CASE("GPIO_mode_test", "[gpio]")
TEST_ASSERT_EQUAL_INT_MESSAGE(!level, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT set error, it gives incorrect output");
}
#endif //!CONFIG_IDF_ENV_FPGA
static void prompt_to_continue(const char *str)
{
printf("%s , please press \"Enter\" to go on!\n", str);

38
components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,8 +10,6 @@
#include <stdbool.h>
#include "soc/gpio_reg.h"
//TODO: [ESP32H21] IDF-11611
#ifdef __cplusplus
extern "C" {
#endif
@ -30,7 +28,6 @@ extern "C" {
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
//TODO: [ESP32H21] IDF-11611, need check
#define GPIO_FUNC_IN_HIGH 0x20
#define GPIO_FUNC_IN_LOW 0x30
@ -50,7 +47,7 @@ typedef enum {
/**
* @brief Change GPIO(0-27) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* @brief Change GPIO(0-25) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@ -67,7 +64,7 @@ typedef enum {
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-27) and returns a bitmask.
* @brief Sample the value of GPIO input pins(0-25) and returns a bitmask.
*
* @param None
*
@ -76,7 +73,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
uint32_t gpio_input_get(void);
/**
* @brief Set GPIO to wakeup the ESP32.
* @brief Set GPIO to wakeup the ESP32H21.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
@ -88,7 +85,7 @@ uint32_t gpio_input_get(void);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* @brief disable GPIOs to wakeup the ESP32H21.
* Please do not call this function in SDK.
*
* @param None
@ -100,10 +97,9 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~27
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
* @param uint32_t gpio : gpio number, 0~25
* gpio == 0x30, input 0 to signal
* gpio == 0x20, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
@ -116,7 +112,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~27
* @param uint32_t gpio : gpio number, 0~25
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x80, cancel output put to the gpio
@ -132,7 +128,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -141,7 +137,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @param uint32_t drv : 0-3
*
@ -152,7 +148,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -161,7 +157,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -170,7 +166,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -179,7 +175,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -188,7 +184,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/
@ -197,7 +193,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~27
* @param uint32_t gpio_num : gpio number, 0~25
*
* @return None
*/

4
components/hal/esp32h21/clk_tree_hal.c
View File

@ -80,10 +80,10 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
abort(); // TODO: IDF-11582
}
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
{
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
abort(); // TODO: IDF-11582
}

29
components/hal/esp32h21/include/hal/gpio_ll.h
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@ -28,8 +28,6 @@
#include "hal/misc.h"
#include "hal/assert.h"
//TODO: [ESP32H21] IDF-11611, inherit from h2
#ifdef __cplusplus
extern "C" {
#endif
@ -116,7 +114,6 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
{
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
}
@ -309,8 +306,6 @@ __attribute__((always_inline))
static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
{
hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
// Ensure no other output signal is routed via GPIO matrix to this pin
REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX);
}
/**
@ -356,10 +351,10 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
{
// gpio_func_out_sel_cfg_reg_t reg = {
// .out_sel = SIG_GPIO_OUT_IDX,
// };
// hw->func_out_sel_cfg[gpio_num].val = reg.val;
gpio_funcn_out_sel_cfg_reg_t reg = {
.funcn_out_sel = SIG_GPIO_OUT_IDX,
};
hw->funcn_out_sel_cfg[gpio_num].val = reg.val;
}
/**
@ -530,19 +525,6 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
}
/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
}
/**
* @brief Set clock source of IO MUX module
*
@ -554,6 +536,9 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
case SOC_MOD_CLK_RC_FAST:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
case SOC_MOD_CLK_PLL_F48M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;

1
components/soc/esp32c5/register/soc/io_mux_reg.h
View File

@ -129,7 +129,6 @@ extern "C" {
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_HD_GPIO_NUM 20
#define SPI_WP_GPIO_NUM 18

8
components/soc/esp32h21/gpio_periph.c
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@ -1,15 +1,11 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
//TODO: [ESP32H21] IDF-11611
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
BIT(1), //GPIO1
@ -37,8 +33,6 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
BIT(27), //GPIO27
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

16
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
View File

@ -233,7 +233,11 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 28
default 26
config SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
@ -245,15 +249,19 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
config SOC_GPIO_IN_RANGE_MAX
int
default 27
default 25
config SOC_GPIO_OUT_RANGE_MAX
int
default 27
default 25
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F
default 0x0000000003FFF81F
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int

2
components/soc/esp32h21/include/soc/gpio_num.h
View File

@ -41,8 +41,6 @@ typedef enum {
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

2
components/soc/esp32h21/include/soc/gpio_pins.h
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@ -10,10 +10,8 @@
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11611
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#define GPIO_MATRIX_INVALID (0x3A)
#ifdef __cplusplus
}

24
components/soc/esp32h21/include/soc/soc_caps.h
View File

@ -188,17 +188,17 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H21 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 28
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// #define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 26
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
// Target has no full LP IO subsystem, GPIO5~11 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
// Digital IOs have their own registers to control pullup/down/capability
// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
@ -209,14 +209,14 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 27
#define SOC_GPIO_OUT_RANGE_MAX 27
#define SOC_GPIO_IN_RANGE_MAX 25
#define SOC_GPIO_OUT_RANGE_MAX 25
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~4. GPIO_NUM_12~25)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000003FFF81FULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

2
components/soc/esp32h21/register/soc/gpio_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

47
components/soc/esp32h21/register/soc/io_mux_reg.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -108,10 +108,6 @@
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL)
#define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL)
#define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN)
#define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_MTMS
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_MTDO
@ -140,25 +136,14 @@
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_SPID
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U0RXD_GPIO_NUM 15
#define U0TXD_GPIO_NUM 16
#define SPI_HD_GPIO_NUM 23
#define SPI_WP_GPIO_NUM 22
#define SPI_CS0_GPIO_NUM 20
#define SPI_CLK_GPIO_NUM 24
#define SPI_D_GPIO_NUM 25
#define SPI_Q_GPIO_NUM 21
#define USB_INT_PHY0_DM_GPIO_NUM 26
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define USB_INT_PHY0_DM_GPIO_NUM 17
#define USB_INT_PHY0_DP_GPIO_NUM 18
#define EXT_OSC_SLOW_GPIO_NUM 13
@ -168,33 +153,7 @@
#define MAX_GPIO_NUM 29
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define GPIO_NUM_IN_INVALID 0x28
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 IO_MUX_CLK_OUT3
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
#define CLK_OUT2 IO_MUX_CLK_OUT2
#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
#define CLK_OUT1 IO_MUX_CLK_OUT1
#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x0)

147
docs/en/api-reference/peripherals/gpio/esp32h21.inc
View File

@ -9,10 +9,153 @@
.. gpio-summary
To be updated
The {IDF_TARGET_NAME} chip features 26 physical GPIO pins (GPIO0 ~ GPIO25). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- Analog Function
- LP GPIO
- Comments
* - GPIO0
-
-
- Strapping pin
* - GPIO1
- ADC1_CH0
-
- Strapping pin
* - GPIO2
- ADC1_CH1
-
-
* - GPIO3
- ADC1_CH2
-
-
* - GPIO4
- ADC1_CH3
-
-
* - GPIO5
- ADC1_CH4
- LP_GPIO0
-
* - GPIO6
-
- LP_GPIO1
-
* - GPIO7
-
- LP_GPIO2
-
* - GPIO8
-
- LP_GPIO3
-
* - GPIO9
-
- LP_GPIO4
-
* - GPIO10
-
- LP_GPIO5
-
* - GPIO11
-
- LP_GPIO6
-
* - GPIO12
-
-
-
* - GPIO13
-
-
- Strapping pin
* - GPIO14
-
-
- Strapping pin
* - GPIO15
-
-
-
* - GPIO16
-
-
-
* - GPIO17
-
-
- USB-JTAG
* - GPIO18
-
-
- USB-JTAG
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
* - GPIO22
-
-
- SPI0/1
* - GPIO23
-
-
- SPI0/1
* - GPIO24
-
-
- SPI0/1
* - GPIO25
-
-
- SPI0/1
.. note::
To be updated
- Strapping pin: GPIO0, GPIO1, GPIO13, and GPIO14 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- SPI0/1: GPIO19 ~ GPIO25 are usually used for SPI flash and not recommended for other uses.
- USB-JTAG: GPIO17 and GPIO18 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.
---

147
docs/zh_CN/api-reference/peripherals/gpio/esp32h21.inc
View File

@ -9,10 +9,153 @@
.. gpio-summary
To be updated
{IDF_TARGET_NAME} 芯片具有 26 个物理 GPIO 管脚（GPIO0 ~ GPIO25）。每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- 模拟功能
- LP GPIO
- 注释
* - GPIO0
-
-
- Strapping 管脚
* - GPIO1
- ADC1_CH0
-
- Strapping 管脚
* - GPIO2
- ADC1_CH1
-
-
* - GPIO3
- ADC1_CH2
-
-
* - GPIO4
- ADC1_CH3
-
-
* - GPIO5
- ADC1_CH4
- LP_GPIO0
-
* - GPIO6
-
- LP_GPIO1
-
* - GPIO7
-
- LP_GPIO2
-
* - GPIO8
-
- LP_GPIO3
-
* - GPIO9
-
- LP_GPIO4
-
* - GPIO10
-
- LP_GPIO5
-
* - GPIO11
-
- LP_GPIO6
-
* - GPIO12
-
-
-
* - GPIO13
-
-
- Strapping 管脚
* - GPIO14
-
-
- Strapping 管脚
* - GPIO15
-
-
-
* - GPIO16
-
-
-
* - GPIO17
-
-
- USB-JTAG
* - GPIO18
-
-
- USB-JTAG
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
* - GPIO22
-
-
- SPI0/1
* - GPIO23
-
-
- SPI0/1
* - GPIO24
-
-
- SPI0/1
* - GPIO25
-
-
- SPI0/1
.. note::
To be updated
- Strapping 管脚：GPIO0、GPIO1、GPIO13 和 GPIO14 是 Strapping 管脚。更多信息请参考 `ESP32-H21 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- SPI0/1：GPIO19 ~ GPIO25 通常用于 SPI flash，不推荐用于其他用途。
- USB-JTAG：GPIO17 和 GPIO18 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。
---

8
examples/peripherals/gpio/generic_gpio/README.md
View File

@ -23,10 +23,10 @@ This test code shows how to configure GPIO and how to use it with interruption.
**Note:** The following pin assignments are used by default, you can change them by `idf.py menuconfig` > `Example Configuration`.
| | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 |
| ---------------------- | -------------------- | -------------------- | ------------------- | ------------------- |
| ESP32C2/ESP32H2 | 8 | 9 | 4 | 5 |
| All other chips | 18 | 19 | 4 | 5 |
| | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 |
| ------------------------- | -------------------- | -------------------- | ------------------- | ------------------- |
| ESP32C2/H2/C5/C61/H21 | 8 | 9 | 4 | 5 |
| All other chips | 18 | 19 | 4 | 5 |
## How to use example

2
examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild
View File

@ -6,6 +6,7 @@ menu "Example Configuration"
int "GPIO output pin 0"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
default 8 if IDF_TARGET_ESP32H21
default 18
help
GPIO pin number to be used as GPIO_OUTPUT_IO_0.
@ -14,6 +15,7 @@ menu "Example Configuration"
int "GPIO output pin 1"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
default 9 if IDF_TARGET_ESP32H21
default 19
help
GPIO pin number to be used as GPIO_OUTPUT_IO_1.