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Merge branch 'fix/remove_gpio_hal_iomux_func_sel' into 'master'

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fix(driver_gpio): remove gpio_hal_iomux_func_sel

See merge request espressif/esp-idf!33928
This commit is contained in:
Wan Lei 2025-02-20 18:52:35 +08:00
commit 76133bc373
19 changed files with 44 additions and 216 deletions
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30
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
View File

@ -93,7 +93,7 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
// For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
// flash clock signal should come from IO MUX.
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
} else {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
@ -108,14 +108,14 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
//select pin function gpio
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIQ_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPID_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIHD_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIWP_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_CS_IO, PIN_FUNC_GPIO);
// flash clock signal should come from IO MUX.
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
// set drive ability for clock
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
uint32_t flash_id = g_rom_flashchip.device_id;
@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
return ESP32_PICO_V3_GPIO;
default:
return MSPI_IOMUX_PIN_NUM_WP;
return FLASH_SPIWP_IO;
}
#endif
}
@ -207,7 +207,7 @@ void bootloader_configure_spi_pins(int drv)
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
// For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
// flash clock signal should come from IO MUX.
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
} else {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
@ -222,14 +222,14 @@ void bootloader_configure_spi_pins(int drv)
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
//select pin function gpio
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIQ_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPID_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIHD_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_SPIWP_IO, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, FLASH_CS_IO, PIN_FUNC_GPIO);
// flash clock signal should come from IO MUX.
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
// set drive ability for clock
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64

3
components/esp_driver_dac/test_apps/dac/main/test_dac.c
View File

@ -12,6 +12,7 @@
#include "driver/dac_cosine.h"
#include "driver/dac_continuous.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_err.h"
#if CONFIG_IDF_TARGET_ESP32
@ -253,7 +254,7 @@ TEST_CASE("DAC_dma_convert_frequency_test", "[dac]")
TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
// Connect the clock signal to pcnt input signal
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[GPIO_NUM_4], PIN_FUNC_GPIO);
gpio_func_sel(GPIO_NUM_4, PIN_FUNC_GPIO);
gpio_set_direction(GPIO_NUM_4, GPIO_MODE_INPUT_OUTPUT);
// The DAC conversion frequency is equal to I2S bclk.
esp_rom_gpio_connect_out_signal(GPIO_NUM_4, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);

12
components/esp_driver_sdio/src/sdio_slave.c
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@ -89,6 +89,7 @@ The driver of FIFOs works as below:
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/gpio.h"
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#include "esp_private/sleep_retention.h"
#endif
@ -283,15 +284,12 @@ no_mem:
static void configure_pin(int pin, uint32_t func, bool pullup)
{
const int sdmmc_func = func;
const int drive_strength = 3;
assert(pin != -1);
uint32_t reg = GPIO_PIN_MUX_REG[pin];
assert(reg != UINT32_MAX);
PIN_INPUT_ENABLE(reg);
gpio_hal_iomux_func_sel(reg, sdmmc_func);
PIN_SET_DRV(reg, drive_strength);
gpio_input_enable(pin);
gpio_func_sel(pin, func);
gpio_set_drive_capability(pin, drive_strength);
gpio_pulldown_dis(pin);
if (pullup) {
gpio_pullup_en(pin);
@ -333,7 +331,7 @@ static void recover_pin(int pin, int sdio_func)
int func = REG_GET_FIELD(reg, MCU_SEL);
if (func == sdio_func) {
gpio_set_direction(pin, GPIO_MODE_INPUT);
gpio_hal_iomux_func_sel(reg, PIN_FUNC_GPIO);
gpio_func_sel(pin, PIN_FUNC_GPIO);
}
}

13
components/esp_driver_sdmmc/src/sdmmc_host.c
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@ -17,6 +17,7 @@
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "driver/sdmmc_host.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/periph_ctrl.h"
@ -557,16 +558,12 @@ esp_err_t sdmmc_host_init(void)
static void configure_pin_iomux(uint8_t gpio_num)
{
const int sdmmc_func = SDMMC_LL_IOMUX_FUNC;
const int drive_strength = 3;
assert(gpio_num != (uint8_t) GPIO_NUM_NC);
gpio_pulldown_dis(gpio_num);
uint32_t reg = GPIO_PIN_MUX_REG[gpio_num];
assert(reg != UINT32_MAX);
PIN_INPUT_ENABLE(reg);
gpio_hal_iomux_func_sel(reg, sdmmc_func);
PIN_SET_DRV(reg, drive_strength);
gpio_pulldown_dis(gpio_num);
gpio_input_enable(gpio_num);
gpio_iomux_output(gpio_num, SDMMC_LL_IOMUX_FUNC, false);
gpio_set_drive_capability(gpio_num, 3);
}
static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name)

7
components/esp_hw_support/esp_clock_output.c
View File

@ -8,6 +8,7 @@
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_clock_output.h"
#include "esp_check.h"
#include "esp_rom_gpio.h"
@ -140,10 +141,10 @@ static esp_clock_output_mapping_t* clkout_mapping_alloc(clkout_channel_handle_t*
allocated_mapping->ref_cnt++;
if (allocated_mapping->ref_cnt == 1) {
#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], CLKOUT_CHANNEL_TO_IOMUX_FUNC(allocated_mapping->clkout_channel_hdl->channel_id));
gpio_iomux_output(gpio_num, CLKOUT_CHANNEL_TO_IOMUX_FUNC(allocated_mapping->clkout_channel_hdl->channel_id), false);
#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
gpio_set_pull_mode(gpio_num, GPIO_FLOATING);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(gpio_num, CLKOUT_CHANNEL_TO_GPIO_SIG_ID(allocated_mapping->clkout_channel_hdl->channel_id), false, false);
#endif
}
@ -173,8 +174,6 @@ static void clkout_mapping_free(esp_clock_output_mapping_t *mapping_hdl)
clkout_channel_free(mapping_hdl->clkout_channel_hdl);
bool do_free_mapping_hdl = false;
if (--mapping_hdl->ref_cnt == 0) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[mapping_hdl->mapped_io], PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(mapping_hdl->mapped_io, SIG_GPIO_OUT_IDX, false, false);
gpio_output_disable(mapping_hdl->mapped_io);
portENTER_CRITICAL(&mapping_hdl->clkout_channel_hdl->clkout_channel_lock);

7
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c
View File

@ -8,10 +8,11 @@
#include "freertos/task.h"
#include "unity.h"
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_err.h"
#include "esp_clock_output.h"
#include "hal/gpio_hal.h"
#include "soc/uart_pins.h"
#include "soc/rtc.h"
#define TEST_LOOPS 100
@ -98,8 +99,8 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
#if CONFIG_IDF_TARGET_ESP32
/* ESP32 clock out channel pin reuses UART TX/RX pin, restore its default
configuration at the end of the test */
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
gpio_iomux_output(U0RXD_GPIO_NUM, FUNC_U0RXD_U0RXD, false);
gpio_iomux_output(U0TXD_GPIO_NUM, FUNC_U0TXD_U0TXD, false);
#endif
}

19
components/esp_psram/esp32/esp_psram_impl_quad.c
View File

@ -803,18 +803,19 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_
//select pin function gpio
if ((psram_io->flash_clk_io == MSPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
//flash clock signal should come from IO MUX.
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
gpio_ll_func_sel(&GPIO, psram_io->flash_clk_io, MSPI_FUNC_NUM);
} else {
//flash clock signal should come from GPIO matrix.
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->flash_clk_io, PIN_FUNC_GPIO);
}
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->flash_cs_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_cs_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_clk_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_spiq_sd0_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_spid_sd1_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_spihd_sd2_io, PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, psram_io->psram_spiwp_sd3_io, PIN_FUNC_GPIO);
uint32_t flash_id = g_rom_flashchip.device_id;
if (flash_id == FLASH_ID_GD25LQ32C) {

12
components/hal/esp32/include/hal/gpio_ll.h
View File

@ -697,18 +697,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

12
components/hal/esp32c2/include/hal/gpio_ll.h
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@ -499,18 +499,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

16
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@ -499,22 +499,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

15
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -487,21 +487,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO13_REG || pin_name == IO_MUX_GPIO14_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Select a function for the pin in the IOMUX
*

15
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@ -458,21 +458,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

15
components/hal/esp32c61/include/hal/gpio_ll.h
View File

@ -487,21 +487,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Select a function for the pin in the IOMUX
*

15
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@ -504,21 +504,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Select a function for the pin in the IOMUX
*

15
components/hal/esp32h21/include/hal/gpio_ll.h
View File

@ -511,21 +511,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
// if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Select a function for the pin in the IOMUX
*

19
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -590,25 +590,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function
// P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
} else if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
USB_WRAP.otg_conf.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Select a function for the pin in the IOMUX
*

12
components/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -511,18 +511,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

15
components/hal/esp32s3/include/hal/gpio_ll.h
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@ -514,21 +514,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
}
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
__attribute__((always_inline))
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
if (pin_name == IO_MUX_GPIO19_REG || pin_name == IO_MUX_GPIO20_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*

8
components/hal/include/hal/gpio_hal.h
View File

@ -509,14 +509,6 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n
#define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) gpio_ll_deepsleep_wakeup_is_enabled((hal)->dev, gpio_num)
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED
/**
* @brief Select a function for the pin in the IOMUX
*
* @param pin_name Pin name to configure
* @param func Function to assign to the pin
*/
#define gpio_hal_iomux_func_sel(pin_name, func) gpio_ll_iomux_func_sel(pin_name, func)
#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
/**
* @brief Control gpio hysteresis enable/disable by software.