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Merge branch 'bugfix/esp32c5_eco1_wifi_ps' into 'master'

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fix some wifi power save issues and optimize phy sleep for esp32c5 eco1 and beta5

Closes PM-306, PM-319, PM-320, PM-296, PM-308, PM-311, PM-310, PM-309, PM-295, PM-274, PM-271, IDFCI-2604, and IDFCI-2605

See merge request espressif/esp-idf!35093
This commit is contained in:
Jiang Jiang Jian 2025-01-21 15:46:04 +08:00
commit 767545693a
24 changed files with 294 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
View File

@ -438,7 +438,7 @@ typedef struct pmu_sleep_machine_constant {
} lp;
struct {
uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */
uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
uint16_t clock_domain_sync_time_us; /* Synchronizing the rtc clock timer to modem system requires at least 1 us (unit: microsecond) */
uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */
uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */
uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */
@ -471,19 +471,19 @@ typedef struct pmu_sleep_machine_constant {
}, \
.hp = { \
.min_slp_time_us = 450, \
.clock_domain_sync_time_us = 150, \
.clock_domain_sync_time_us = 2, \
.system_dfs_up_work_time_us = 124, \
.analog_wait_time_us = 154, \
.isolate_wait_time_us = 1, \
.reset_wait_time_us = 1, \
.power_supply_wait_time_us = 2, \
.power_up_wait_time_us = 2, \
.regdma_s2m_work_time_us = 172, \
.regdma_s2a_work_time_us = 480, \
.regdma_m2a_work_time_us = 278, \
.regdma_a2s_work_time_us = 382, \
.regdma_rf_on_work_time_us = 70, \
.regdma_rf_off_work_time_us = 23, \
.regdma_s2m_work_time_us = 275, \
.regdma_s2a_work_time_us = 587, \
.regdma_m2a_work_time_us = 320, \
.regdma_a2s_work_time_us = 494, \
.regdma_rf_on_work_time_us = 60, \
.regdma_rf_off_work_time_us = 25, \
.xtal_wait_stable_time_us = 250, \
.pll_wait_stable_time_us = 300 \
} \

6
components/esp_hw_support/sleep_modes.c
View File

@ -674,6 +674,9 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s
}
#endif
#if CONFIG_MAC_BB_PD
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(false);
# endif
mac_bb_power_down_cb_execute();
#endif
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
@ -736,6 +739,9 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
#endif
#if CONFIG_MAC_BB_PD
mac_bb_power_up_cb_execute();
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(true);
# endif
#endif
#if REGI2C_ANA_CALI_PD_WORKAROUND
regi2c_analog_cali_reg_write();

9
components/esp_phy/CMakeLists.txt
View File

@ -101,6 +101,10 @@ if(CONFIG_ESP_PHY_ENABLED)
if(CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION)
idf_component_get_property(esp_common_dir esp_common COMPONENT_DIR)
idf_component_get_property(esp_rom_dir esp_rom COMPONENT_DIR)
idf_component_get_property(newlib_dir newlib COMPONENT_DIR)
idf_component_get_property(soc_dir soc COMPONENT_DIR)
idf_component_get_property(log_dir log COMPONENT_DIR)
partition_table_get_partition_info(phy_partition_offset
"--partition-type data --partition-subtype phy" "offset")
@ -118,8 +122,9 @@ if(CONFIG_ESP_PHY_ENABLED)
DEPENDS ${CMAKE_CURRENT_LIST_DIR}/${idf_target}/phy_init_data.c
COMMAND ${CMAKE_C_COMPILER} -c ${CMAKE_CURRENT_LIST_DIR}/${idf_target}/phy_init_data.c
-I ${esp_common_dir}/include -I ${CMAKE_CURRENT_LIST_DIR}/include
-I ${CMAKE_CURRENT_LIST_DIR}/${idf_target}/include
-I ${config_dir} -o phy_init_data.obj
-I ${CMAKE_CURRENT_LIST_DIR}/${idf_target}/include -I ${esp_rom_dir}/include
-I ${soc_dir}/${idf_target}/include -I ${newlib_dir}/platform_include
-I ${log_dir}/include -I ${config_dir} -o phy_init_data.obj
COMMAND ${CMAKE_OBJCOPY} -O binary phy_init_data.obj ${phy_init_data_bin}
)
add_custom_target(phy_init_data ALL DEPENDS ${phy_init_data_bin})

69
components/esp_phy/esp32c5/phy_init_data.c
View File

@ -5,7 +5,10 @@
*/
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "phy_init_data.h"
#include "esp_private/phy.h"
#include "esp_check.h"
const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC;
@ -273,3 +276,69 @@ const esp_phy_init_data_t phy_init_data= { {
} };
const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
#include "esp_private/sleep_retention.h"
static const char* TAG = "phy_sleep";
static esp_err_t sleep_retention_wifi_bb_init(void *arg)
{
#define N_REGS_WIFI_AGC() (126)
#define N_REGS_WIFI_TX() (20)
#define N_REGS_WIFI_NRX() (141)
#define N_REGS_WIFI_BB() (63)
#define N_REGS_WIFI_BRX() (39)
#define N_REGS_WIFI_FE_COEX() (19)
#define N_REGS_WIFI_FE_DATA() (31)
#define N_REGS_WIFI_FE_CTRL() (55)
const static sleep_retention_entries_config_t bb_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
[8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, 20, 0, 0), .owner = BIT(0) | BIT(1) } /* FE WIFI DATA */
};
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
ESP_LOGD(TAG, "WiFi BB sleep retention initialization");
return ESP_OK;
}
void esp_phy_sleep_data_init(void)
{
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = sleep_retention_wifi_bb_init, .arg = NULL } },
.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
};
esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
return;
}
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to allocate sleep retention linked list for wifi bb retention");
}
}
void esp_phy_sleep_data_deinit(void)
{
esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to free sleep retention linked list for wifi bb retention");
return;
}
err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
}
}
#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */

63
components/esp_phy/esp32c6/phy_init_data.c
View File

@ -5,7 +5,10 @@
*/
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "phy_init_data.h"
#include "esp_private/phy.h"
#include "esp_check.h"
const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC;
@ -144,3 +147,63 @@ const esp_phy_init_data_t phy_init_data= { {
} };
const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
#include "esp_private/sleep_retention.h"
static const char* TAG = "phy_sleep";
static esp_err_t sleep_retention_wifi_bb_init(void *arg)
{
#define N_REGS_WIFI_AGC() (121)
#define N_REGS_WIFI_TX() (14)
#define N_REGS_WIFI_NRX() (136)
#define N_REGS_WIFI_BB() (53)
#define N_REGS_WIFI_BRX() (39)
#define N_REGS_WIFI_FE_COEX() (58)
const static sleep_retention_entries_config_t bb_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
};
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
ESP_LOGD(TAG, "WiFi BB sleep retention initialization");
return ESP_OK;
}
void esp_phy_sleep_data_init(void)
{
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = sleep_retention_wifi_bb_init, .arg = NULL } },
.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
};
esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
return;
}
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to allocate sleep retention linked list for wifi bb retention");
}
}
void esp_phy_sleep_data_deinit(void)
{
esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to free sleep retention linked list for wifi bb retention");
return;
}
err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
}
}
#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */

68
components/esp_phy/esp32c61/phy_init_data.c
View File

@ -5,7 +5,10 @@
*/
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "phy_init_data.h"
#include "esp_private/phy.h"
#include "esp_check.h"
const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC;
@ -145,3 +148,68 @@ const esp_phy_init_data_t phy_init_data= { {
} };
const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
#include "esp_private/sleep_retention.h"
static const char* TAG = "phy_sleep";
static esp_err_t sleep_retention_wifi_bb_init(void *arg)
{
#define N_REGS_WIFI_AGC() (121)
#define N_REGS_WIFI_TX() (14)
#define N_REGS_WIFI_NRX() (136)
#define N_REGS_WIFI_BB() (53)
#define N_REGS_WIFI_BRX() (39)
#define N_REGS_WIFI_FE_COEX() (58)
#define N_REGS_WIFI_FE_DATA() (41)
#define N_REGS_WIFI_FE_CTRL() (87)
const static sleep_retention_entries_config_t bb_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, N_REGS_WIFI_TX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, N_REGS_WIFI_NRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, N_REGS_WIFI_BB(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, N_REGS_WIFI_FE_COEX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */
};
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
ESP_LOGD(TAG, "WiFi BB sleep retention initialization");
return ESP_OK;
}
void esp_phy_sleep_data_init(void)
{
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = sleep_retention_wifi_bb_init, .arg = NULL } },
.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
};
esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
return;
}
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to allocate sleep retention linked list for wifi bb retention");
}
}
void esp_phy_sleep_data_deinit(void)
{
esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to free sleep retention linked list for wifi bb retention");
return;
}
err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
}
}
#endif /* SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD */

13
components/esp_phy/include/esp_private/phy.h
View File

@ -8,6 +8,7 @@
#include <sys/lock.h>
#include "sdkconfig.h"
#include "esp_phy_init.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
@ -243,6 +244,18 @@ uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
void phy_wakeup_from_modem_state_extra_init(void);
#endif
#if SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_MAC_BB_PD
/**
* @brief PHY module sleep data (includes AGC, TX, NRX, BB, FE, etc..) initialize.
*/
void esp_phy_sleep_data_init(void);
/**
* @brief PHY module sleep data de-initialize.
*/
void esp_phy_sleep_data_deinit(void);
#endif
#ifdef __cplusplus
}
#endif

2
components/esp_phy/lib

@ -1 +1 @@
Subproject commit 1e3487dc778d48c15229af05ce0f03f78e15528c
Subproject commit 7114c37cbc163e373e8dd4a7ecfdeacddc9fa8c2

2
components/esp_phy/linker.lf
View File

@ -29,3 +29,5 @@ entries:
phy_init:esp_phy_enable (noflash)
phy_init:esp_phy_disable (noflash)
phy_init:esp_wifi_bt_power_domain_off (noflash)
if PM_SLP_IRAM_OPT = y:
phy_override:phy_get_tsens_value (noflash)

48
components/esp_phy/src/phy_init.c
View File

@ -50,10 +50,6 @@
#endif
#include "hal/efuse_hal.h"
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
#include "esp_private/sleep_retention.h"
#endif
#if CONFIG_IDF_TARGET_ESP32
extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
#endif
@ -484,26 +480,6 @@ static uint32_t* s_mac_bb_pd_mem = NULL;
static uint8_t s_macbb_backup_mem_ref = 0;
/* Reference of powering down MAC and BB */
static bool s_mac_bb_pu = true;
#elif SOC_PM_MODEM_RETENTION_BY_REGDMA
static esp_err_t sleep_retention_wifi_bb_init(void *arg)
{
const static sleep_retention_entries_config_t bb_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, 121, 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14, 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53, 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39, 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87, 0, 0), .owner = BIT(0) | BIT(1) } /* FE CTRL */
#endif
};
esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");
ESP_LOGD(TAG, "WiFi BB sleep retention initialization");
return ESP_OK;
}
#endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
void esp_mac_bb_pd_mem_init(void)
@ -516,19 +492,7 @@ void esp_mac_bb_pd_mem_init(void)
}
_lock_release(&s_phy_access_lock);
#elif SOC_PM_MODEM_RETENTION_BY_REGDMA
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = sleep_retention_wifi_bb_init, .arg = NULL } },
.depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_MODEM)
};
esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_WIFI_BB, &init_param);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention init failed");
return;
}
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to allocate sleep retention linked list for wifi bb retention");
}
esp_phy_sleep_data_init();
#endif
}
@ -543,15 +507,7 @@ void esp_mac_bb_pd_mem_deinit(void)
}
_lock_release(&s_phy_access_lock);
#elif SOC_PM_MODEM_RETENTION_BY_REGDMA
esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "failed to free sleep retention linked list for wifi bb retention");
return;
}
err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_WIFI_BB);
if (err != ESP_OK) {
ESP_LOGW(TAG, "WiFi BB sleep retention deinit failed");
}
esp_phy_sleep_data_deinit();
#endif
}

10
components/esp_pm/linker.lf
View File

@ -39,6 +39,16 @@ entries:
sleep_modem:modem_domain_pd_allowed (noflash)
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
if SOC_TEMP_SENSOR_SUPPORTED = y:
sar_periph_ctrl_common:temperature_sensor_power_acquire (noflash)
sar_periph_ctrl_common:temperature_sensor_power_release (noflash)
sar_periph_ctrl_common:temperature_sensor_get_raw_value (noflash)
sar_periph_ctrl_common:temp_sensor_get_raw_value (noflash)
regi2c_ctrl:regi2c_saradc_enable (noflash)
regi2c_ctrl:regi2c_saradc_disable (noflash)
if SOC_ADC_SUPPORTED = y:
adc_share_hw_ctrl:adc_apb_periph_claim (noflash)
adc_share_hw_ctrl:adc_apb_periph_free (noflash)
[mapping:esp_system_pm]
archive: libesp_system.a

15
components/esp_system/port/soc/esp32c5/clk.c
View File

@ -23,6 +23,7 @@
#include "esp_cpu.h"
#include "hal/efuse_hal.h"
#include "hal/wdt_hal.h"
#include "hal/clk_tree_ll.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_lpcon_ll.h"
#endif
@ -222,14 +223,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
* the issue where the modem module fails to transmit and receive packets
* due to the loss of the modem root clock caused by automatic clock gating
* during soc root clock source switching. For detailed information, refer
* to IDF-11064. */
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
* the issue where the modem module fails to transmit and receive packets
* due to the loss of the modem root clock caused by automatic clock gating
* during soc root clock source switching. For detailed information, refer
* to IDF-11064. */
clk_ll_soc_root_clk_auto_gating_bypass(true);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: [ESP32C5] IDF-8844

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit 73ba41ad38632ee8e36e5354aa565487fbfb156c
Subproject commit dfbd8b0145a604bcd4c0b57feff18cd1e62197cb

19
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@ -9,16 +9,19 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "soc/chip_revision.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32c5/rom/rtc.h"
#include "hal/misc.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
@ -420,6 +423,22 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
/**
* @brief Enable or disable the soc root clock auto gating logic
*
* @param ena true to enable, false to disable
*/
static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gating_bypass(bool ena)
{
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (ena) {
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
} else {
REG_SET_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
}
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*

3
components/soc/esp32c2/temperature_sensor_periph.c
View File

@ -5,8 +5,9 @@
*/
#include "soc/temperature_sensor_periph.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32c3/temperature_sensor_periph.c
View File

@ -5,8 +5,9 @@
*/
#include "soc/temperature_sensor_periph.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32c5/temperature_sensor_periph.c
View File

@ -8,8 +8,9 @@
#include "soc/regdma.h"
#include "soc/temperature_sensor_periph.h"
#include "soc/apb_saradc_reg.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32c6/temperature_sensor_periph.c
View File

@ -8,8 +8,9 @@
#include "soc/regdma.h"
#include "soc/temperature_sensor_periph.h"
#include "soc/apb_saradc_reg.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32c61/temperature_sensor_periph.c
View File

@ -8,8 +8,9 @@
#include "soc/regdma.h"
#include "soc/temperature_sensor_periph.h"
#include "soc/apb_saradc_reg.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32h2/temperature_sensor_periph.c
View File

@ -8,8 +8,9 @@
#include "soc/regdma.h"
#include "soc/temperature_sensor_periph.h"
#include "soc/apb_saradc_reg.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

2
components/soc/esp32p4/temperature_sensor_periph.c
View File

@ -6,7 +6,7 @@
#include "soc/temperature_sensor_periph.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32s2/temperature_sensor_periph.c
View File

@ -5,8 +5,9 @@
*/
#include "soc/temperature_sensor_periph.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

3
components/soc/esp32s3/temperature_sensor_periph.c
View File

@ -5,8 +5,9 @@
*/
#include "soc/temperature_sensor_periph.h"
#include "esp_attr.h"
const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
DRAM_ATTR temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
/*Offset reg_val min max error */
{-2, 5, 50, 125, 3},
{-1, 7, 20, 100, 2},

2
components/soc/include/soc/temperature_sensor_periph.h
View File

@ -25,7 +25,7 @@ typedef struct {
int error_max;
} temperature_sensor_attribute_t;
extern const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM];
extern temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM];
#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
typedef struct {