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fix(i2s): suplimemt of c61 i2s ll

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laokaiyao 2024-10-30 16:05:35 +08:00 committed by Kevin (Lao Kaiyao)
parent 24a6994471
commit 76d87acd59
4 changed files with 118 additions and 35 deletions
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2
components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
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@ -114,7 +114,7 @@ static void test_i2s_tdm_master(uint32_t sample_rate, i2s_data_bit_width_t bit_w
if (i2s_channel_read(i2s_tdm_rx_handle, rx_buffer, buf_size, &bytes_read, 1000) != ESP_OK) {
continue;
}
for (int i = 0; i < buf_size && count < TEST_I2S_MAX_DATA; i++) {
for (int i = 0; i < buf_size / sizeof(uint32_t) && count < TEST_I2S_MAX_DATA; i++) {
if (rx_buffer[i] == count) {
count++;
} else if (count != 1) {

3
components/hal/esp32c5/include/hal/i2s_ll.h
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@ -13,7 +13,6 @@
#pragma once
#include <stdbool.h>
#include "sdkconfig.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
@ -154,7 +153,7 @@ static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
{
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0; // TODO: need check
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;
}
/**

2
components/hal/esp32c61/include/hal/etm_ll.h
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@ -18,6 +18,8 @@
extern "C" {
#endif
#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task
/**
* @brief Enable the clock for ETM register
*

146
components/hal/esp32c61/include/hal/i2s_ll.h
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@ -18,6 +18,7 @@
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_struct.h"
#include "soc/soc_etm_source.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
@ -28,16 +29,16 @@ extern "C" {
#endif
#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL)
#define I2S_LL_GET_ID(hw) (((hw) == &I2S0)? 0 : -1)
#define I2S_LL_TDM_CH_MASK (0xffff)
#define I2S_LL_PDM_BCK_FACTOR (64)
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_PLL_F120M_CLK_FREQ (120 * 1000000) // PLL_F160M_CLK: 120MHz
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event) \
(uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){{ \
@ -64,6 +65,7 @@ extern "C" {
#define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFUL)
/**
* @brief Enable the bus clock for I2S module
*
* @param i2s_id The port id of I2S
* @param enable Set true to enable the buf clock
@ -313,13 +315,21 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void)hw;
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 2);
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 0;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = 1;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = 0;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = 0;
/* Set the target mclk division coefficients */
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = yn1;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
typeof(PCR.i2s_tx_clkm_div_conf) div = {};
div.i2s_tx_clkm_div_x = x;
div.i2s_tx_clkm_div_y = y;
div.i2s_tx_clkm_div_z = z;
div.i2s_tx_clkm_div_yn1 = yn1;
PCR.i2s_tx_clkm_div_conf.val = div.val;
}
/**
@ -335,13 +345,21 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void)hw;
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 2);
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 0;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = 1;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = 0;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = 0;
/* Set the target mclk division coefficients */
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = yn1;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int);
typeof(PCR.i2s_rx_clkm_div_conf) div = {};
div.i2s_rx_clkm_div_x = x;
div.i2s_rx_clkm_div_y = y;
div.i2s_rx_clkm_div_z = z;
div.i2s_rx_clkm_div_yn1 = yn1;
PCR.i2s_rx_clkm_div_conf.val = div.val;
}
/**
@ -352,12 +370,6 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t div_x = 0;
uint32_t div_y = 0;
uint32_t div_z = 0;
@ -392,12 +404,6 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t div_x = 0;
uint32_t div_y = 0;
uint32_t div_z = 0;
@ -525,7 +531,7 @@ static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int
*/
static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
{
hw->tx_conf1.tx_half_sample_bits = half_sample_bits - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_conf1, tx_half_sample_bits, half_sample_bits - 1);
}
/**
@ -536,7 +542,7 @@ static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_
*/
static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
{
hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_conf1, rx_half_sample_bits, half_sample_bits - 1);
}
/**
@ -1218,7 +1224,7 @@ static inline uint32_t i2s_ll_tx_get_bclk_sync_count(i2s_dev_t *hw)
* @brief Set the TX ETM threshold of REACH_THRESH event
*
* @param hw Peripheral I2S hardware instance address.
* @param thresh The threshold that send
* @param thresh The threshold that send, in words (4 bytes)
*/
static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
{
@ -1229,13 +1235,89 @@ static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
* @brief Set the RX ETM threshold of REACH_THRESH event
*
* @param hw Peripheral I2S hardware instance address.
* @param thresh The threshold that received
* @param thresh The threshold that received, in words (4 bytes)
*/
static inline void i2s_ll_rx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
{
hw->etm_conf.etm_rx_receive_word_num = thresh;
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}
#ifdef __cplusplus
}
#endif