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Merge branch 'bugfix/fix_some_wifi_coexist_bugs_20241105_v5.1' into 'release/v5.1'

Browse Source 
bugfix/fix some wifi coexist bugs 20241105 v5.1

See merge request espressif/esp-idf!34657
This commit is contained in:
Jiang Jiang Jian 2024-11-21 15:49:41 +08:00
commit 7ac7939f52
46 changed files with 1003 additions and 60 deletions
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4
components/esp_coex/CMakeLists.txt
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@ -13,7 +13,9 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE)
endif()
if(CONFIG_ESP_WIFI_ENABLED)
list(APPEND srcs "${idf_target}/esp_coex_adapter.c")
list(APPEND srcs "${idf_target}/esp_coex_adapter.c"
"src/coexist_debug_diagram.c"
"src/coexist_debug.c")
endif()
idf_component_register(SRCS "${srcs}"

197
components/esp_coex/Kconfig
View File

@ -33,4 +33,201 @@ menu "Wireless Coexistence"
help
If enabled, coexist power management will be enabled.
config ESP_COEX_GPIO_DEBUG
bool "GPIO debugging for coexistence"
default n
depends on !PM_SLP_DISABLE_GPIO && !PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
help
Support coexistence GPIO debugging
if (ESP_COEX_GPIO_DEBUG)
choice ESP_COEX_GPIO_DEBUG_DIAG
prompt "Debugging Diagram"
default ESP_COEX_GPIO_DEBUG_DIAG_GENERAL
help
Select type of debugging diagram
config ESP_COEX_GPIO_DEBUG_DIAG_GENERAL
bool "General"
config ESP_COEX_GPIO_DEBUG_DIAG_WIFI
bool "Wi-Fi"
endchoice
config ESP_COEX_GPIO_DEBUG_IO_COUNT
int "Max number of debugging GPIOs"
range 0 12
default 12
config ESP_COEX_GPIO_DEBUG_IO_IDX0
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 0)
int "Actual IO num for Debug IO ID0"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 15 if IDF_TARGET_ESP32
default 4 if IDF_TARGET_ESP32S2
default 19 if IDF_TARGET_ESP32C3
default 4 if IDF_TARGET_ESP32S3
default 18 if IDF_TARGET_ESP32C2
default 4 if IDF_TARGET_ESP32C6
default 2 if IDF_TARGET_ESP32C5
default 4 if IDF_TARGET_ESP32C61
default 1
config ESP_COEX_GPIO_DEBUG_IO_IDX1
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 1)
int "Actual IO num for Debug IO ID1"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 2 if IDF_TARGET_ESP32
default 5 if IDF_TARGET_ESP32S2
default 18 if IDF_TARGET_ESP32C3
default 5 if IDF_TARGET_ESP32S3
default 4 if IDF_TARGET_ESP32C2
default 5 if IDF_TARGET_ESP32C6
default 3 if IDF_TARGET_ESP32C5
default 5 if IDF_TARGET_ESP32C61
default 2
config ESP_COEX_GPIO_DEBUG_IO_IDX2
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 2)
int "Actual IO num for Debug IO ID2"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 0 if IDF_TARGET_ESP32
default 6 if IDF_TARGET_ESP32S2
default 4 if IDF_TARGET_ESP32C3
default 6 if IDF_TARGET_ESP32S3
default 5 if IDF_TARGET_ESP32C2
default 6 if IDF_TARGET_ESP32C6
default 4 if IDF_TARGET_ESP32C5
default 6 if IDF_TARGET_ESP32C61
default 3
config ESP_COEX_GPIO_DEBUG_IO_IDX3
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 3)
int "Actual IO num for Debug IO ID3"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 4 if IDF_TARGET_ESP32
default 7 if IDF_TARGET_ESP32S2
default 5 if IDF_TARGET_ESP32C3
default 7 if IDF_TARGET_ESP32S3
default 6 if IDF_TARGET_ESP32C2
default 7 if IDF_TARGET_ESP32C6
default 5 if IDF_TARGET_ESP32C5
default 7 if IDF_TARGET_ESP32C61
default 4
config ESP_COEX_GPIO_DEBUG_IO_IDX4
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 4)
int "Actual IO num for Debug IO ID4"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 5 if IDF_TARGET_ESP32
default 8 if IDF_TARGET_ESP32S2
default 6 if IDF_TARGET_ESP32C3
default 15 if IDF_TARGET_ESP32S3
default 7 if IDF_TARGET_ESP32C2
default 8 if IDF_TARGET_ESP32C6
default 27 if IDF_TARGET_ESP32C5
default 0 if IDF_TARGET_ESP32C61
default 5
config ESP_COEX_GPIO_DEBUG_IO_IDX5
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 5)
int "Actual IO num for Debug IO ID5"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 18 if IDF_TARGET_ESP32
default 9 if IDF_TARGET_ESP32S2
default 7 if IDF_TARGET_ESP32C3
default 16 if IDF_TARGET_ESP32S3
default 8 if IDF_TARGET_ESP32C2
default 10 if IDF_TARGET_ESP32C6
default 6 if IDF_TARGET_ESP32C5
default 1 if IDF_TARGET_ESP32C61
default 6
config ESP_COEX_GPIO_DEBUG_IO_IDX6
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 6)
int "Actual IO num for Debug IO ID6"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 19 if IDF_TARGET_ESP32
default 10 if IDF_TARGET_ESP32S2
default 8 if IDF_TARGET_ESP32C3
default 17 if IDF_TARGET_ESP32S3
default 9 if IDF_TARGET_ESP32C2
default 11 if IDF_TARGET_ESP32C6
default 7 if IDF_TARGET_ESP32C5
default 8 if IDF_TARGET_ESP32C61
default 7
config ESP_COEX_GPIO_DEBUG_IO_IDX7
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 7)
int "Actual IO num for Debug IO ID7"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 22 if IDF_TARGET_ESP32
default 11 if IDF_TARGET_ESP32S2
default 9 if IDF_TARGET_ESP32C3
default 18 if IDF_TARGET_ESP32S3
default 10 if IDF_TARGET_ESP32C2
default 2 if IDF_TARGET_ESP32C6
default 26 if IDF_TARGET_ESP32C5
default 2 if IDF_TARGET_ESP32C61
default 8
config ESP_COEX_GPIO_DEBUG_IO_IDX8
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 8)
int "Actual IO num for Debug IO ID8"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 13 if IDF_TARGET_ESP32
default 12 if IDF_TARGET_ESP32S2
default 10 if IDF_TARGET_ESP32C3
default 10 if IDF_TARGET_ESP32S3
default 1 if IDF_TARGET_ESP32C2
default 15 if IDF_TARGET_ESP32C6
default 24 if IDF_TARGET_ESP32C5
default 3 if IDF_TARGET_ESP32C61
default 9
config ESP_COEX_GPIO_DEBUG_IO_IDX9
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 9)
int "Actual IO num for Debug IO ID9"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 12 if IDF_TARGET_ESP32
default 13 if IDF_TARGET_ESP32S2
default 0 if IDF_TARGET_ESP32C3
default 11 if IDF_TARGET_ESP32S3
default 0 if IDF_TARGET_ESP32C2
default 23 if IDF_TARGET_ESP32C6
default 23 if IDF_TARGET_ESP32C5
default 9 if IDF_TARGET_ESP32C61
default 10
config ESP_COEX_GPIO_DEBUG_IO_IDX10
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 10)
int "Actual IO num for Debug IO ID10"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 14 if IDF_TARGET_ESP32
default 14 if IDF_TARGET_ESP32S2
default 3 if IDF_TARGET_ESP32C3
default 12 if IDF_TARGET_ESP32S3
default 3 if IDF_TARGET_ESP32C2
default 22 if IDF_TARGET_ESP32C6
default 10 if IDF_TARGET_ESP32C5
default 13 if IDF_TARGET_ESP32C61
default 11
config ESP_COEX_GPIO_DEBUG_IO_IDX11
depends on (ESP_COEX_GPIO_DEBUG_IO_COUNT > 11)
int "Actual IO num for Debug IO ID11"
range 0 SOC_GPIO_OUT_RANGE_MAX
default 27 if IDF_TARGET_ESP32
default 15 if IDF_TARGET_ESP32S2
default 2 if IDF_TARGET_ESP32C3
default 13 if IDF_TARGET_ESP32S3
default 2 if IDF_TARGET_ESP32C2
default 21 if IDF_TARGET_ESP32C6
default 9 if IDF_TARGET_ESP32C5
default 12 if IDF_TARGET_ESP32C61
default 12
endif
endmenu # Wireless Coexistence

13
components/esp_coex/esp32/esp_coex_adapter.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,6 +20,7 @@
#include "esp_timer.h"
#include "private/esp_coexist_adapter.h"
#include "esp32/rom/ets_sys.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -206,6 +207,15 @@ static int32_t esp_coex_internal_semphr_give_wrapper(void *semphr)
return (int32_t)xSemaphoreGive(((modem_static_queue_t *)semphr)->handle);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._spin_lock_create = esp_coex_common_spin_lock_create_wrapper,
@ -227,5 +237,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

19
components/esp_coex/esp32c2/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,6 +22,7 @@
#include "esp_private/esp_clk.h"
#include "private/esp_coexist_adapter.h"
#include "esp32c2/rom/ets_sys.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -142,6 +143,20 @@ static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, voi
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
{
return rtc_clk_xtal_freq_get();
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -161,5 +176,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

13
components/esp_coex/esp32c3/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,6 +23,7 @@
#include "private/esp_coexist_adapter.h"
#include "esp32c3/rom/ets_sys.h"
#include "soc/system_reg.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -148,6 +149,15 @@ static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, voi
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -165,5 +175,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

19
components/esp_coex/esp32c6/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,6 +22,7 @@
#include "esp_private/esp_clk.h"
#include "private/esp_coexist_adapter.h"
#include "esp32c6/rom/ets_sys.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -142,6 +143,20 @@ static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, voi
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
{
return rtc_clk_xtal_freq_get();
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -160,5 +175,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

21
components/esp_coex/esp32h2/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -21,7 +21,8 @@
#include "soc/rtc.h"
#include "esp_private/esp_clk.h"
#include "private/esp_coexist_adapter.h"
#include "esp32c6/rom/ets_sys.h"
#include "esp32h2/rom/ets_sys.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -134,6 +135,20 @@ static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, voi
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
{
return rtc_clk_xtal_freq_get();
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -152,5 +167,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

13
components/esp_coex/esp32s2/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,6 +22,7 @@
#include "esp_private/esp_clk.h"
#include "private/esp_coexist_adapter.h"
#include "esp32s2/rom/ets_sys.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -216,6 +217,15 @@ static int32_t esp_coex_internal_semphr_give_wrapper(void *semphr)
return (int32_t)xSemaphoreGive(((modem_static_queue_t *)semphr)->handle);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -233,5 +243,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

13
components/esp_coex/esp32s3/esp_coex_adapter.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,6 +23,7 @@
#include "private/esp_coexist_adapter.h"
#include "esp32s3/rom/ets_sys.h"
#include "soc/system_reg.h"
#include "private/esp_coexist_debug.h"
#define TAG "esp_coex_adapter"
@ -222,6 +223,15 @@ static int32_t esp_coex_internal_semphr_give_wrapper(void *semphr)
return (int32_t)xSemaphoreGive(((modem_static_queue_t *)semphr)->handle);
}
static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
{
#if CONFIG_ESP_COEX_GPIO_DEBUG
return esp_coexist_debug_matrix_init(evt, sig, rev);
#else
return ESP_ERR_NOT_SUPPORTED;
#endif
}
coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@ -239,5 +249,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};

13
components/esp_coex/include/esp_coexist.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -116,7 +116,7 @@ const char *esp_coex_version_get(void);
* @deprecated Use esp_coex_status_bit_set() and esp_coex_status_bit_clear() instead.
* Set coexist preference of performance
* For example, if prefer to bluetooth, then it will make A2DP(play audio via classic bt)
* more smooth while wifi is runnning something.
* more smooth while wifi is running something.
* If prefer to wifi, it will do similar things as prefer to bluetooth.
* Default, it prefer to balance.
*
@ -219,6 +219,15 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid);
esp_err_t esp_coex_wifi_i154_enable(void);
#endif
#if CONFIG_ESP_COEX_GPIO_DEBUG
/**
* @brief Enable coexist GPIO debug.
* To fully enable this feature, make sure functions in rom_funcs are out of ROM.
* @return : ESP_OK - success, other - failed
*/
esp_err_t esp_coexist_debug_init(void);
#endif
#ifdef __cplusplus
}
#endif

2
components/esp_coex/include/private/esp_coexist_adapter.h
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@ -46,6 +46,8 @@ typedef struct {
void (* _timer_done)(void *ptimer);
void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
int (* _debug_matrix_init)(int event, int signal, bool rev);
int (* _xtal_freq_get)(void);
int32_t _magic;
} coex_adapter_funcs_t;

152
components/esp_coex/include/private/esp_coexist_debug.h Normal file
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@ -0,0 +1,152 @@
/*
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#if CONFIG_ESP_COEX_GPIO_DEBUG
#include "esp_err.h"
#include "stdbool.h"
#include "soc/soc_caps.h"
#define COEX_GPIO_DEBUG_IO_INVALID SOC_GPIO_PIN_COUNT
/* Debug signal */
#define COEX_GPIO_DEBUG_SIG_RES_US 10
typedef enum {
COEX_GPIO_DEBUG_SIG_POSE,
COEX_GPIO_DEBUG_SIG_NEGA,
} coex_gpio_debug_sig_t;
#define COEX_GPIO_DEBUG_SIG_TO_DURATION(sig) ((sig - COEX_GPIO_DEBUG_SIG_NEGA) * COEX_GPIO_DEBUG_SIG_RES_US)
#define COEX_GPIO_DEBUG_SIG_CHECK_US 100
/* User diagram */
#ifdef CONFIG_ESP_COEX_GPIO_DEBUG_DIAG_GENERAL
#define COEX_GPIO_DEBUG_DIAG_GENERAL 1
#elif defined(CONFIG_ESP_COEX_GPIO_DEBUG_DIAG_WIFI)
#define COEX_GPIO_DEBUG_DIAG_WIFI 1
#endif
/* User configuration validity check */
#define COEX_GPIO_DEBUG_IO_COUNT_MAX 12
#define COEX_GPIO_DEBUG_IO_COUNT CONFIG_ESP_COEX_GPIO_DEBUG_IO_COUNT
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX0)
#define COEX_GPIO_DEBUG_IO_IDX0 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX0 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX0
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX1)
#define COEX_GPIO_DEBUG_IO_IDX1 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX1 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX1
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX2)
#define COEX_GPIO_DEBUG_IO_IDX2 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX2 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX2
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX3)
#define COEX_GPIO_DEBUG_IO_IDX3 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX3 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX3
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX4)
#define COEX_GPIO_DEBUG_IO_IDX4 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX4 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX4
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX5)
#define COEX_GPIO_DEBUG_IO_IDX5 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX5 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX5
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX6)
#define COEX_GPIO_DEBUG_IO_IDX6 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX6 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX6
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX7)
#define COEX_GPIO_DEBUG_IO_IDX7 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX7 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX7
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX8)
#define COEX_GPIO_DEBUG_IO_IDX8 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX8 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX8
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX9)
#define COEX_GPIO_DEBUG_IO_IDX9 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX9 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX9
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX10)
#define COEX_GPIO_DEBUG_IO_IDX10 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX10 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX10
#endif
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX11)
#define COEX_GPIO_DEBUG_IO_IDX11 COEX_GPIO_DEBUG_IO_INVALID
#else
#define COEX_GPIO_DEBUG_IO_IDX11 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX11
#endif
/* wifi callback -> debug */
void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t));
int wifi_gpio_debug_max_event_get(void);
/* functions to check if in ROM */
void lmacProcessTxComplete(void);
void lmacTxFrame(void);
void pm_update_by_connectionless_status(void);
void pm_sleep(void);
void pm_dream(void);
void pm_beacon_monitor_timeout_process(void);
void pm_connectionless_wake_window_timeout_process(void);
void pm_coex_schm_process(void);
void pm_tbtt_process(void);
void pm_rx_beacon_process(void);
void ppTask(void);
void wDev_IndicateFrame(void);
void pm_check_state(void);
void pm_tx_null_data_done_process(void);
void pm_start(void);
void pm_stop(void);
void pm_disconnected_wake(void);
/* coex callback -> debug */
void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t));
int coex_gpio_debug_max_event_get(void);
esp_err_t coex_gpio_debug_matrix_init(void);
/* debug -> coex wrapper */
esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev);
/* debug <-> diagram */
void wifi_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
void coex_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
void diagram_bind_io_to_evt(void);
/* coex -> debug
* configure single gpio debug event */
esp_err_t coex_gpio_debug_matrix_config(int event);
/* debug -> internal use */
esp_err_t esp_coexist_gpio_debug_matrix_config(int event);
#endif

14
components/esp_coex/include/private/esp_coexist_internal.h
View File

@ -28,6 +28,16 @@ typedef enum {
COEX_SCHM_CALLBACK_TYPE_I154,
} coex_schm_callback_type_t;
typedef enum {
COEX_SCHM_ST_TYPE_WIFI = 0,
COEX_SCHM_ST_TYPE_BLE,
COEX_SCHM_ST_TYPE_BT,
} coex_schm_st_type_t;
#define COEX_STATUS_GET_WIFI_BITMAP (1 << COEX_SCHM_ST_TYPE_WIFI)
#define COEX_STATUS_GET_BLE_BITMAP (1 << COEX_SCHM_ST_TYPE_BLE)
#define COEX_STATUS_GET_BT_BITMAP (1 << COEX_SCHM_ST_TYPE_BT)
typedef void (* coex_func_cb_t)(uint32_t event, int sched_cnt);
typedef esp_err_t (* coex_set_lpclk_source_callback_t)(void);
typedef void (* coex_wifi_channel_change_cb_t)(uint8_t primary, uint8_t secondary);
@ -94,9 +104,11 @@ esp_err_t coex_preference_set(coex_prefer_t prefer);
/**
* @brief Get software coexist status.
*
* @param bitmap : bitmap of the module getting status.
* @return : software coexist status
*/
uint32_t coex_status_get(void);
uint32_t coex_status_get(uint8_t bitmap);
/**
* @brief WiFi requests coexistence.

2
components/esp_coex/lib

@ -1 +1 @@
Subproject commit d17141ba292d6a4b7434c5080cb0b0e7ce170fc8
Subproject commit 97df1ca6cbfb8105ed3121e72a73591a36220b33

39
components/esp_coex/src/coexist.c
View File

@ -1,21 +1,24 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_coexist.h"
#include "private/esp_coexist_internal.h"
#include "soc/soc_caps.h"
#if CONFIG_EXTERNAL_COEX_ENABLE
#include "esp_log.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "esp_attr.h"
#include "esp_private/gpio.h"
#endif
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#if SOC_EXTERNAL_COEX_ADVANCE
@ -163,9 +166,6 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
return ESP_ERR_INVALID_ARG;
}
esp_coex_external_set_wire_type(wire_type);
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params, 0, 0);
#endif
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
switch (wire_type)
@ -174,7 +174,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
case EXTERN_COEX_WIRE_4:
{
esp_coex_external_set_txline(true);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.tx_line));
esp_rom_gpio_connect_out_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_O1_TXLINE_IDX, false, false);
@ -183,7 +183,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
#endif
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
@ -192,7 +192,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.grant));
esp_rom_gpio_connect_out_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
@ -200,7 +200,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
@ -218,7 +218,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
{
case EXTERN_COEX_WIRE_4:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.tx_line], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
@ -227,7 +227,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_3:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.priority], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.priority, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.priority));
esp_rom_gpio_connect_out_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_O1_IDX, false, false);
@ -235,7 +235,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_2:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.grant], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
@ -244,7 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
__attribute__((fallthrough));
case EXTERN_COEX_WIRE_1:
{
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.request], PIN_FUNC_GPIO);
gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.request, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.request));
esp_rom_gpio_connect_out_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_O0_IDX, false, false);
@ -259,7 +259,16 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
return ESP_ERR_INVALID_ARG;
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
}
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params, 0, 0);
#endif
esp_err_t ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
if (ESP_OK != ret) {
return ESP_FAIL;
}

279
components/esp_coex/src/coexist_debug.c Normal file
View File

@ -0,0 +1,279 @@
/*
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "private/esp_coexist_debug.h"
#include <stdbool.h>
#include "esp_err.h"
#include "string.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "rom/ets_sys.h"
#include "driver/gpio.h"
#include "soc/gpio_sig_map.h"
#include "esp_rom_gpio.h"
#include "soc/soc.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#if CONFIG_ESP_COEX_GPIO_DEBUG
static char* TAG = "coexist debug";
__attribute__((weak)) void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t))
{
ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
}
__attribute__((weak)) int wifi_gpio_debug_max_event_get(void)
{
ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
return 0;
}
__attribute__((weak)) void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t))
{
ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
}
__attribute__((weak)) int coex_gpio_debug_max_event_get(void)
{
ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
return 0;
}
__attribute__((weak)) esp_err_t coex_gpio_debug_matrix_init(void)
{
ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
return ESP_OK;
}
/* Check if functions in ROM */
static const void* rom_funcs[] = {
#if CONFIG_ESP_WIFI_ENABLED
lmacProcessTxComplete,
lmacTxFrame,
pm_update_by_connectionless_status,
pm_sleep,
pm_dream,
pm_beacon_monitor_timeout_process,
pm_connectionless_wake_window_timeout_process,
pm_coex_schm_process,
pm_tbtt_process,
pm_rx_beacon_process,
ppTask,
wDev_IndicateFrame,
pm_check_state,
pm_tx_null_data_done_process,
pm_start,
pm_stop,
pm_disconnected_wake,
#endif
};
static const char* rom_funcs_name[] = {
#if CONFIG_ESP_WIFI_ENABLED
"lmacProcessTxComplete",
"lmacTxframe",
"pm_update_by_connectionless_status",
"pm_sleep",
"pm_dream",
"pm_beacon_monitor_timeout_process",
"pm_connectionless_wake_window_timeout_process",
"pm_coex_schm_process",
"pm_tbtt_process",
"pm_rx_beacon_process",
"ppTask",
"wDev_IndicateFrame",
"pm_check_state",
"pm_tx_null_data_done_process",
"pm_start",
"pm_stop",
"pm_disconnected_wake",
#endif
};
static bool check_funcs_in_rom(void)
{
bool in_rom = false;
for (uint8_t i = 0; i < sizeof(rom_funcs) / sizeof(void*); i++) {
if ((uint32_t)rom_funcs[i] >= SOC_IROM_MASK_LOW && (uint32_t)rom_funcs[i] <= SOC_IROM_MASK_HIGH) {
ESP_LOGE(TAG, "remove function from ROM: %s", rom_funcs_name[i]);
in_rom = true;
}
}
return in_rom;
}
/* Define used IO nums */
static const DRAM_ATTR gpio_num_t s_io_nums[COEX_GPIO_DEBUG_IO_COUNT_MAX] = {
COEX_GPIO_DEBUG_IO_IDX0,
COEX_GPIO_DEBUG_IO_IDX1,
COEX_GPIO_DEBUG_IO_IDX2,
COEX_GPIO_DEBUG_IO_IDX3,
COEX_GPIO_DEBUG_IO_IDX4,
COEX_GPIO_DEBUG_IO_IDX5,
COEX_GPIO_DEBUG_IO_IDX6,
COEX_GPIO_DEBUG_IO_IDX7,
COEX_GPIO_DEBUG_IO_IDX8,
COEX_GPIO_DEBUG_IO_IDX9,
COEX_GPIO_DEBUG_IO_IDX10,
COEX_GPIO_DEBUG_IO_IDX11,
};
/* Mapping from evt to IO */
static DRAM_ATTR gpio_num_t *s_evt_io_map, *s_wifi_evt_io_map, *s_coex_evt_io_map;
static DRAM_ATTR uint8_t s_wifi_evt_max, s_coex_evt_max;
inline static void bind_io_to_evt(gpio_num_t *ptrmap, uint8_t io, uint8_t evt)
{
ptrmap[evt] = io;
}
inline static void evt_set_signal(gpio_num_t io, coex_gpio_debug_sig_t sig)
{
if (sig == COEX_GPIO_DEBUG_SIG_POSE) {
gpio_set_level(io, true);
} else if (sig == COEX_GPIO_DEBUG_SIG_NEGA) {
gpio_set_level(io, false);
} else {
gpio_set_level(io, true);
esp_rom_delay_us(COEX_GPIO_DEBUG_SIG_TO_DURATION(sig));
gpio_set_level(io, false);
}
}
void wifi_bind_io_to_evt(uint8_t io_idx, uint8_t evt)
{
if (!s_wifi_evt_io_map || evt >= s_wifi_evt_max || io_idx >= COEX_GPIO_DEBUG_IO_COUNT) {
return;
}
ESP_LOGI(TAG, "Bind IO %u to Wi-Fi evt %u", s_io_nums[io_idx], evt);
bind_io_to_evt(s_wifi_evt_io_map, s_io_nums[io_idx], evt);
}
void coex_bind_io_to_evt(uint8_t io_idx, uint8_t evt)
{
if (!s_coex_evt_io_map || evt >= s_coex_evt_max || io_idx >= COEX_GPIO_DEBUG_IO_COUNT) {
return;
}
ESP_LOGI(TAG, "Bind IO %u to coexist evt %u", s_io_nums[io_idx], evt);
bind_io_to_evt(s_coex_evt_io_map, s_io_nums[io_idx], evt);
}
IRAM_ATTR void wifi_set_gpio_debug(int evt, coex_gpio_debug_sig_t sig)
{
if (evt >= s_wifi_evt_max || s_wifi_evt_io_map[evt] == COEX_GPIO_DEBUG_IO_INVALID) {
return;
}
evt_set_signal(s_wifi_evt_io_map[evt], sig);
}
IRAM_ATTR void coex_set_gpio_debug(int evt, coex_gpio_debug_sig_t sig)
{
if (evt >= s_coex_evt_max || s_coex_evt_io_map[evt] == COEX_GPIO_DEBUG_IO_INVALID) {
return;
}
evt_set_signal(s_coex_evt_io_map[evt], sig);
}
esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev)
{
if (evt >= s_coex_evt_max || s_coex_evt_io_map[evt] == COEX_GPIO_DEBUG_IO_INVALID) {
return ESP_ERR_INVALID_ARG;
}
esp_rom_gpio_connect_out_signal(s_coex_evt_io_map[evt], sig, rev, false);
return ESP_OK;
}
esp_err_t esp_coexist_gpio_debug_matrix_config(int event)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
esp_err_t ret = coex_gpio_debug_matrix_config(event);
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
return ret;
}
esp_err_t esp_coexist_debug_init(void)
{
if (check_funcs_in_rom()) {
return ESP_ERR_INVALID_STATE;
}
s_wifi_evt_max = wifi_gpio_debug_max_event_get();
s_coex_evt_max = coex_gpio_debug_max_event_get();
uint8_t evt_max = s_wifi_evt_max + s_coex_evt_max;
if (evt_max == 0) {
return ESP_ERR_NOT_SUPPORTED;
}
/* Allocate binding map */
s_evt_io_map = malloc(sizeof(gpio_num_t) * evt_max);
if (!s_evt_io_map) {
return ESP_ERR_NO_MEM;
}
/* Init to invalid IO num */
for (uint8_t i = 0; i < evt_max; i++) {
s_evt_io_map[i] = COEX_GPIO_DEBUG_IO_INVALID;
}
s_wifi_evt_io_map = s_evt_io_map;
s_coex_evt_io_map = s_evt_io_map + s_wifi_evt_max;
/* binding map configuration */
diagram_bind_io_to_evt();
/* Register callback for Wi-Fi evt */
wifi_set_gpio_debug_cb(wifi_set_gpio_debug);
/* Register callback for coexist evt */
coex_set_gpio_debug_cb(coex_set_gpio_debug);
/* IO init and validity check */
gpio_config_t io_conf = {
//disable interrupt
.intr_type = GPIO_INTR_DISABLE,
//set as output mode
.mode = GPIO_MODE_OUTPUT,
//bit mask of the pins that you want to set,e.g.GPIO18/19
.pin_bit_mask = 0,
//disable pull-down mode
.pull_down_en = GPIO_PULLDOWN_DISABLE,
//enable pull-up mode
.pull_up_en = GPIO_PULLUP_ENABLE,
};
for (uint8_t i = 0; i < COEX_GPIO_DEBUG_IO_COUNT; i++) {
gpio_num_t io = s_io_nums[i];
io_conf.pin_bit_mask = (1ULL << io);
gpio_config(&io_conf);
gpio_set_level(io, 0);
}
esp_rom_delay_us(COEX_GPIO_DEBUG_SIG_CHECK_US);
for (uint8_t i = 0; i < COEX_GPIO_DEBUG_IO_COUNT; i++) {
gpio_set_level(s_io_nums[i], true);
}
esp_rom_delay_us(COEX_GPIO_DEBUG_SIG_CHECK_US);
for (uint8_t i = 0; i < COEX_GPIO_DEBUG_IO_COUNT; i++) {
gpio_set_level(s_io_nums[i], false);
}
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
/* Init coexist hardware signal */
ESP_ERROR_CHECK(coex_gpio_debug_matrix_init());
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
return ESP_OK;
}
#endif

59
components/esp_coex/src/coexist_debug_diagram.c Normal file
View File

@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "private/esp_coexist_debug.h"
#if CONFIG_ESP_COEX_GPIO_DEBUG
#ifdef COEX_GPIO_DEBUG_DIAG_GENERAL
void diagram_bind_io_to_evt(void) {
/* Bind IO to coexist evt */
#if CONFIG_IDF_TARGET_ESP32
coex_bind_io_to_evt(0, 8);
coex_bind_io_to_evt(0, 11);
coex_bind_io_to_evt(1, 16);
#else
coex_bind_io_to_evt(0, 0);
coex_bind_io_to_evt(1, 1);
#endif
/* Bind IO to Wi-Fi evt */
wifi_bind_io_to_evt(2, 9);
wifi_bind_io_to_evt(3, 10);
wifi_bind_io_to_evt(4, 11);
wifi_bind_io_to_evt(5, 0);
wifi_bind_io_to_evt(6, 1);
}
#elif defined(COEX_GPIO_DEBUG_DIAG_WIFI)
void diagram_bind_io_to_evt(void) {
/* Bind IO to coexist evt */
#if CONFIG_IDF_TARGET_ESP32
coex_bind_io_to_evt(0, 8);
coex_bind_io_to_evt(0, 11);
coex_bind_io_to_evt(1, 16);
#else
coex_bind_io_to_evt(0, 0);
coex_bind_io_to_evt(1, 1);
#endif
/* Bind IO to Wi-Fi evt */
wifi_bind_io_to_evt(2, 9);
wifi_bind_io_to_evt(3, 10);
wifi_bind_io_to_evt(4, 11);
wifi_bind_io_to_evt(5, 0);
wifi_bind_io_to_evt(6, 1);
wifi_bind_io_to_evt(7, 3);
wifi_bind_io_to_evt(8, 4);
wifi_bind_io_to_evt(9, 5);
wifi_bind_io_to_evt(10, 6);
wifi_bind_io_to_evt(11, 7);
}
#else
void diagram_bind_io_to_evt(void) {
}
#endif
#endif

68
components/esp_coex/test_md5/test_md5.sh
View File

@ -32,40 +32,74 @@ case $IDF_TARGET in
esac
LIB_DIR=${IDF_TARGET}
ELF_FILE=test.elf
COEX_ELF_FILE=coex.elf
TEST_ELF_FILE=test.elf
FAILURES=0
function check_md5()
{
FILENAME=$1
SYMBOL=$2
${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${ELF_FILE} \
-u ${SYMBOL} \
${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a
GDB_COMMAND="printf \"%s\\n\", (const char*) ${SYMBOL}"
MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${ELF_FILE} -ex "${GDB_COMMAND}")
MD5_FROM_HEADER=$(md5sum ${FILENAME} | cut -c 1-7)
echo "Checking ${FILENAME}:"
echo " ${MD5_FROM_HEADER} - from header file"
echo " ${MD5_FROM_LIB} - from library"
if [ "${MD5_FROM_LIB}" != "${MD5_FROM_HEADER}" ]; then
if [ "$1" != "$2" ]; then
echo " error: MD5 mismatch!"
FAILURES=$(($FAILURES+1))
fi
}
function check_md5_file_lib()
{
FILENAME=$1
SYMBOL=$2
${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \
-u ${SYMBOL} \
${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a
GDB_COMMAND="printf \"%s\\n\", (const char*) ${SYMBOL}"
MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${GDB_COMMAND}")
MD5_FROM_HEADER=$(md5sum ${FILENAME} | cut -c 1-7)
echo "Checking ${FILENAME}:"
echo " ${MD5_FROM_HEADER} - from header file"
echo " ${MD5_FROM_LIB} - from library"
check_md5 ${MD5_FROM_HEADER} ${MD5_FROM_LIB}
}
function check_md5_libs()
{
COEX_SYMBOL=$1
TEST_SYMBOL=$2
TEST_PATH=$3
${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \
-u ${COEX_SYMBOL} \
${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a
${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${TEST_ELF_FILE} \
-u ${TEST_SYMBOL} \
${TEST_PATH}/*.a
COEX_GDB_COMMAND="printf \"%s\\n\", (const char*) ${COEX_SYMBOL}"
TEST_GDB_COMMAND="printf \"%s\\n\", (const char*) ${TEST_SYMBOL}"
COEX_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${COEX_GDB_COMMAND}")
TEST_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${TEST_ELF_FILE} -ex "${TEST_GDB_COMMAND}")
echo "Checking ${TEST_PATH}/${TEST_SYMBOL} "
echo " ${COEX_MD5_FROM_LIB} - from coexist library"
echo " ${TEST_MD5_FROM_LIB} - from test library"
check_md5 ${COEX_MD5_FROM_LIB} ${TEST_MD5_FROM_LIB}
}
echo "Checking libraries for target ${IDF_TARGET}..."
check_md5 ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5
check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5
case $IDF_TARGET in
esp32c6|esp32h2)
check_md5 ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5
check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5
;;
esac
if [[ ! "$IDF_TARGET" =~ ^(esp32h2)$ ]]; then
check_md5_libs g_coex_basic_md5 g_wifi_coex_basic_md5 ${IDF_PATH}/components/esp_wifi/lib/${LIB_DIR}
fi
if [ $FAILURES -gt 0 ]; then
exit 1
fi

4
components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
View File

@ -64,8 +64,8 @@ hal_set_sta_tbtt = 0x40001e4c;
pm_set_sleep_type = 0x40001e54;
pm_tx_null_data_done_process = 0x40001eb0;
//pm_tx_data_process = 0x40001eb4;
pm_attach = 0x40001eb8;
pm_coex_schm_process = 0x40001ebc;
/*pm_attach = 0x40001eb8;*/
/*pm_coex_schm_process = 0x40001ebc;*/
pm_on_probe_resp_rx = 0x40001ecc;
pm_send_probe_stop = 0x40001edc;
hal_sniffer_rx_set_promis = 0x40001ef4;

4
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
View File

@ -799,7 +799,7 @@ dbg_lmac_rxtx_statis_dump = 0x40001e90;
dbg_lmac_hw_statis_dump = 0x40001e94;
dbg_lmac_diag_statis_dump = 0x40001e98;
dbg_lmac_ps_statis_dump = 0x40001e9c;
pp_timer_do_process = 0x40001ea0;
/*pp_timer_do_process = 0x40001ea0;*/
rcUpdateAMPDUParam = 0x40001ea4;
rcUpdatePhyMode = 0x40001ea8;
rcGetHighestRateIdx = 0x40001eac;
@ -1079,7 +1079,7 @@ coex_hw_timer_set = 0x4000219c;
coex_schm_interval_set = 0x400021a0;
coex_schm_lock = 0x400021a4;
coex_schm_unlock = 0x400021a8;
coex_status_get = 0x400021ac;
/*coex_status_get = 0x400021ac;*/
coex_wifi_release = 0x400021b0;
esp_coex_ble_conn_dynamic_prio_get = 0x400021b4;
/*coex_hw_timer_tick_get = 0x400021b8;*/

2
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
View File

@ -946,7 +946,7 @@ coex_hw_timer_set = 0x400018e0;
coex_schm_interval_set = 0x400018e4;
coex_schm_lock = 0x400018e8;
coex_schm_unlock = 0x400018ec;
coex_status_get = 0x400018f0;
/*coex_status_get = 0x400018f0;*/
coex_wifi_release = 0x400018f4;
esp_coex_ble_conn_dynamic_prio_get = 0x400018f8;
/* Data (.data, .bss, .rodata) */

2
components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld
View File

@ -35,7 +35,7 @@ coex_hw_timer_set = 0x40000b30;
coex_schm_interval_set = 0x40000b34;
coex_schm_lock = 0x40000b38;
coex_schm_unlock = 0x40000b3c;
coex_status_get = 0x40000b40;
/*coex_status_get = 0x40000b40;*/
coex_wifi_release = 0x40000b44;
esp_coex_ble_conn_dynamic_prio_get = 0x40000b48;
/* Data (.data, .bss, .rodata) */

2
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
View File

@ -1230,7 +1230,7 @@ coex_hw_timer_set = 0x40005c04;
coex_schm_interval_set = 0x40005c10;
coex_schm_lock = 0x40005c1c;
coex_schm_unlock = 0x40005c28;
coex_status_get = 0x40005c34;
/*coex_status_get = 0x40005c34;*/
coex_wifi_release = 0x40005c40;
esp_coex_ble_conn_dynamic_prio_get = 0x40005c4c;
/* Data (.data, .bss, .rodata) */

2
components/esp_wifi/esp32/esp_adapter.c
View File

@ -448,7 +448,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/esp32c2/esp_adapter.c
View File

@ -384,7 +384,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/esp32c3/esp_adapter.c
View File

@ -401,7 +401,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/esp32c6/esp_adapter.c
View File

@ -390,7 +390,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/esp32s2/esp_adapter.c
View File

@ -439,7 +439,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_EXTERNAL_COEX_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/esp32s3/esp_adapter.c
View File

@ -456,7 +456,7 @@ static void coex_disable_wrapper(void)
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
return coex_status_get();
return coex_status_get(COEX_STATUS_GET_WIFI_BITMAP);
#else
return 0;
#endif

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit 7b8497e1925284a9e891ed535699c34fe486506f
Subproject commit eaa36d56a58ba6ab8d16ebce7683a3b93b690d41

8
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@ -283,6 +283,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 39
config SOC_GPIO_OUT_RANGE_MAX
int
default 33
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0xEF0FEA

3
components/soc/esp32/include/soc/soc_caps.h
View File

@ -169,6 +169,9 @@
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
#define SOC_GPIO_IN_RANGE_MAX 39
#define SOC_GPIO_OUT_RANGE_MAX 33
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL

8
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -239,6 +239,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 20
config SOC_GPIO_OUT_RANGE_MAX
int
default 20
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -119,6 +119,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 20
#define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)

8
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -335,6 +335,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 21
config SOC_GPIO_OUT_RANGE_MAX
int
default 21
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -160,6 +160,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -411,6 +411,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
config SOC_GPIO_OUT_RANGE_MAX
int
default 30
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -184,6 +184,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)

8
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -427,6 +427,14 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 27
config SOC_GPIO_OUT_RANGE_MAX
int
default 27
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F

3
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -192,6 +192,9 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 27
#define SOC_GPIO_OUT_RANGE_MAX 27
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL

8
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -335,6 +335,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x7FFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 46
config SOC_GPIO_OUT_RANGE_MAX
int
default 45
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00007FFFFC000000

3
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -159,6 +159,9 @@
// GPIO 46 is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
#define SOC_GPIO_IN_RANGE_MAX 46
#define SOC_GPIO_OUT_RANGE_MAX 45
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000ULL

8
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -395,6 +395,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x1FFFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 48
config SOC_GPIO_OUT_RANGE_MAX
int
default 48
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0001FFFFFC000000

4
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -163,6 +163,10 @@
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
#define SOC_GPIO_IN_RANGE_MAX 48
#define SOC_GPIO_OUT_RANGE_MAX 48
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL

8
components/soc/linux/include/soc/Kconfig.soc_caps.in
View File

@ -2,3 +2,11 @@
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_GPIO_IN_RANGE_MAX
int
default 65535
config SOC_GPIO_OUT_RANGE_MAX
int
default 65535

6
components/soc/linux/include/soc/soc_caps.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,3 +23,7 @@
*/
#pragma once
// No meaning to define GPIO number for Linux target, only to avoid build warning on Kconfig ESP_CONSOLE_UART_TX_GPIO, ESP_CONSOLE_UART_RX_GPIO
#define SOC_GPIO_IN_RANGE_MAX (65535)
#define SOC_GPIO_OUT_RANGE_MAX (65535)