diff --git a/components/esp_hw_support/include/soc/esp32c2/memprot.h b/components/esp_hw_support/include/soc/esp32c2/memprot.h index c0db1ee5b1..c7b1ad461e 100644 --- a/components/esp_hw_support/include/soc/esp32c2/memprot.h +++ b/components/esp_hw_support/include/soc/esp32c2/memprot.h @@ -27,14 +27,6 @@ extern "C" { #define DRAM_SRAM_START 0x3FC7C000 #endif -#ifndef MAP_DRAM_TO_IRAM -#define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + IRAM_SRAM_START) -#endif - -#ifndef MAP_IRAM_TO_DRAM -#define MAP_IRAM_TO_DRAM(addr) (addr - IRAM_SRAM_START + DRAM_SRAM_START) -#endif - typedef enum { MEMPROT_NONE = 0x00000000, MEMPROT_IRAM0_SRAM = 0x00000001, diff --git a/components/hal/include/hal/memprot_types.h b/components/hal/include/hal/memprot_types.h index 21e2c43060..0c0e7ee797 100644 --- a/components/hal/include/hal/memprot_types.h +++ b/components/hal/include/hal/memprot_types.h @@ -50,9 +50,6 @@ typedef enum { } memprot_hal_area_t; //auxiliary macros & defines -#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) -#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) #define MEMP_HAL_CHECK_IRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_IRAM_LOW || x >= SOC_DIRAM_IRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } #define MEMP_HAL_CHECK_DRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_DRAM_LOW || x >= SOC_DIRAM_DRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } diff --git a/components/heap/port/esp32c2/memory_layout.c b/components/heap/port/esp32c2/memory_layout.c index 0fbc8e1b09..875353199e 100644 --- a/components/heap/port/esp32c2/memory_layout.c +++ b/components/heap/port/esp32c2/memory_layout.c @@ -52,13 +52,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6E0000) const soc_memory_region_t soc_memory_regions[] = { { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1 { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2 { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3 - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area) }; diff --git a/components/heap/port/esp32c3/memory_layout.c b/components/heap/port/esp32c3/memory_layout.c index 07c8a37cee..0b899d8bb3 100644 --- a/components/heap/port/esp32c3/memory_layout.c +++ b/components/heap/port/esp32c3/memory_layout.c @@ -61,13 +61,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index 6e9fbd0c0c..d84f4852a8 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -61,13 +61,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 5d1bbb132a..0c058156e6 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -57,7 +57,6 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * Register the shared buffer area of the last memory block into the heap during heap initialization */ #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) -#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6F0000) const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM @@ -73,7 +72,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), 2, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM #endif diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index 0a5008b08c..e7c9bdc5fc 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -175,6 +175,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FCA0000 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 @@ -187,8 +191,6 @@ //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FCA0000 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 -#define SOC_MEM_INTERNAL_LOW1 0x4037C000 -#define SOC_MEM_INTERNAL_HIGH1 0x403C0000 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index a0733b0228..dc8be888d8 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -179,6 +179,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC80000 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 @@ -191,10 +195,6 @@ //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FC80000 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 -#define SOC_MEM_INTERNAL_LOW1 0x40370000 -#define SOC_MEM_INTERNAL_HIGH1 0x403E0000 -#define SOC_MEM_INTERNAL_LOW2 0x600FE000 -#define SOC_MEM_INTERNAL_HIGH2 0x60100000 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index b452f371c1..8118b8662f 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -179,6 +179,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC80000 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 @@ -191,10 +195,6 @@ //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). #define SOC_MEM_INTERNAL_LOW 0x3FC80000 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 -#define SOC_MEM_INTERNAL_LOW1 0x40370000 -#define SOC_MEM_INTERNAL_HIGH1 0x403E0000 -#define SOC_MEM_INTERNAL_LOW2 0x600FE000 -#define SOC_MEM_INTERNAL_HIGH2 0x60100000 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index fe25297917..ceebf485e4 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -181,6 +181,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FFB0000 #define SOC_DIRAM_DRAM_HIGH 0x40000000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFB0000 #define SOC_DMA_HIGH 0x40000000 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index b1b256d4a8..0517b54e81 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -199,6 +199,10 @@ #define SOC_DIRAM_DRAM_LOW 0x3FC88000 #define SOC_DIRAM_DRAM_HIGH 0x3FCF0000 +#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) +#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) + // Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FC88000 #define SOC_DMA_HIGH 0x3FD00000 diff --git a/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c b/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c index bcee035e0f..b0a596d5d3 100644 --- a/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c +++ b/tools/test_apps/system/memprot/main/esp32s2/test_memprot_main.c @@ -95,9 +95,6 @@ static uint8_t fnc_call0_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x0 volatile bool g_override_illegal_instruction = false; -#define MAP_DRAM_TO_IRAM(addr) (addr - SOC_DIRAM_DRAM_LOW + SOC_DIRAM_IRAM_LOW) -#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_DIRAM_IRAM_LOW + SOC_DIRAM_DRAM_LOW) - #define SRAM_TEST_BUFFER_SIZE 0x400 #define SRAM_TEST_OFFSET 0x200