mirror of
https://github.com/espressif/esp-idf
synced 2025-03-09 09:09:10 -04:00
Merge branch 'fix/esp_tee_aes_sha_prot' into 'master'
fix(esp_tee): Protect the AES/SHA clock registers from REE access Closes IDF-8954 and IDF-7188 See merge request espressif/esp-idf!36783
This commit is contained in:
Mahavir Jain
commit
8014ffa225
@ -291,8 +291,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE);
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#endif
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periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
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#if !CONFIG_SECURE_ENABLE_TEE
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// NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals
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periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
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#endif
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periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
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@ -43,9 +43,8 @@ typedef struct {
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uint32_t magic_word;
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uint32_t api_major_version;
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uint32_t api_minor_version;
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uint32_t reserved[2];
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uint32_t reserved[3];
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/* TEE-related fields */
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void *s_entry_addr;
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void *s_int_handler;
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/* REE-related fields */
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void *ns_entry_addr;
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@ -85,14 +84,12 @@ uint32_t esp_tee_service_call_with_noniram_intr_disabled(int argc, ...);
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#if !(__DOXYGEN__)
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/* Offsets of some values in esp_tee_config_t that are used by assembly code */
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#define ESP_TEE_CFG_OFFS_S_ENTRY_ADDR 0x14
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#define ESP_TEE_CFG_OFFS_S_INTR_HANDLER 0x18
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#define ESP_TEE_CFG_OFFS_NS_ENTRY_ADDR 0x1C
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#define ESP_TEE_CFG_OFFS_NS_INTR_HANDLER 0x20
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#if !defined(__ASSEMBLER__)
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/* Check the offsets are correct using the C compiler */
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ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, s_entry_addr) == ESP_TEE_CFG_OFFS_S_ENTRY_ADDR, "offset macro is wrong");
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ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, s_int_handler) == ESP_TEE_CFG_OFFS_S_INTR_HANDLER, "offset macro is wrong");
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ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, ns_entry_addr) == ESP_TEE_CFG_OFFS_NS_ENTRY_ADDR, "offset macro is wrong");
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ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, ns_int_handler) == ESP_TEE_CFG_OFFS_NS_INTR_HANDLER, "offset macro is wrong");
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@ -208,6 +208,10 @@ secure_services:
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type: IDF
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function: esp_sha_write_digest_state
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args: 2
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- id: 132
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type: IDF
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function: esp_sha_enable_periph_clk
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args: 1
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# ID: 134-149 (16) - eFuse
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- family: efuse
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entries:
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@ -228,6 +228,11 @@ void __wrap_esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state
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esp_tee_service_call(3, SS_ESP_SHA_WRITE_DIGEST_STATE, sha_type, digest_state);
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}
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void __wrap_esp_sha_enable_periph_clk(bool enable)
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{
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esp_tee_service_call(2, SS_ESP_SHA_ENABLE_PERIPH_CLK, enable);
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}
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/* ---------------------------------------------- MMU HAL ------------------------------------------------- */
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void IRAM_ATTR __wrap_mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len)
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -25,9 +25,9 @@ esp_tee_config_t esp_tee_app_config __attribute__((section(".esp_tee_app_cfg")))
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.api_major_version = ESP_TEE_API_MAJOR_VER,
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.api_minor_version = ESP_TEE_API_MINOR_VER,
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/* .s_entry_addr and .s_intr_handler are NULL in the
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app binary, but will be written by the TEE before it loads the binary
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*/
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/* s_intr_handler is NULL in the REE image, but will be written by
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* the TEE before it loads the binary
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*/
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.ns_int_handler = &_tee_interrupt_handler,
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.ns_entry_addr = &_u2m_switch,
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@ -20,8 +20,7 @@ set(srcs "core/esp_tee_init.c"
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# Arch specific implementation for TEE
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list(APPEND srcs "arch/${arch}/esp_tee_vectors.S"
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"arch/${arch}/esp_tee_vector_table.S"
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"arch/${arch}/esp_tee_secure_entry.S")
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"arch/${arch}/esp_tee_vector_table.S")
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# SoC specific implementation for TEE
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list(APPEND srcs "soc/${target}/esp_tee_secure_sys_cfg.c"
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@ -78,7 +77,9 @@ list(APPEND srcs "common/esp_app_desc_tee.c")
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${include})
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set_source_files_properties("core/esp_secure_services.c" PROPERTIES COMPILE_FLAGS -Wno-deprecated)
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# TODO: Currently only -Og optimization level works correctly at runtime
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set_source_files_properties("core/esp_secure_dispatcher.c" PROPERTIES COMPILE_FLAGS "-Og")
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include(${CMAKE_CURRENT_LIST_DIR}/ld/esp_tee_ld.cmake)
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# esp_app_desc_t configuration structure for TEE: Linking symbol and trimming project version and name
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@ -1,42 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/tee_reg.h"
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#include "soc/plic_reg.h"
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.global esp_tee_service_dispatcher
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/* Entry point to the secure world (i.e. M-mode) - responsible for
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* setting up the execution environment for the secure world */
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.section .text
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.align 4
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.global _sec_world_entry
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.type _sec_world_entry, @function
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_sec_world_entry:
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/* Setup the APM for HP CPU in TEE mode */
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li t0, TEE_M0_MODE_CTRL_REG
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sw zero, 0(t0) /* APM_LL_SECURE_MODE_TEE = 0 */
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/* Disable the U-mode delegation of all interrupts */
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csrwi mideleg, 0
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/* Jump to the secure service dispatcher */
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jal esp_tee_service_dispatcher
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/* Setup the APM for HP CPU in REE mode */
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li t0, TEE_M0_MODE_CTRL_REG
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li t1, 0x1 /* APM_LL_SECURE_MODE_REE = 1 */
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sw t1, 0(t0)
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/* Enable the U-mode delegation of all interrupts (except the TEE secure interrupt) */
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li t0, 0xffffbfff
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csrw mideleg, t0
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/* Fire an M-ecall */
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mv a1, zero
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ecall
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fence
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ret
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,6 +12,7 @@
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#include "riscv/encoding.h"
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#include "riscv/rvruntime-frames.h"
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#include "esp_private/vectors_const.h"
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#include "esp_tee.h"
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#include "sdkconfig.h"
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@ -25,9 +26,12 @@
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.equ ECALL_U_MODE, 0x8
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.equ ECALL_M_MODE, 0xb
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.equ TEE_APM_INTR_MASK_0, 0x00300000
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.equ TEE_APM_INTR_MASK_1, 0x000000F8
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.equ TEE_APM_INTR_MASK_1, 0x000000f8
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.equ TEE_INTR_DELEG_MASK, 0xffffbfff
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.global esp_tee_global_interrupt_handler
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.global esp_tee_service_dispatcher
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.section .data
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.align 4
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@ -177,15 +181,18 @@ _panic_handler:
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addi sp, sp, -16
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sw t0, 0(sp)
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/* Check whether the exception is an M-mode ecall */
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/* Read mcause */
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csrr t0, mcause
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xori t0, t0, ECALL_M_MODE
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beqz t0, _machine_ecall
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li t1, VECTORS_MCAUSE_INTBIT_MASK | VECTORS_MCAUSE_REASON_MASK
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and t0, t0, t1
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/* Check whether the exception is an M-mode ecall */
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li t1, ECALL_M_MODE
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beq t0, t1, _machine_ecall
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/* Check whether the exception is an U-mode ecall */
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csrr t0, mcause
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xori t0, t0, ECALL_U_MODE
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beqz t0, _user_ecall
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li t1, ECALL_U_MODE
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beq t0, t1, _user_ecall
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/* Restore t0 from the stack */
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lw t0, 0(sp)
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@ -250,6 +257,10 @@ _return_from_exception:
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_ecall_handler:
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/* M-mode ecall handler */
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_machine_ecall:
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/* Set the privilege mode to transition to after mret to U-mode */
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li t0, MSTATUS_MPP
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csrc mstatus, t0
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/* Check whether this is the first M-mode ecall (see esp_tee_init) and skip context restoration */
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lui t0, ESP_TEE_M2U_SWITCH_MAGIC
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beq a1, t0, _skip_ctx_restore
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@ -267,15 +278,10 @@ _machine_ecall:
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restore_general_regs RV_STK_FRMSZ
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csrrw a0, mscratch, zero
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/* This point is reached only after the first M-mode ecall, never again (see esp_tee_init) */
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_skip_ctx_restore:
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/* Copy the ra register to mepc which contains the user app entry point (i.e. call_start_cpu0) */
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csrw mepc, ra
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/* Set the privilege mode to transition to after mret to U-mode */
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li t3, MSTATUS_MPP
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csrc mstatus, t3
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/* Jump to the REE */
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mret
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@ -291,28 +297,34 @@ _user_ecall:
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lw t0, 0(sp)
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addi sp, sp, 16
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/* This point is reached after a secure service call is issued from the REE */
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/* Save register context and the mepc */
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/* This point is reached when a secure service call is issued from the REE */
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/* Save register context and mepc */
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save_general_regs RV_STK_FRMSZ
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save_mepc
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/* Saving the U-mode (i.e. REE) stack pointer */
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/* Save the U-mode (i.e. REE) stack pointer */
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la t0, _ns_sp
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sw sp, 0(t0)
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/* Switching to the M-mode (i.e. TEE) stack */
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/* Switch to the M-mode (i.e. TEE) stack */
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la sp, _tee_stack
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/* Load the TEE entry point (see sec_world_entry) in the mepc */
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la t2, esp_tee_app_config
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lw t2, ESP_TEE_CFG_OFFS_S_ENTRY_ADDR(t2)
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csrw mepc, t2
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/* Disable the U-mode delegation of all interrupts */
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csrwi mideleg, 0
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/* Set the privilege mode to transition to after mret to M-mode */
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li t3, MSTATUS_MPP
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csrs mstatus, t3
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/* Enable interrupts */
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csrsi mstatus, MSTATUS_MIE
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mret
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/* Jump to the secure service dispatcher */
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jal esp_tee_service_dispatcher
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/* Enable the U-mode delegation of all interrupts (except the TEE secure interrupt) */
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li t0, TEE_INTR_DELEG_MASK
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csrs mideleg, t0
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/* Fire an M-ecall */
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mv a1, zero
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ecall
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/* This point is reached after servicing a U-mode interrupt occurred
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* while executing a secure service */
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@ -333,7 +345,7 @@ _rtn_from_ns_int:
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/* Restore register context and resume the secure service */
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restore_mepc
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restore_general_regs
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restore_general_regs RV_STK_FRMSZ
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mret
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@ -347,7 +359,7 @@ _rtn_from_ns_int:
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_tee_ns_intr_handler:
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/* Start by saving the general purpose registers and the PC value before
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* the interrupt happened. */
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save_general_regs
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save_general_regs RV_STK_FRMSZ
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save_mepc
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/* Though it is not necessary we save GP and SP here.
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@ -357,7 +369,7 @@ _tee_ns_intr_handler:
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/* As gp register is not saved by the macro, save it here */
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sw gp, RV_STK_GP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, CONTEXT_SIZE /* restore sp with the value when interrupt happened */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when interrupt happened */
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/* Save SP */
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sw t0, RV_STK_SP(sp)
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@ -395,8 +407,8 @@ _tee_ns_intr_handler:
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csrw mscratch, t0
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/* Enable the U-mode interrupt delegation (except for the TEE secure interrupt) */
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li t0, 0xffffbfff
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csrw mideleg, t0
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li t0, TEE_INTR_DELEG_MASK
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csrs mideleg, t0
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/* Place magic bytes in all the general registers */
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store_magic_general_regs
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@ -413,7 +425,7 @@ _tee_ns_intr_handler:
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_tee_s_intr_handler:
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/* Start by saving the general purpose registers and the PC value before
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* the interrupt happened. */
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save_general_regs
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save_general_regs RV_STK_FRMSZ
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save_mepc
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/* Though it is not necessary we save GP and SP here.
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@ -423,7 +435,7 @@ _tee_s_intr_handler:
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/* As gp register is not saved by the macro, save it here */
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sw gp, RV_STK_GP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, CONTEXT_SIZE /* restore sp with the value when interrupt happened */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when interrupt happened */
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/* Save SP */
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sw t0, RV_STK_SP(sp)
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@ -457,7 +469,7 @@ _save_reg_ctx:
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_continue:
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/* Before doing anything preserve the stack pointer */
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mv s11, sp
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/* Switching to the TEE interrupt stack */
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/* Switch to the TEE interrupt stack */
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la sp, _tee_intr_stack
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/* If this is a non-nested interrupt, SP now points to the interrupt stack */
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@ -527,7 +539,7 @@ _intr_hdlr_exec:
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mv sp, s11
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restore_mepc
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restore_general_regs
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restore_general_regs RV_STK_FRMSZ
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/* exit, this will also re-enable the interrupts */
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mret
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@ -3,7 +3,7 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <stdarg.h>
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#include "esp_log.h"
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#include "esp_tee.h"
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@ -34,13 +34,10 @@ static const secure_service_entry_t *find_service_by_id(uint32_t id)
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}
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/**
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* @brief Entry point to the TEE binary during secure service call. It decipher the call and dispatch it
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* to corresponding Secure Service API in secure world.
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* TODO: Fix the assembly routine here for compatibility with all levels of compiler optimizations
|
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* @brief Handles incoming secure service requests to the TEE.
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* Validates and routes each request to the appropriate
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* secure service implementation.
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*/
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#pragma GCC push_options
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#pragma GCC optimize ("Og")
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int esp_tee_service_dispatcher(int argc, va_list ap)
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{
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if (argc > ESP_TEE_MAX_INPUT_ARG) {
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@ -50,7 +47,7 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
|
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}
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int ret = -1;
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uint32_t argv[ESP_TEE_MAX_INPUT_ARG], *argp;
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uint32_t argv[ESP_TEE_MAX_INPUT_ARG] = {0};
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uint32_t sid = va_arg(ap, uint32_t);
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argc--;
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@ -58,13 +55,11 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
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const secure_service_entry_t *service = find_service_by_id(sid);
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if (service == NULL) {
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ESP_LOGE(TAG, "Invalid service ID!");
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va_end(ap);
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return ret;
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}
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if (argc != service->nargs) {
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ESP_LOGE(TAG, "Invalid number of arguments for service %d!", sid);
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va_end(ap);
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return ret;
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}
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@ -73,65 +68,47 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
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for (int i = 0; i < argc; i++) {
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argv[i] = va_arg(ap, uint32_t);
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}
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argp = &argv[0];
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va_end(ap);
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uint32_t *argp = &argv[0];
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asm volatile(
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"mv t0, %1 \n"
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"beqz t0, service_call \n"
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"mv t0, %1 \n" // t0 = argc
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"mv t1, %3 \n" // t1 = argp
|
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"li t2, 8 \n" // t2 = 8 (max register args)
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"ble t0, t2, load_regs \n" // If argc <= 8 (a0-a7), skip stack routine
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// Store extra args (argc > 8) on stack
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"mv t3, sp \n"
|
||||
"addi t1, t1, 32 \n"
|
||||
|
||||
"stack_loop: \n"
|
||||
"lw t4, 0(t1) \n"
|
||||
"sw t4, 0(t3) \n"
|
||||
"addi t1, t1, 4 \n"
|
||||
"addi t3, t3, 4 \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"bge t0, t2, stack_loop \n"
|
||||
|
||||
// Load the first 8 arguments into a0-a7
|
||||
"load_regs: \n"
|
||||
"lw a0, 0(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a1, 4(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a2, 8(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a3, 12(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a4, 16(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a5, 20(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a6, 24(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
|
||||
"lw a7, 28(%3) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"beqz t0, service_call \n"
|
||||
"fence \n"
|
||||
|
||||
"addi %3, %3, 32 \n"
|
||||
"mv t2, sp \n"
|
||||
"loop: \n"
|
||||
"lw t1, 0(%3) \n"
|
||||
"sw t1, 0(t2) \n"
|
||||
"addi t0, t0, -1 \n"
|
||||
"addi t2, t2, 4 \n"
|
||||
"addi %3, %3, 4 \n"
|
||||
"bnez t0, loop \n"
|
||||
|
||||
"service_call: \n"
|
||||
"mv t1, %2 \n"
|
||||
"jalr 0(t1) \n"
|
||||
"mv %0, a0 \n"
|
||||
"mv t1, %2 \n" // Load function pointer
|
||||
"jalr 0(t1) \n" // Call function
|
||||
"mv %0, a0 \n" // Store return value
|
||||
: "=r"(ret)
|
||||
: "r"(argc), "r"(fp_secure_service), "r"(argp)
|
||||
: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "t0", "t1", "t2"
|
||||
: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
|
||||
"t0", "t1", "t2", "t3", "t4"
|
||||
);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#pragma GCC pop_options
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include "soc/soc_caps.h"
|
||||
#include "aes/esp_aes.h"
|
||||
#include "sha/sha_core.h"
|
||||
#include "esp_sha_internal.h"
|
||||
|
||||
#include "esp_tee.h"
|
||||
#include "esp_tee_memory_utils.h"
|
||||
@ -325,6 +326,11 @@ void _ss_esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_fi
|
||||
esp_sha_block(sha_type, data_block, is_first_block);
|
||||
}
|
||||
|
||||
void _ss_esp_sha_enable_periph_clk(bool enable)
|
||||
{
|
||||
esp_sha_enable_periph_clk(enable);
|
||||
}
|
||||
|
||||
/* ---------------------------------------------- OTA ------------------------------------------------- */
|
||||
|
||||
int _ss_esp_tee_ota_begin(void)
|
||||
|
||||
@ -59,7 +59,6 @@ static void tee_init_app_config(void)
|
||||
esp_tee_app_config.api_minor_version = ESP_TEE_API_MINOR_VER;
|
||||
|
||||
/* Set the TEE-related fields (from the TEE binary) that the REE will use to interface with TEE */
|
||||
esp_tee_app_config.s_entry_addr = &_sec_world_entry;
|
||||
esp_tee_app_config.s_int_handler = &_tee_s_intr_handler;
|
||||
}
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include "soc/soc.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
|
||||
extern void tee_apm_violation_isr(void *arg);
|
||||
|
||||
@ -91,34 +92,41 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = {
|
||||
.regn_pms = 0x6,
|
||||
.filter_enable = 1,
|
||||
},
|
||||
/* Region 5: Peripherals [RSA - TEE Controller & APM] (RW) */
|
||||
/* Protected: APM, TEE Controller */
|
||||
/* Region 5/6: Peripherals [RSA - TEE Controller & APM] (RW) */
|
||||
/* Protected: AES + SHA PCR, APM, TEE Controller */
|
||||
{
|
||||
.regn_num = 5,
|
||||
.regn_start_addr = DR_REG_RSA_BASE,
|
||||
.regn_end_addr = (PCR_AES_CONF_REG - 0x4),
|
||||
.regn_pms = 0x6,
|
||||
.filter_enable = 1,
|
||||
},
|
||||
{
|
||||
.regn_num = 6,
|
||||
.regn_start_addr = PCR_RSA_CONF_REG,
|
||||
.regn_end_addr = (DR_REG_TEE_BASE - 0x4),
|
||||
.regn_pms = 0x6,
|
||||
.filter_enable = 1,
|
||||
},
|
||||
/* Region 6: Peripherals [Miscellaneous - PMU] (RW) */
|
||||
/* Region 7: Peripherals [Miscellaneous - PMU] (RW) */
|
||||
{
|
||||
.regn_num = 6,
|
||||
.regn_num = 7,
|
||||
.regn_start_addr = DR_REG_MISC_BASE,
|
||||
.regn_end_addr = (DR_REG_PMU_BASE - 0x04),
|
||||
.regn_pms = 0x6,
|
||||
.filter_enable = 1,
|
||||
},
|
||||
/* Region 7: Peripherals [DEBUG - PWDET] (RW) */
|
||||
/* Region 8: Peripherals [DEBUG - PWDET] (RW) */
|
||||
{
|
||||
.regn_num = 7,
|
||||
.regn_num = 8,
|
||||
.regn_start_addr = DR_REG_OPT_DEBUG_BASE,
|
||||
.regn_end_addr = 0x600D0000,
|
||||
.regn_pms = 0x6,
|
||||
.filter_enable = 1,
|
||||
},
|
||||
/* Region 8: REE SRAM region (RW) */
|
||||
/* Region 9: REE SRAM region (RW) */
|
||||
{
|
||||
.regn_num = 8,
|
||||
.regn_num = 9,
|
||||
.regn_start_addr = SOC_NS_IRAM_START,
|
||||
.regn_end_addr = SOC_IRAM_HIGH,
|
||||
.regn_pms = 0x6,
|
||||
@ -164,9 +172,9 @@ apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data = {
|
||||
|
||||
/* HP_APM: TEE mode accessible regions */
|
||||
apm_ctrl_region_config_data_t hp_apm_pms_data_tee[] = {
|
||||
/* Region 9: Entire memory region (RWX)*/
|
||||
/* Region 10: Entire memory region (RWX)*/
|
||||
{
|
||||
.regn_num = 9,
|
||||
.regn_num = 10,
|
||||
.regn_start_addr = 0x0,
|
||||
.regn_end_addr = ~0x0,
|
||||
.regn_pms = 0x7,
|
||||
@ -303,6 +311,9 @@ void esp_tee_configure_apm_protection(void)
|
||||
/* Disable all control filter first to have full access of address rage. */
|
||||
apm_hal_apm_ctrl_filter_enable_all(false);
|
||||
|
||||
/* Switch HP_CPU to TEE mode */
|
||||
apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_TEE);
|
||||
|
||||
/* LP APM0 configuration. */
|
||||
lp_apm0_sec_mode_data.regn_count = sizeof(lp_apm0_pms_data) / sizeof(apm_ctrl_region_config_data_t);
|
||||
apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm0_sec_mode_data);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -12,6 +12,7 @@
|
||||
#include "esp_cpu.h"
|
||||
#include "esp_log.h"
|
||||
#include "hal/apm_hal.h"
|
||||
#include "hal/clk_gate_ll.h"
|
||||
|
||||
#include "esp_tee.h"
|
||||
#include "esp_tee_intr.h"
|
||||
@ -91,13 +92,14 @@ void esp_tee_soc_secure_sys_init(void)
|
||||
esp_tee_protect_intr_src(ETS_EFUSE_INTR_SOURCE); // eFuse
|
||||
esp_tee_protect_intr_src(ETS_AES_INTR_SOURCE); // AES
|
||||
esp_tee_protect_intr_src(ETS_SHA_INTR_SOURCE); // SHA
|
||||
|
||||
/* Disable AES/SHA peripheral clocks; they will be toggled as needed when the peripheral is in use */
|
||||
periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
|
||||
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
|
||||
}
|
||||
|
||||
IRAM_ATTR inline void esp_tee_switch_to_ree(uint32_t ree_entry_addr)
|
||||
{
|
||||
/* Switch HP_CPU to REE0 mode. */
|
||||
apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_REE0);
|
||||
|
||||
/* 2nd argument is used as magic value to detect very first M2U switch */
|
||||
/* TBD: clean this up and use proper temporary register instead of a1 */
|
||||
/* Switch to non-secure world and launch App. */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -10,16 +10,17 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_attr.h"
|
||||
|
||||
#define TEE_TEST_INT_COUNT 3
|
||||
|
||||
uint32_t __attribute__((__noinline__)) esp_tee_service_add(uint32_t a, uint32_t b);
|
||||
uint32_t NOINLINE_ATTR esp_tee_service_add(uint32_t a, uint32_t b);
|
||||
|
||||
uint32_t __attribute__((__noinline__)) esp_tee_service_sub(uint32_t a, uint32_t b);
|
||||
uint32_t NOINLINE_ATTR esp_tee_service_sub(uint32_t a, uint32_t b);
|
||||
|
||||
uint32_t __attribute__((__noinline__)) esp_tee_service_mul(uint32_t a, uint32_t b);
|
||||
uint32_t NOINLINE_ATTR esp_tee_service_mul(uint32_t a, uint32_t b);
|
||||
|
||||
uint32_t __attribute__((__noinline__)) esp_tee_service_div(uint32_t a, uint32_t b);
|
||||
uint32_t NOINLINE_ATTR esp_tee_service_div(uint32_t a, uint32_t b);
|
||||
|
||||
int esp_tee_secure_int_test(void);
|
||||
|
||||
@ -33,7 +34,7 @@ int esp_tee_test_illegal_instr(void);
|
||||
|
||||
int esp_tee_test_instr_fetch_prohibited(uint32_t type);
|
||||
|
||||
void dummy_secure_service(void);
|
||||
void NOINLINE_ATTR dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i);
|
||||
|
||||
uint32_t add_in_loop(uint32_t a, uint32_t b, uint32_t iter);
|
||||
|
||||
|
||||
@ -64,7 +64,7 @@ secure_services:
|
||||
- id: 215
|
||||
type: custom
|
||||
function: dummy_secure_service
|
||||
args: 0
|
||||
args: 9
|
||||
- id: 216
|
||||
type: custom
|
||||
function: add_in_loop
|
||||
|
||||
@ -7,8 +7,10 @@
|
||||
#include "esp_tee.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
void _ss_dummy_secure_service(void)
|
||||
void NOINLINE_ATTR _ss_dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i)
|
||||
{
|
||||
esp_rom_printf("Dummy secure service\n");
|
||||
*i = a + b + c + d + e + f + g + h;
|
||||
}
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
#include "esp_tee.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
void dummy_secure_service(void)
|
||||
void dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i)
|
||||
{
|
||||
esp_tee_service_call(1, SS_DUMMY_SECURE_SERVICE);
|
||||
esp_tee_service_call(10, SS_DUMMY_SECURE_SERVICE, a, b, c, d, e, f, g, h, i);
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -7,30 +7,30 @@
|
||||
#include "esp_log.h"
|
||||
#include "esp_tee.h"
|
||||
#include "esp_tee_test.h"
|
||||
|
||||
#include "esp_attr.h"
|
||||
static const char *TAG = "test_sec_srv";
|
||||
|
||||
/* Sample Trusted App */
|
||||
|
||||
uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_add(uint32_t a, uint32_t b)
|
||||
uint32_t NOINLINE_ATTR _ss_esp_tee_service_add(uint32_t a, uint32_t b)
|
||||
{
|
||||
ESP_LOGD(TAG, "SS: %s", __func__);
|
||||
return (a + b);
|
||||
}
|
||||
|
||||
uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_sub(uint32_t a, uint32_t b)
|
||||
uint32_t NOINLINE_ATTR _ss_esp_tee_service_sub(uint32_t a, uint32_t b)
|
||||
{
|
||||
ESP_LOGD(TAG, "SS: %s", __func__);
|
||||
return (a - b);
|
||||
}
|
||||
|
||||
uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_mul(uint32_t a, uint32_t b)
|
||||
uint32_t NOINLINE_ATTR _ss_esp_tee_service_mul(uint32_t a, uint32_t b)
|
||||
{
|
||||
ESP_LOGD(TAG, "SS: %s", __func__);
|
||||
return (a * b);
|
||||
}
|
||||
|
||||
uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_div(uint32_t a, uint32_t b)
|
||||
uint32_t NOINLINE_ATTR _ss_esp_tee_service_div(uint32_t a, uint32_t b)
|
||||
{
|
||||
ESP_LOGD(TAG, "SS: %s", __func__);
|
||||
return (a / b);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -68,7 +68,9 @@ TEST_CASE("Test multiple calls to sample app (basic services)", "[basic]")
|
||||
|
||||
TEST_CASE("Custom secure service call", "[basic]")
|
||||
{
|
||||
dummy_secure_service();
|
||||
int res = -1;
|
||||
dummy_secure_service(1, 2, 3, 4, 5, 6, 7, 8, &res);
|
||||
TEST_ASSERT_EQUAL_UINT32(36, res);
|
||||
}
|
||||
|
||||
void test_task(void *pvParameters)
|
||||
|
||||
@ -56,6 +56,13 @@ static inline esp_sha_mode sha_operation_mode(size_t length)
|
||||
return SHA_BLOCK_MODE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the SHA peripheral clock
|
||||
*
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
void esp_sha_enable_periph_clk(bool enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
#include "esp_private/esp_crypto_lock_internal.h"
|
||||
#include "esp_log.h"
|
||||
#include "sha/sha_core.h"
|
||||
#include "esp_sha_internal.h"
|
||||
#include "hal/sha_hal.h"
|
||||
#include "hal/sha_ll.h"
|
||||
#include "soc/soc_caps.h"
|
||||
@ -51,6 +52,15 @@
|
||||
#endif
|
||||
#endif /* SOC_SHA_SUPPORT_DMA */
|
||||
|
||||
#if !ESP_TEE_BUILD
|
||||
#define SHA_LOCK() esp_crypto_sha_aes_lock_acquire()
|
||||
#define SHA_RELEASE() esp_crypto_sha_aes_lock_release()
|
||||
#else
|
||||
#define SHA_RCC_ATOMIC()
|
||||
#define SHA_LOCK()
|
||||
#define SHA_RELEASE()
|
||||
#endif
|
||||
|
||||
void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state)
|
||||
{
|
||||
sha_hal_write_digest(sha_type, digest_state);
|
||||
@ -89,34 +99,16 @@ inline static size_t block_length(esp_sha_type type)
|
||||
/* Enable SHA peripheral and then lock it */
|
||||
void esp_sha_acquire_hardware(void)
|
||||
{
|
||||
#if !ESP_TEE_BUILD
|
||||
/* Released when releasing hw with esp_sha_release_hardware() */
|
||||
esp_crypto_sha_aes_lock_acquire();
|
||||
#endif
|
||||
|
||||
SHA_RCC_ATOMIC() {
|
||||
sha_ll_enable_bus_clock(true);
|
||||
sha_ll_reset_register();
|
||||
#if SOC_AES_CRYPTO_DMA
|
||||
crypto_dma_ll_enable_bus_clock(true);
|
||||
crypto_dma_ll_reset_register();
|
||||
#endif
|
||||
}
|
||||
SHA_LOCK();
|
||||
esp_sha_enable_periph_clk(true);
|
||||
}
|
||||
|
||||
/* Disable SHA peripheral block and then release it */
|
||||
void esp_sha_release_hardware(void)
|
||||
{
|
||||
SHA_RCC_ATOMIC() {
|
||||
sha_ll_enable_bus_clock(false);
|
||||
#if SOC_AES_CRYPTO_DMA
|
||||
crypto_dma_ll_enable_bus_clock(false);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !ESP_TEE_BUILD
|
||||
esp_crypto_sha_aes_lock_release();
|
||||
#endif
|
||||
esp_sha_enable_periph_clk(false);
|
||||
SHA_RELEASE();
|
||||
}
|
||||
|
||||
void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block)
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include "hal/sha_ll.h"
|
||||
#include "hal/sha_hal.h"
|
||||
#include "hal/sha_types.h"
|
||||
#include "soc/soc_caps.h"
|
||||
@ -20,10 +21,33 @@
|
||||
#include "sha/sha_parallel_engine.h"
|
||||
#else
|
||||
#include "sha/sha_core.h"
|
||||
#include "esp_sha_internal.h"
|
||||
#include "esp_private/esp_crypto_lock_internal.h"
|
||||
#if SOC_SHA_CRYPTO_DMA
|
||||
#include "hal/crypto_dma_ll.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static const char *TAG = "esp_sha";
|
||||
|
||||
#if !SOC_SHA_SUPPORT_PARALLEL_ENG
|
||||
void esp_sha_enable_periph_clk(bool enable)
|
||||
{
|
||||
SHA_RCC_ATOMIC() {
|
||||
sha_ll_enable_bus_clock(enable);
|
||||
if (enable) {
|
||||
sha_ll_reset_register();
|
||||
}
|
||||
#if SOC_SHA_CRYPTO_DMA
|
||||
crypto_dma_ll_enable_bus_clock(enable);
|
||||
if (enable) {
|
||||
crypto_dma_ll_reset_register();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output)
|
||||
{
|
||||
union {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user