From c11f49e2cb2a3cc18b211a9f88f786eac43e149a Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Tue, 18 Feb 2025 21:06:07 +0800 Subject: [PATCH 1/3] feat(soc): update esp32h21 pau registers --- .../esp32h21/include/soc/Kconfig.soc_caps.in | 18 +++++++++++++++++- components/soc/esp32h21/include/soc/soc_caps.h | 10 +++++----- components/soc/esp32h21/register/soc/pau_reg.h | 2 +- .../soc/esp32h21/register/soc/pau_struct.h | 2 +- 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 4c7a35ad72..92a2b39f61 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -669,7 +669,23 @@ config SOC_PM_SUPPORT_TOP_PD config SOC_PM_PAU_LINK_NUM int - default 4 + default 5 + +config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE + bool + default y + +config SOC_PM_CPU_RETENTION_BY_SW + bool + default y + +config SOC_PM_MODEM_RETENTION_BY_REGDMA + bool + default y + +config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY + bool + default y config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 7fd716a7d8..1a6c4bb68a 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -528,11 +528,11 @@ #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_SUPPORT_TOP_PD (1) -#define SOC_PM_PAU_LINK_NUM (4) -// #define SOC_PM_CPU_RETENTION_BY_SW (1) -// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) -// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*! Date: Tue, 18 Feb 2025 10:43:38 +0800 Subject: [PATCH 2/3] feat(hal): support esp32h21 pau hal layer --- .../hal/esp32h21/include/hal/lp_aon_ll.h | 138 +++++++++++++++++ components/hal/esp32h21/include/hal/pau_ll.h | 142 ++++++++++++++++++ components/hal/esp32h21/pau_hal.c | 82 ++++++++++ 3 files changed, 362 insertions(+) create mode 100644 components/hal/esp32h21/include/hal/lp_aon_ll.h create mode 100644 components/hal/esp32h21/include/hal/pau_ll.h create mode 100644 components/hal/esp32h21/pau_hal.c diff --git a/components/hal/esp32h21/include/hal/lp_aon_ll.h b/components/hal/esp32h21/include/hal/lp_aon_ll.h new file mode 100644 index 0000000000..64e8164180 --- /dev/null +++ b/components/hal/esp32h21/include/hal/lp_aon_ll.h @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H21 LP_AON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/lp_aon_struct.h" +#include "hal/misc.h" +#include "esp32h21/rom/rtc.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get ext1 wakeup source status + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_status); +} + +/** + * @brief Clear the ext1 wakeup source status + */ +static inline void lp_aon_ll_ext1_clear_wakeup_status(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_status_clr, 1); +} + +/** + * @brief Set the wake-up LP_IO of the ext1 wake-up source + * @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7 + * @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level + * each bit's corresponding position is set to 0, the wakeup level will be low + * on the contrary, each bit's corresponding position is set to 1, the wakeup + * level will be high + */ +static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, io_mask); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv, level_mask); +} + +/** + * @brief Clear all ext1 wakup-source setting + */ +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, 0); +} + +/** + * @brief Get ext1 wakeup source setting + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); +} + + +/** + * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. + * Set the flag to inform + * @param true: deepsleep false: lightsleep + */ +static inline void lp_aon_ll_inform_wakeup_type(bool dslp) +{ + if (dslp) { + REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ + + } else { + REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ + } +} + +/** + * @brief Set the maximum number of linked lists supported by REGDMA + * @param count: the maximum number of regdma link + */ +static inline void lp_aon_ll_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); +} + +/** + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. + * @param count: the maximum number of loop + */ +static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); +} + +/** + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing + * registers and gets stuck on the bus, a timeout will be triggered. + * @param count: the maximum number of time + */ +static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); +} + +/** + * @brief Set the regdma_link_addr + * @param addr: the addr of regdma_link + */ +static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); +} + +static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); +} + +static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h21/include/hal/pau_ll.h b/components/hal/esp32h21/include/hal/pau_ll.h new file mode 100644 index 0000000000..d927070687 --- /dev/null +++ b/components/hal/esp32h21/include/hal/pau_ll.h @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H21 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "soc/pcr_struct.h" +#include "hal/pau_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void pau_ll_enable_bus_clock(bool enable) +{ + if (enable) { + PCR.regdma_conf.regdma_clk_en = 1; + PCR.regdma_conf.regdma_rst_en = 0; + } else { + PCR.regdma_conf.regdma_clk_en = 0; + PCR.regdma_conf.regdma_rst_en = 1; + } +} + +static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ + return dev->regdma_conf.flow_err; +} + +static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ + dev->regdma_conf.link_sel = link; +} + +static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 1; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 0; +} + +static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) +{ + dev->regdma_conf.sel_mac = 1; +} + +static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev) +{ + dev->regdma_conf.sel_mac = 0; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev) +{ + dev->regdma_conf.start_mac = 1; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev) +{ + dev->regdma_conf.start_mac = 0; +} + +static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ + return dev->regdma_current_link_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ + return dev->regdma_peri_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ + return dev->regdma_mem_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ + return dev->int_raw.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ + return dev->int_st.val; +} + +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 1; +} + +static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 0; +} + +static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 1; +} + +static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 0; +} + +static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ + dev->int_clr.done_int_clr = 1; +} + +static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ + dev->int_clr.error_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h21/pau_hal.c b/components/hal/esp32h21/pau_hal.c new file mode 100644 index 0000000000..05da12e136 --- /dev/null +++ b/components/hal/esp32h21/pau_hal.c @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PAU (ESP32-H21 specific part) + +#include "soc/soc.h" +#include "soc/pcr_struct.h" +#include "esp_attr.h" +#include "hal/misc.h" +#include "hal/pau_hal.h" +#include "hal/pau_types.h" +#include "hal/lp_aon_ll.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); +} + +void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + pau_ll_set_regdma_select_wifimac_link(hal->dev); + pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_deselect_wifimac_link(hal->dev); + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules. + * It is also used as software trigger REGDMA to backup and restore, and is + * used by the UT to test module driver retention function. + */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +#if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE +void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) +{ + HAL_ASSERT(count > 0); + lp_aon_ll_set_regdma_link_count(count - 1); +} +#endif + +void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) +{ + HAL_ASSERT(loop_num > 0 && time > 0); + lp_aon_ll_set_regdma_link_loop_threshold(loop_num); + lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); +} + +void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) +{ + HAL_ASSERT(count > 0 && interval > 0); + lp_aon_ll_set_regdma_link_wait_retry_count(count); + lp_aon_ll_set_regdma_link_wait_read_interval(interval); +} From 93cdad7a3b504f7390bee32c6112aa89936b7fc3 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 19 Feb 2025 10:10:57 +0800 Subject: [PATCH 3/3] feat(esp_hw_support): support esp32h21 retention link software trigger --- components/esp_hw_support/CMakeLists.txt | 23 ++--- .../esp_hw_support/lowpower/CMakeLists.txt | 2 +- components/esp_hw_support/sleep_retention.c | 8 +- .../test_apps/.build-test-rules.yml | 4 +- components/soc/CMakeLists.txt | 2 +- .../esp32h21/include/soc/Kconfig.soc_caps.in | 8 ++ .../include/soc/retention_periph_defs.h | 89 +++++++++++++++++++ .../soc/esp32h21/include/soc/soc_caps.h | 3 +- components/soc/include/soc/ledc_periph.h | 2 +- 9 files changed, 124 insertions(+), 17 deletions(-) create mode 100644 components/soc/esp32h21/include/soc/retention_periph_defs.h diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 4235e184e2..262f235d3e 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -28,12 +28,6 @@ if(NOT non_os_build) "periph_ctrl.c" "revision.c" "rtc_module.c" - "sleep_modem.c" - "sleep_modes.c" - "sleep_console.c" - "sleep_usb.c" - "sleep_gpio.c" - "sleep_event.c" "regi2c_ctrl.c" "esp_gpio_reserve.c" "sar_periph_ctrl_common.c" @@ -49,14 +43,23 @@ if(NOT non_os_build) if(CONFIG_SOC_ADC_SUPPORTED) list(APPEND srcs "adc_share_hw_ctrl.c") endif() - if(CONFIG_SOC_ISP_SHARE_CSI_BRG) list(APPEND srcs "mipi_csi_share_hw_ctrl.c") endif() if(CONFIG_SOC_PAU_SUPPORTED) - list(APPEND srcs "sleep_retention.c" - "sleep_system_peripheral.c" - ) + list(APPEND srcs "sleep_retention.c") + endif() + if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) + list(APPEND srcs "sleep_modem.c" + "sleep_modes.c" + "sleep_console.c" + "sleep_usb.c" + "sleep_gpio.c" + "sleep_event.c" + ) + if(CONFIG_SOC_PAU_SUPPORTED) + list(APPEND srcs "sleep_system_peripheral.c") + endif() endif() # [refactor-todo] diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt index 2d4124bb61..bb470ef3b8 100644 --- a/components/esp_hw_support/lowpower/CMakeLists.txt +++ b/components/esp_hw_support/lowpower/CMakeLists.txt @@ -1,6 +1,6 @@ idf_build_get_property(non_os_build NON_OS_BUILD) -if(non_os_build) +if(non_os_build OR NOT CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) return() endif() diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c index d7b63cb63f..7df1d700cd 100644 --- a/components/esp_hw_support/sleep_retention.c +++ b/components/esp_hw_support/sleep_retention.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -514,7 +514,9 @@ static void sleep_retention_entries_destroy(sleep_retention_module_t module) } if (created_modules == 0) { sleep_retention_entries_check_and_distroy_final_default(); +#if SOC_LIGHT_SLEEP_SUPPORTED pmu_sleep_disable_regdma_backup(); +#endif memset((void *)s_retention.lists, 0, sizeof(s_retention.lists)); s_retention.highpri = (uint8_t)-1; } @@ -641,8 +643,12 @@ esp_err_t sleep_retention_entries_create(const sleep_retention_entries_config_t if (err) goto error; err = sleep_retention_entries_create_wrapper(retent, num, priority, module); if (err) goto error; +#if SOC_LIGHT_SLEEP_SUPPORTED pmu_sleep_enable_regdma_backup(); +#endif +#if SOC_LIGHT_SLEEP_SUPPORTED && SOC_DEEP_SLEEP_SUPPORTED ESP_ERROR_CHECK(esp_deep_sleep_register_hook(&pmu_sleep_disable_regdma_backup)); +#endif error: return err; diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index 90b80e7967..43d2838e14 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -44,8 +44,8 @@ components/esp_hw_support/test_apps/rtc_power_modes: components/esp_hw_support/test_apps/sleep_retention: enable: - - if: SOC_PAU_SUPPORTED == 1 and CONFIG_NAME != "xip_psram" - - if: SOC_PAU_SUPPORTED == 1 and (SOC_SPIRAM_XIP_SUPPORTED == 1 and CONFIG_NAME == "xip_psram") + - if: SOC_PAU_SUPPORTED == 1 and SOC_LIGHT_SLEEP_SUPPORTED == 1 and CONFIG_NAME != "xip_psram" + - if: SOC_PAU_SUPPORTED == 1 and SOC_LIGHT_SLEEP_SUPPORTED == 1 and (SOC_SPIRAM_XIP_SUPPORTED == 1 and CONFIG_NAME == "xip_psram") components/esp_hw_support/test_apps/vad_wakeup: disable: diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 8bdbe3c63d..e446e96994 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -165,7 +165,7 @@ if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED) list(APPEND srcs "${target_folder}/sdio_slave_periph.c") endif() -if(CONFIG_SOC_PAU_SUPPORTED) +if(CONFIG_SOC_PAU_SUPPORTED AND CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) list(APPEND srcs "${target_folder}/system_retention_periph.c") endif() diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 92a2b39f61..2d7188f64b 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -43,6 +43,10 @@ config SOC_SPI_FLASH_SUPPORTED bool default y +config SOC_PAU_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_32M bool default y @@ -671,6 +675,10 @@ config SOC_PM_PAU_LINK_NUM int default 5 +config SOC_PM_RETENTION_MODULE_NUM + int + default 32 + config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE bool default y diff --git a/components/soc/esp32h21/include/soc/retention_periph_defs.h b/components/soc/esp32h21/include/soc/retention_periph_defs.h new file mode 100644 index 0000000000..44a487382f --- /dev/null +++ b/components/soc/esp32h21/include/soc/retention_periph_defs.h @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum periph_retention_module { + SLEEP_RETENTION_MODULE_MIN = 0, + SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ + /* clock module, which includes system and modem */ + SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, + /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, + * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ + SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + /* Timer Group by target*/ + SLEEP_RETENTION_MODULE_TG0_WDT = 4, + SLEEP_RETENTION_MODULE_TG1_WDT = 5, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + /* GDMA by channel */ + SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + /* MISC Peripherals */ + SLEEP_RETENTION_MODULE_ADC = 11, + SLEEP_RETENTION_MODULE_I2C0 = 12, + SLEEP_RETENTION_MODULE_I2C1 = 13, + SLEEP_RETENTION_MODULE_RMT0 = 14, + SLEEP_RETENTION_MODULE_UART0 = 15, + SLEEP_RETENTION_MODULE_UART1 = 16, + SLEEP_RETENTION_MODULE_I2S0 = 17, + SLEEP_RETENTION_MODULE_ETM0 = 18, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 19, + SLEEP_RETENTION_MODULE_TWAI0 = 20, + SLEEP_RETENTION_MODULE_PARLIO0 = 21, + SLEEP_RETENTION_MODULE_GPSPI2 = 22, + SLEEP_RETENTION_MODULE_LEDC = 23, + SLEEP_RETENTION_MODULE_PCNT0 = 24, + SLEEP_RETENTION_MODULE_MCPWM0 = 25, + + /* Modem module, which includes BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_BLE_MAC = 28, + SLEEP_RETENTION_MODULE_BT_BB = 29, + SLEEP_RETENTION_MODULE_802154_MAC = 30, + + SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 +} periph_retention_module_t; + +#define is_top_domain_module(m) \ + ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_PCNT0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ + : false) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 1a6c4bb68a..a85199d7c0 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -74,7 +74,7 @@ // #define SOC_RMT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11622 // #define SOC_AES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11504 // #define SOC_SDIO_SLAVE_SUPPORTED 1 -// #define SOC_PAU_SUPPORTED 1 +#define SOC_PAU_SUPPORTED 1 // #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11517, IDF-11520 // #define SOC_DEEP_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11515 // #define SOC_MODEM_CLOCK_SUPPORTED 1 @@ -529,6 +529,7 @@ #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_SUPPORT_TOP_PD (1) #define SOC_PM_PAU_LINK_NUM (5) +#define SOC_PM_RETENTION_MODULE_NUM (32) #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1) #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) diff --git a/components/soc/include/soc/ledc_periph.h b/components/soc/include/soc/ledc_periph.h index 8ed332010b..066dc5ca7c 100644 --- a/components/soc/include/soc/ledc_periph.h +++ b/components/soc/include/soc/ledc_periph.h @@ -31,7 +31,7 @@ extern const ledc_signal_conn_t ledc_periph_signal[2]; extern const ledc_signal_conn_t ledc_periph_signal[1]; #endif -#if SOC_PAU_SUPPORTED +#if SOC_PAU_SUPPORTED && SOC_LEDC_SUPPORT_SLEEP_RETENTION #if SOC_LIGHT_SLEEP_SUPPORTED #if SOC_PHY_SUPPORTED