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bootloader: enable super WDT and BOD reset on C2

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This commit is contained in:
Xiao Xufeng 2023-03-08 14:12:34 +08:00
parent 6ce4fd9eab
commit 8227ca97bd
3 changed files with 32 additions and 3 deletions
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10
components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
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@ -34,6 +34,7 @@
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
@ -240,10 +241,19 @@ static void bootloader_super_wdt_auto_feed(void)
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
}
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_ana_reset_config();
bootloader_super_wdt_auto_feed();
// protect memory region
bootloader_init_mem();

21
components/bootloader_support/src/esp32c2/bootloader_soc.c
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@ -3,19 +3,34 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/rtc_cntl_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
(void)enable;
}

4
components/soc/esp32c2/include/soc/rtc_cntl_reg.h
View File

@ -1678,6 +1678,10 @@ RO CPU.*/
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0xFC)
/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add desc.*/