esp32: move spiram, himem

components/esp32/CMakeLists.txt

@@ -11,12 +11,6 @@ if(BOOTLOADER_BUILD)
     target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32.peripherals.ld")
 else()
     # Regular app build
-    set(srcs
-        "cache_sram_mmu.c"
-        "esp_himem.c"
-        "spiram.c"
-        "spiram_psram.c")
-
     set(include_dirs "include")
 
     set(requires driver efuse soc xtensa) #unfortunately rom/uart uses SOC registers directly
@@ -40,7 +34,7 @@ else()
                         PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32.project.ld")
 
     target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32.peripherals.ld")
-    target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
+    target_link_libraries(${COMPONENT_LIB} INTERFACE gcc)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
 
     idf_build_get_property(config_dir CONFIG_DIR)
@@ -57,27 +51,4 @@ else()
     add_custom_target(esp32_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32_out.ld)
     add_dependencies(${COMPONENT_LIB} esp32_linker_script)
 
-    if(CONFIG_SPIRAM_CACHE_WORKAROUND)
-        # Note: Adding as a PUBLIC compile option here causes this option to propagate to all
-        # components that depend on esp32.
-        #
-        # To handle some corner cases, the same flag is set in project_include.cmake
-        target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
-        # also, make sure we link with this option so correct toolchain libs are pulled in
-        target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
-        # set strategy selected
-        # note that we don't need to set link options as the library linked is independent of this
-        if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST)
-            target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
-            target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
-        endif()
-        if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW)
-            target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
-            target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
-        endif()
-        if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS)
-            target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
-            target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
-        endif()
-    endif()
 endif()

components/esp32/Makefile.projbuild

@@ -1,25 +1,3 @@
-# Enable psram cache bug workaround in compiler if selected
-
-ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
-SPIRAM_CACHE_WORKAROUND_FLAGS = -mfix-esp32-psram-cache-issue
-
-ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
-SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=dupldst
-endif
-ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
-SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=memw
-endif
-ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
-SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=nops
-endif
-
-CFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
-CXXFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
-LDFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
-endif
-
-
-
 # Enable dynamic esp_timer overflow value if building unit tests
 ifneq ("$(filter esp32,$(TEST_COMPONENTS_LIST))","")
 CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL

components/esp32s2/CMakeLists.txt

@@ -11,9 +11,6 @@ if(BOOTLOADER_BUILD)
 else()
     # Regular app build
 
-    set(srcs "spiram.c"
-             "spiram_psram.c")
-
     set(include_dirs "include")
 
     set(requires driver efuse xtensa)
@@ -39,7 +36,7 @@ else()
                          PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32s2.project.ld")
 
     target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s2.peripherals.ld")
-    target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
+    target_link_libraries(${COMPONENT_LIB} INTERFACE gcc)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
 
     idf_build_get_property(config_dir CONFIG_DIR)

components/esp32s2/include/esp_spiram.h

@@ -1,85 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_SPIRAM_H
-#define __ESP_SPIRAM_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
- *
- * @return ESP_OK on success
- */
-esp_err_t esp_spiram_init(void);
-
-/**
- * @brief Configure Cache/MMU for access to external SPI RAM.
- *
- * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
- * option is enabled. Applications which need to enable SPI RAM at run time
- * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
- *
- * @attention this function must be called with flash cache disabled.
- */
-void esp_spiram_init_cache(void);
-
-
-/**
- * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
- * (in case of a dual-core system) the app CPU is online. This test overwrites the
- * memory with crap, so do not call after e.g. the heap allocator has stored important
- * stuff in SPI RAM.
- *
- * @return true on success, false on failed memory test
- */
-bool esp_spiram_test(void);
-
-
-/**
- * @brief Add the initialized SPI RAM to the heap allocator.
- */
-esp_err_t esp_spiram_add_to_heapalloc(void);
-
-
-/**
- * @brief Get the size of the attached SPI RAM chip selected in menuconfig
- *
- * @return Size in bytes, or 0 if no external RAM chip support compiled in.
- */
-size_t esp_spiram_get_size(void);
-
-
-/**
- * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
- * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
- * RAM cache.
- *
- * This is meant for use from within the SPI flash code.
- */
-void esp_spiram_writeback_cache(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

components/esp32s2/test/test_spiram_cache_flush.c

@@ -1,182 +0,0 @@
-/*
-This code tests the interaction between PSRAM and SPI flash routines.
-*/
-
-#include <esp_types.h>
-#include <stdio.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "freertos/queue.h"
-#include "freertos/xtensa_api.h"
-#include "unity.h"
-#include "soc/dport_reg.h"
-#include "soc/io_mux_reg.h"
-#include <stdint.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include "esp_heap_caps.h"
-#include "esp_spi_flash.h"
-#include "esp_partition.h"
-#include "test_utils.h"
-
-#if CONFIG_SPIRAM
-
-#if CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC
-#define USE_CAPS_ALLOC 1
-#endif // CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC
-
-#define TSTSZ (16*1024)
-
-#if !CONFIG_FREERTOS_UNICORE
-
-volatile static int res[2], err[2];
-
-void tstMem(void *arg) {
-    volatile unsigned char *mem=(volatile unsigned char*)arg;
-    int p=0;
-    while(1) {
-        for (int i=0; i<TSTSZ; i++) {
-            mem[i]=(i^p);
-        }
-        for (int i=0; i<TSTSZ; i++) {
-            if (mem[i]!=((i^p)&0xff)) {
-                printf("Core %d mem err! Got %x espected %x at addr %p\n", xPortGetCoreID(), mem[i], (i^p)&0xff, &mem[i]);
-                err[xPortGetCoreID()]++;
-            }
-        }
-        p++;
-        res[xPortGetCoreID()]++;
-    }
-}
-
-
-TEST_CASE("Spiram cache flush on mmap", "[spiram]")
-{
-    void *mem[2];
-    res[0]=0; res[1]=0;
-#if USE_CAPS_ALLOC
-    printf("Allocating SPI RAM chunk...\n");
-    mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
-    mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
-#else
-    mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
-    mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
-#endif
-    assert(mem[0]);
-    assert(mem[1]);
-    TaskHandle_t th[2];
-    err[0]=0; err[1]=0;
-    printf("Creating tasks\n");
-    xTaskCreatePinnedToCore(tstMem  , "tskone"  , 2048, mem[0], 3, &th[0], 0);
-    xTaskCreatePinnedToCore(tstMem  , "tsktwo"  , 2048, mem[1], 3, &th[1], 1);
-
-    for (int l=0; l<10; l++) {
-        for (int p=0; p<4096*1024; p+=65536) {
-            const void *out;
-            spi_flash_mmap_handle_t h;
-            spi_flash_mmap(p, 65536, SPI_FLASH_MMAP_DATA, &out, &h);
-            spi_flash_munmap(h);
-        }
-    }
-
-    printf("Checked memory %d and %d times. Errors: %d and %d\n", res[0], res[1], err[0], err[1]);
-
-    vTaskDelete(th[0]);
-    vTaskDelete(th[1]);
-#if USE_CAPS_ALLOC
-    free(mem[0]);
-    free(mem[1]);
-#endif
-    TEST_ASSERT(err[0]==0);
-    TEST_ASSERT(err[1]==0);
-}
-
-
-#define CYCLES 1024
-
-TEST_CASE("Spiram cache flush on write/read", "[spiram]")
-{
-    void *mem[2];
-    res[0]=0; res[1]=0;
-#if USE_CAPS_ALLOC
-    printf("Allocating SPI RAM chunk...\n");
-    mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
-    mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
-#else
-    mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
-    mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
-#endif
-    assert(mem[0]);
-    assert(mem[1]);
-    TaskHandle_t th[2];
-    const esp_partition_t* part = get_test_data_partition();
-    assert(part!=NULL);
-
-    printf("Erasing sector...\n");
-    esp_partition_erase_range(part, 0, 64*1024);
-    printf("Erased.\n");
-    printf("Creating tasks\n");
-    xTaskCreatePinnedToCore(tstMem  , "tskone"  , 2048, mem[0], 3, &th[0], 0);
-    xTaskCreatePinnedToCore(tstMem  , "tsktwo"  , 2048, mem[1], 3, &th[1], 1);
-    char buf[512];
-
-    const void *out;
-    spi_flash_mmap_handle_t handle;
-    esp_partition_mmap(part, 0, 512, SPI_FLASH_MMAP_DATA, &out, &handle);
-    for (int i=0; i<CYCLES; i++) {
-        esp_partition_write(part, 0, buf, 512);
-        esp_partition_read(part, 0, buf, 512);
-        vTaskDelay(1);
-    }
-    spi_flash_munmap(handle);
-
-    printf("Checked memory %d and %d times.\n", res[0], res[1]);
-
-    vTaskDelete(th[0]);
-    vTaskDelete(th[1]);
-#if USE_CAPS_ALLOC
-    free(mem[0]);
-    free(mem[1]);
-#endif
-}
-#endif // !CONFIG_FREERTOS_UNICORE
-
-IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
-    char *mem1=malloc(0x10000);
-#if USE_CAPS_ALLOC
-    char *mem2=heap_caps_malloc(0x10000, MALLOC_CAP_SPIRAM);
-#else
-    char *mem2=(void*)SOC_EXTRAM_DATA_LOW;
-#endif
-
-#if !CONFIG_SPIRAM_SPEED_80M
-    printf("**** WARNING **** Spi memory isn't running at 80MHz, so this test is somewhat meaningless.\n");
-#endif
-
-    printf("RAM: Got %p and %p\n", mem1, mem2);
-    assert(mem1);
-    assert(mem2);
-    for (int i=0; i<0x10000; i++) mem1[i]=i^0xAAAAAAAA;
-
-    for (int cycle=1; cycle<100; cycle++) {
-        memcpy(mem2, mem1, 0x10000);
-        if (memcmp(mem1, mem2, 0x10000)!=0) {
-            printf("Memcmp failed! Cycle %d\n", cycle);
-            for (int i=0; i<0x10000; i++) {
-                if (mem1[i]!=mem2[i]) {
-                    printf("Found real difference at index %d: 0x%x vs 0x%x\n", i, mem1[i], mem2[i]);
-                    break;
-                }
-            }
-        }
-    }
-
-    free(mem1);
-#if USE_CAPS_ALLOC
-    free(mem2);
-#endif
-}
-
-#endif // CONFIG_SPIRAM

components/esp32s3/CMakeLists.txt

@@ -11,11 +11,6 @@ if(BOOTLOADER_BUILD)
     target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s3.peripherals.ld")
 else()
     # Regular app build
-
-    set(srcs "dport_access.c"
-             "spiram.c"
-             "spiram_psram.c"
-             "spi_timing_config.c")
     set(include_dirs "include")
 
     set(requires driver efuse soc xtensa) #unfortunately rom/uart uses SOC registers directly
@@ -26,12 +21,6 @@ else()
     set(priv_requires app_trace app_update bootloader_support log mbedtls nvs_flash pthread
         spi_flash vfs espcoredump esp_common perfmon esp_timer esp_ipc)
 
-    if(CONFIG_SPIRAM_MODE_QUAD)
-        list(APPEND srcs "spiram_psram.c")
-    elseif(CONFIG_SPIRAM_MODE_OCT)
-        list(APPEND srcs "opiram_psram.c")
-    endif()
-
     idf_component_register(SRCS "${srcs}"
                         INCLUDE_DIRS "${include_dirs}"
                         REQUIRES "${requires}"
@@ -46,7 +35,7 @@ else()
                                           PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32s3.project.ld")
 
     target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32s3.peripherals.ld")
-    target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
+    target_link_libraries(${COMPONENT_LIB} INTERFACE gcc)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
 
     idf_build_get_property(config_dir CONFIG_DIR)

components/esp32s3/include/esp_spiram.h

@@ -1,90 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_SPIRAM_H
-#define __ESP_SPIRAM_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include "esp_err.h"
-
-/**
- * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
- *
- * @return ESP_OK on success
- */
-esp_err_t esp_spiram_init(void);
-
-/**
- * @brief Configure Cache/MMU for access to external SPI RAM.
- *
- * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
- * option is enabled. Applications which need to enable SPI RAM at run time
- * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
- *
- * @attention this function must be called with flash cache disabled.
- */
-void esp_spiram_init_cache(void);
-
-
-/**
- * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
- * (in case of a dual-core system) the app CPU is online. This test overwrites the
- * memory with crap, so do not call after e.g. the heap allocator has stored important
- * stuff in SPI RAM.
- *
- * @return true on success, false on failed memory test
- */
-bool esp_spiram_test(void);
-
-
-/**
- * @brief Add the initialized SPI RAM to the heap allocator.
- */
-esp_err_t esp_spiram_add_to_heapalloc(void);
-
-
-/**
- * @brief Get the size of the attached SPI RAM chip selected in menuconfig
- *
- * @return Size in bytes, or 0 if no external RAM chip support compiled in.
- */
-size_t esp_spiram_get_size(void);
-
-
-/**
- * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
- * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
- * RAM cache.
- *
- * This is meant for use from within the SPI flash code.
- */
-void esp_spiram_writeback_cache(void);
-
-
-
-/**
- * @brief Reserve a pool of internal memory for specific DMA/internal allocations
- *
- * @param size Size of reserved pool in bytes
- *
- * @return
- *          - ESP_OK on success
- *          - ESP_ERR_NO_MEM when no memory available for pool
- */
-esp_err_t esp_spiram_reserve_dma_pool(size_t size);
-
-
-#endif

components/esp_hw_support/CMakeLists.txt

@@ -6,7 +6,7 @@ if(${target} STREQUAL "esp32")
      list(APPEND requires efuse)
 endif()
 
-set(priv_requires efuse)
+set(priv_requires efuse bootloader_support spi_flash)
 
 set(srcs "compare_set.c" "cpu_util.c")
 if(NOT BOOTLOADER_BUILD)
@@ -33,3 +33,27 @@ idf_component_register(SRCS ${srcs}
 
 idf_build_get_property(target IDF_TARGET)
 add_subdirectory(port/${target})
+
+if(CONFIG_SPIRAM_CACHE_WORKAROUND AND NOT BOOTLOADER_BUILD)
+    # Note: Adding as a PUBLIC compile option here causes this option to propagate to all
+    # components that depend on esp32.
+    #
+    # To handle some corner cases, the same flag is set in project_include.cmake
+    target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
+    # also, make sure we link with this option so correct toolchain libs are pulled in
+    target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-issue)
+    # set strategy selected
+    # note that we don't need to set link options as the library linked is independent of this
+    if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST)
+        target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
+        target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=dupldst)
+    endif()
+    if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW)
+        target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
+        target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=memw)
+    endif()
+    if(CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS)
+        target_compile_options(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
+        target_link_libraries(${COMPONENT_LIB} PUBLIC -mfix-esp32-psram-cache-strategy=nops)
+    endif()
+endif()

components/esp_hw_support/Makefile.projbuild

@@ -0,0 +1,19 @@
+# Enable psram cache bug workaround in compiler if selected
+
+ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
+SPIRAM_CACHE_WORKAROUND_FLAGS = -mfix-esp32-psram-cache-issue
+
+ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
+SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=dupldst
+endif
+ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
+SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=memw
+endif
+ifdef CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
+SPIRAM_CACHE_WORKAROUND_FLAGS += -mfix-esp32-psram-cache-strategy=nops
+endif
+
+CFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
+CXXFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
+LDFLAGS+=$(SPIRAM_CACHE_WORKAROUND_FLAGS)
+endif

components/esp_hw_support/component.mk

@@ -3,7 +3,17 @@ COMPONENT_ADD_INCLUDEDIRS := . include port/$(IDF_TARGET)/ include/soc port/$(ID
 COMPONENT_ADD_LDFRAGMENTS := linker.lf
 
 ifdef IS_BOOTLOADER_BUILD
-COMPONENT_OBJEXCLUDE += clk_ctrl_os.o mac_addr.o esp_async_memcpy.o intr_alloc.o sleep_modes.o regi2c_ctrl.o port/$(IDF_TARGET)/dport_access.o
+COMPONENT_OBJEXCLUDE += clk_ctrl_os.o \
+						intr_alloc.o \
+						sleep_modes.o \
+						esp_async_memcpy.o \
+						mac_addr.o \
+						regi2c_ctrl.o \
+						port/$(IDF_TARGET)/dport_access.o \
+						port/$(IDF_TARGET)/cache_sram_mmu.o \
+						port/$(IDF_TARGET)/esp_himem.o \
+						port/$(IDF_TARGET)/spiram.o \
+						port/$(IDF_TARGET)/spiram_psram.o
 endif
 
 COMPONENT_OBJEXCLUDE += esp_async_memcpy.o

components/esp_hw_support/include/soc/esp32/spiram.h

@@ -108,9 +108,8 @@ esp_err_t esp_spiram_reserve_dma_pool(size_t size);
  */
 bool esp_spiram_is_initialized(void);
 
-
-#endif
-
 #ifdef __cplusplus
 }
 #endif
+
+#endif //  __ESP_SPIRAM_H

components/esp_hw_support/port/esp32/CMakeLists.txt

@@ -12,7 +12,11 @@ set(srcs
     "chip_info.c")
 
 if(NOT BOOTLOADER_BUILD)
-    list(APPEND srcs "dport_access.c")
+    list(APPEND srcs "cache_sram_mmu.c"
+                     "dport_access.c"
+                     "esp_himem.c"
+                     "spiram.c"
+                     "spiram_psram.c")
 endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

components/esp_hw_support/port/esp32/spiram_psram.h

@@ -11,6 +11,10 @@
 #include "esp_err.h"
 #include "sdkconfig.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 typedef enum {
     PSRAM_CACHE_F80M_S40M = 0,
     PSRAM_CACHE_F40M_S40M,
@@ -59,4 +63,8 @@ psram_size_t psram_get_size(void);
  */
 esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif

components/esp_hw_support/port/esp32s2/CMakeLists.txt

@@ -19,7 +19,9 @@ if(NOT BOOTLOADER_BUILD)
                      "esp_hmac.c"
                      "esp_crypto_lock.c"
                      "esp_ds.c"
-                     "dport_access.c")
+                     "dport_access.c"
+                     "spiram.c"
+                     "spiram_psram.c")
 endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

components/esp_hw_support/port/esp32s3/CMakeLists.txt

@@ -16,7 +16,15 @@ if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "../async_memcpy_impl_gdma.c"
                      "dport_access.c"
                      "esp_crypto_lock.c"
-                     "memprot.c")
+                     "memprot.c"
+                     "spiram.c")
+
+    if(CONFIG_SPIRAM_MODE_QUAD)
+        list(APPEND srcs "spiram_psram.c")
+    elseif(CONFIG_SPIRAM_MODE_OCT)
+        list(APPEND srcs "opiram_psram.c")
+    endif()
+
 endif()
 
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

components/esp_hw_support/test/test_4mpsram.c

@@ -9,6 +9,8 @@
 #include "driver/spi_common_internal.h"
 #include "sdkconfig.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+
 static const char TAG[] = "test_psram";
 
 #ifdef CONFIG_SPIRAM
@@ -98,3 +100,5 @@ they will not pass this test at 80MHz.
     test_spi_bus_occupy(-1);
 }
 #endif
+
+#endif // CONFIG_IDF_TARGET_ESP32

components/esp_hw_support/test/test_himem.c

@@ -14,6 +14,8 @@
 #include "sdkconfig.h"
 #include "esp32/himem.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+
 #if CONFIG_SPIRAM_BANKSWITCH_ENABLE
 
 //Fill memory with pseudo-random data generated from the given seed.
@@ -107,3 +109,5 @@ TEST_CASE("high psram memory test", "[himem]")
 
 
 #endif
+
+#endif // CONFIG_IDF_TARGET_ESP32

components/esp_hw_support/test/test_spiram_cache_flush.c

@@ -13,7 +13,6 @@ This code tests the interaction between PSRAM and SPI flash routines.
 #include "freertos/task.h"
 #include "freertos/semphr.h"
 #include "freertos/queue.h"
-#include "freertos/xtensa_api.h"
 #include "unity.h"
 #include <stdint.h>
 #include <stdlib.h>

components/spi_flash/CMakeLists.txt

@@ -82,7 +82,9 @@ else()
         endif()
 
         if(CONFIG_IDF_TARGET_ESP32S3)
-            list(APPEND srcs "spi_flash_timing_tuning.c")
+            list(APPEND srcs
+                "esp32s3/spi_timing_config.c"
+                "spi_flash_timing_tuning.c")
         endif()
 
         # New implementation after IDF v4.0

components/spi_flash/esp32s3/spi_timing_config.c

@@ -11,7 +11,7 @@
 #include "esp_types.h"
 #include "esp_log.h"
 #include "soc/spi_mem_reg.h"
-#include "esp32s3/spi_timing_config.h"
+#include "spi_timing_config.h"
 
 #define OPI_PSRAM_SYNC_READ                 0x0000
 #define OPI_PSRAM_SYNC_WRITE                0x8080

components/spi_flash/esp32s3/spi_timing_config.h

@@ -9,7 +9,7 @@
 #include "esp_flash_partitions.h"
 #include "esp32s3/rom/spi_flash.h"
 #include "esp32s3/rom/opi_flash.h"
-#include "esp32s3/mspi_timing_tuning_configs.h"
+#include "mspi_timing_tuning_configs.h"
 
 #ifdef __cplusplus
 extern "C" {

docs/doxygen/Doxyfile_esp32

@@ -8,5 +8,5 @@ INPUT += \
          $(IDF_PATH)/components/soc/$(IDF_TARGET)/include/soc/rtc_io_channel.h \
          $(IDF_PATH)/components/soc/$(IDF_TARGET)/include/soc/touch_sensor_channel.h \
          $(IDF_PATH)/components/driver/$(IDF_TARGET)/include/driver/touch_sensor.h \
-         $(IDF_PATH)/components/esp32/include/esp32/himem.h \
+         $(IDF_PATH)/components/esp_hw_support/include/soc/esp32/himem.h \
          $(IDF_PATH)/components/ulp/include/$(IDF_TARGET)/ulp.h