diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index ec334281ba..3076547b73 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 3f91b5a37afbcdf1379820626a92e69c +// md5_digest_table ef33779021404fbaddc878eefebaddc1 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -155,10 +155,6 @@ static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, }; -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { {EFUSE_BLK0, 40, 1}, // Disable Icache, }; @@ -691,11 +687,6 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { &DIS_ICACHE[0], // Disable Icache NULL diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index 73c91d4328..a9939e912b 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -50,7 +50,6 @@ RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index 3ebc34ac27..839116af26 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -9,7 +9,7 @@ extern "C" { #endif -// md5_digest_table 3f91b5a37afbcdf1379820626a92e69c +// md5_digest_table ef33779021404fbaddc878eefebaddc1 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -51,7 +51,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; diff --git a/components/efuse/esp32h2/esp_efuse_table.c b/components/efuse/esp32h2/esp_efuse_table.c index c67739f81a..540e2e050a 100644 --- a/components/efuse/esp32h2/esp_efuse_table.c +++ b/components/efuse/esp32h2/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table e460a50d9f80fa56cb87cd54ff055feb +// md5_digest_table a007943ae37fe41884a23d505a6e7dbb // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -155,10 +155,6 @@ static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, }; -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { {EFUSE_BLK0, 40, 1}, // Disable Icache, }; @@ -676,11 +672,6 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { &DIS_ICACHE[0], // Disable Icache NULL diff --git a/components/efuse/esp32h2/esp_efuse_table.csv b/components/efuse/esp32h2/esp_efuse_table.csv index 9ac3667c5d..08467f0ec0 100644 --- a/components/efuse/esp32h2/esp_efuse_table.csv +++ b/components/efuse/esp32h2/esp_efuse_table.csv @@ -51,7 +51,6 @@ RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode diff --git a/components/efuse/esp32h2/include/esp_efuse_table.h b/components/efuse/esp32h2/include/esp_efuse_table.h index cde5e284eb..a35a2ea1de 100644 --- a/components/efuse/esp32h2/include/esp_efuse_table.h +++ b/components/efuse/esp32h2/include/esp_efuse_table.h @@ -9,7 +9,7 @@ extern "C" { #endif -// md5_digest_table e460a50d9f80fa56cb87cd54ff055feb +// md5_digest_table a007943ae37fe41884a23d505a6e7dbb // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -51,7 +51,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index d50ead1310..5d8a53eda6 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 0f3dc076304dac1cb56cea03c223d26d +// md5_digest_table ee5142bc489eee22230a49b5c7cafe00 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -23,10 +23,6 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, }; -static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT, -}; - static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, }; @@ -163,10 +159,6 @@ static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, }; -static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { - {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { {EFUSE_BLK0, 40, 1}, // Disable Icache, }; @@ -554,11 +546,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = { - &WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT NULL @@ -729,11 +716,6 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { - &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { &DIS_ICACHE[0], // Disable Icache NULL diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index af29f4fd49..40decc2f29 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -14,7 +14,6 @@ # EFUSE_RD_WR_DIS_REG # WR_DIS, EFUSE_BLK0, 0, 32, Write protection WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT @@ -51,7 +50,6 @@ RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 1ca6a78a9b..1f9ed383d7 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -9,7 +9,7 @@ extern "C" { #endif -// md5_digest_table 0f3dc076304dac1cb56cea03c223d26d +// md5_digest_table ee5142bc489eee22230a49b5c7cafe00 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -18,7 +18,6 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; @@ -53,7 +52,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h index e901d8714d..aca7304f53 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/include/soc/efuse_reg.h @@ -141,12 +141,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: Set this bit to disable reading from BlOCK4-10.*/ #define EFUSE_RD_DIS 0x0000007F @@ -516,12 +516,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: The value of RD_DIS.*/ #define EFUSE_RD_DIS 0x0000007F @@ -1486,12 +1486,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED5_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ #define EFUSE_RD_DIS_ERR 0x0000007F diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index 8d1514242d..24915ba810 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -22,7 +22,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/ + uint32_t rpt4_reserved5: 1; /*Reserved*/ uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ @@ -106,7 +106,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/ + uint32_t rpt4_reserved5: 1; /*Reserved*/ uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ @@ -274,7 +274,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved5_err: 1; /*Reserved.*/ uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h index 0e4897fd6e..fc55f2938e 100644 --- a/components/soc/esp32h2/include/soc/efuse_reg.h +++ b/components/soc/esp32h2/include/soc/efuse_reg.h @@ -141,12 +141,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: Set this bit to disable reading from BlOCK4-10.*/ #define EFUSE_RD_DIS 0x0000007F @@ -516,12 +516,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved*/ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: The value of RD_DIS.*/ #define EFUSE_RD_DIS 0x0000007F @@ -1486,12 +1486,12 @@ extern "C" { #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved*/ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED5_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ #define EFUSE_RD_DIS_ERR 0x0000007F diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h index 8d1514242d..4c5af9d8c7 100644 --- a/components/soc/esp32h2/include/soc/efuse_struct.h +++ b/components/soc/esp32h2/include/soc/efuse_struct.h @@ -106,7 +106,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/ + uint32_t rpt4_reserved5: 1; /*Reserved*/ uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ @@ -274,7 +274,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ + uint32_t rpt4_reserved5_err: 1; /*If RPT4_RESERVED5 is 1 then it indicates a programming error.*/ uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index 67cd4843cd..65ec6a3eaf 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -230,12 +230,12 @@ AG can be enabled in HMAC module..*/ #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM..*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 +/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved */ +#define EFUSE_RPT4_RESERVED5 (BIT(7)) +#define EFUSE_RPT4_RESERVED5_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_V 0x1 +#define EFUSE_RPT4_RESERVED5_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: Set this bit to disable reading from BlOCK4-10..*/ #define EFUSE_RD_DIS 0x0000007F @@ -1283,12 +1283,12 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/ #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If any bits in this filed are 1, then it indicates a programming error..*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Reserved*/ +#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) +#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED5_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ /*description: If any bits in this filed are 1, then it indicates a programming error..*/ #define EFUSE_RD_DIS_ERR 0x0000007F diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index a982e7ff20..bd45983ba2 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -36,7 +36,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t reg_dis_rtc_ram_boot : 1; /*Set this bit to disable boot from RTC RAM.*/ + uint32_t reg_rpt4_reserved5 : 1; /*Reserved*/ uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ @@ -218,7 +218,7 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_rtc_ram_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_rpt4_reserved5_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst index a058ac8254..7f87e9954a 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-C3.rst @@ -8,7 +8,6 @@ EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) ---------------------------------------------------------------------------------------- Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) DIS_FORCE_DOWNLOAD (BLOCK0) Disables forcing chip into Download mode = False R/W (0b0) diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst index c2592a7b0c..8248dd1ffc 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S3.rst @@ -27,7 +27,6 @@ ADC2_MODE3_D1 (BLOCK2) ADC2 calibration 16 = -4 R/W (0b100001) Config fuses: - DIS_RTC_RAM_BOOT (BLOCK0) Disables boot from RTC RAM = False R/W (0b0) DIS_ICACHE (BLOCK0) Disables ICache = False R/W (0b0) DIS_DCACHE (BLOCK0) Disables DCache = False R/W (0b0) DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0)