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Merge branch 'master' into feature/esp32s2beta_merge

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This commit is contained in:
Angus Gratton 2019-10-22 13:51:49 +11:00 committed by Angus Gratton
commit 8675a818f9
143 changed files with 4319 additions and 1090 deletions
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6
CMakeLists.txt
View File

@ -27,6 +27,12 @@ else()
list(APPEND cxx_compile_options "-fno-exceptions")
endif()
if(CONFIG_COMPILER_CXX_RTTI)
list(APPEND cxx_compile_options "-frtti")
else()
list(APPEND cxx_compile_options "-fno-rtti")
endif()
if(CONFIG_COMPILER_DISABLE_GCC8_WARNINGS)
list(APPEND compile_options "-Wno-parentheses"
"-Wno-sizeof-pointer-memaccess"

9
Kconfig
View File

@ -251,6 +251,15 @@ mainmenu "Espressif IoT Development Framework Configuration"
Size (in bytes) of the emergency memory pool for C++ exceptions. This pool will be used to allocate
memory for thrown exceptions when there is not enough memory on the heap.
config COMPILER_CXX_RTTI
# Invisible option, until the toolchain with RTTI support is released.
# Use prompt "Enable C++ run-time type info (RTTI)" when updating.
bool
help
Enabling this option compiles all C++ files with RTTI support enabled.
This increases binary size (typically by tens of kB) but allows using
dynamic_cast conversion and typeid operator.
choice COMPILER_STACK_CHECK_MODE
prompt "Stack smashing protection mode"
default COMPILER_STACK_CHECK_MODE_NONE

11
components/bt/CMakeLists.txt
View File

@ -289,6 +289,11 @@ if(CONFIG_BT_ENABLED)
"host/bluedroid/stack/smp/smp_l2c.c"
"host/bluedroid/stack/smp/smp_main.c"
"host/bluedroid/stack/smp/smp_utils.c")
if(CONFIG_BLE_MESH)
list(APPEND srcs "esp_ble_mesh/mesh_core/bluedroid_host/mesh_bearer_adapt.c")
endif()
endif()
if(CONFIG_BLE_MESH)
@ -335,9 +340,7 @@ if(CONFIG_BT_ENABLED)
"esp_ble_mesh/mesh_core/lpn.c"
"esp_ble_mesh/mesh_core/mesh_aes_encrypt.c"
"esp_ble_mesh/mesh_core/mesh_atomic.c"
"esp_ble_mesh/mesh_core/mesh_bearer_adapt.c"
"esp_ble_mesh/mesh_core/mesh_buf.c"
"esp_ble_mesh/mesh_core/mesh_hci.c"
"esp_ble_mesh/mesh_core/mesh_kernel.c"
"esp_ble_mesh/mesh_core/mesh_main.c"
"esp_ble_mesh/mesh_core/mesh_util.c"
@ -469,6 +472,10 @@ if(CONFIG_BT_ENABLED)
"host/nimble/nimble/porting/nimble/src/os_cputime.c"
"host/nimble/esp-hci/src/esp_nimble_hci.c")
if (CONFIG_BLE_MESH)
list(APPEND srcs "esp_ble_mesh/mesh_core/nimble_host/mesh_bearer_adapt.c")
endif()
if(CONFIG_BT_NIMBLE_MESH)
list(APPEND include_dirs

1
components/bt/Kconfig
View File

@ -411,7 +411,6 @@ endmenu
menuconfig BLE_MESH
bool "ESP BLE Mesh Support"
depends on BT_BLUEDROID_ENABLED
help
This option enables ESP BLE Mesh support. The specific features that are
available may depend on other features that have been enabled in the

4
components/bt/common/btc/core/btc_task.c
View File

@ -19,6 +19,7 @@
#include "esp_log.h"
#include "bt_common.h"
#include "osi/allocator.h"
#include "btc/btc_alarm.h"
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "common/bt_target.h"
@ -32,7 +33,6 @@
#include "btc_blufi_prf.h"
#include "blufi_int.h"
#include "btc/btc_dm.h"
#include "btc/btc_alarm.h"
#include "bta/bta_gatt_api.h"
#if CLASSIC_BT_INCLUDED
#include "btc/btc_profile_queue.h"
@ -94,7 +94,9 @@ static const btc_func_t profile_tab[BTC_PID_NUM] = {
[BTC_PID_BLUFI] = {btc_blufi_call_handler, btc_blufi_cb_handler },
#endif ///GATTS_INCLUDED == TRUE
[BTC_PID_DM_SEC] = {NULL, btc_dm_sec_cb_handler },
#endif
[BTC_PID_ALARM] = {btc_alarm_handler, NULL },
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#if CLASSIC_BT_INCLUDED
#if (BTC_GAP_BT_INCLUDED == TRUE)
[BTC_PID_GAP_BT] = {btc_gap_bt_call_handler, btc_gap_bt_cb_handler },

2
components/bt/common/btc/include/btc/btc_manage.h
View File

@ -15,9 +15,7 @@
#ifndef __BTC_MANAGE_H__
#define __BTC_MANAGE_H__
#include "bta/bta_api.h"
#include "btc/btc_task.h"
#include "esp_bt_defs.h"
#if BTC_DYNAMIC_MEMORY == FALSE
extern void *btc_profile_cb_tab[BTC_PID_NUM];

2
components/bt/common/include/bt_user_config.h
View File

@ -49,7 +49,7 @@
#ifdef CONFIG_BTC_TASK_STACK_SIZE
#define UC_BTC_TASK_STACK_SIZE CONFIG_BTC_TASK_STACK_SIZE
#else
#define UC_BTC_TASK_STACK_SIZE 3072
#define UC_BTC_TASK_STACK_SIZE 4096
#endif
/**********************************************************

48
components/bt/component.mk
View File

@ -129,26 +129,31 @@ COMPONENT_PRIV_INCLUDEDIRS += common/btc/include \
COMPONENT_SRCDIRS += common/osi \
common/btc/core
ifdef CONFIG_BLE_MESH
COMPONENT_SRCDIRS += esp_ble_mesh/mesh_core/bluedroid_host
endif
endif
ifdef CONFIG_BLE_MESH
COMPONENT_ADD_INCLUDEDIRS += esp_ble_mesh/mesh_core \
esp_ble_mesh/mesh_core/include \
esp_ble_mesh/mesh_core/settings \
esp_ble_mesh/btc/include \
esp_ble_mesh/mesh_models/common/include \
esp_ble_mesh/mesh_models/client/include \
esp_ble_mesh/api/core/include \
esp_ble_mesh/api/models/include \
esp_ble_mesh/api
COMPONENT_ADD_INCLUDEDIRS += esp_ble_mesh/mesh_core \
esp_ble_mesh/mesh_core/include \
esp_ble_mesh/mesh_core/settings \
esp_ble_mesh/btc/include \
esp_ble_mesh/mesh_models/common/include \
esp_ble_mesh/mesh_models/client/include \
esp_ble_mesh/api/core/include \
esp_ble_mesh/api/models/include \
esp_ble_mesh/api
COMPONENT_SRCDIRS += esp_ble_mesh/mesh_core \
esp_ble_mesh/mesh_core/settings \
esp_ble_mesh/btc \
esp_ble_mesh/mesh_models/common \
esp_ble_mesh/mesh_models/client \
esp_ble_mesh/api/core \
esp_ble_mesh/api/models
COMPONENT_SRCDIRS += esp_ble_mesh/mesh_core \
esp_ble_mesh/mesh_core/settings \
esp_ble_mesh/btc \
esp_ble_mesh/mesh_models/common \
esp_ble_mesh/mesh_models/client \
esp_ble_mesh/api/core \
esp_ble_mesh/api/models
endif
@ -196,6 +201,17 @@ endif
COMPONENT_OBJEXCLUDE += host/nimble/nimble/nimble/host/store/config/src/ble_store_config_conf.o
ifdef CONFIG_BLE_MESH
COMPONENT_PRIV_INCLUDEDIRS += common/btc/include \
common/include
COMPONENT_SRCDIRS += common/osi \
common/btc/core \
esp_ble_mesh/mesh_core/nimble_host
COMPONENT_ADD_INCLUDEDIRS += common/osi/include
endif
ifdef CONFIG_BT_NIMBLE_MESH
COMPONENT_ADD_INCLUDEDIRS += host/nimble/nimble/nimble/host/mesh/include

1
components/bt/esp_ble_mesh/Kconfig.in
View File

@ -8,6 +8,7 @@ if BLE_MESH
config BLE_MESH_USE_DUPLICATE_SCAN
bool "Support Duplicate Scan in BLE Mesh"
depends on BT_BLUEDROID_ENABLED
select BLE_SCAN_DUPLICATE
select BLE_MESH_SCAN_DUPLICATE_EN
default y

11
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_common_api.c
View File

@ -19,10 +19,9 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "osi/alarm.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_defs.h"
@ -32,12 +31,18 @@ esp_err_t esp_ble_mesh_init(esp_ble_mesh_prov_t *prov, esp_ble_mesh_comp_t *comp
btc_ble_mesh_prov_args_t arg = {0};
SemaphoreHandle_t semaphore = NULL;
btc_msg_t msg = {0};
esp_err_t ret;
if (prov == NULL || comp == NULL) {
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
ret = bt_mesh_host_init();
if (ret != ESP_OK) {
return ret;
}
// Create a semaphore
if ((semaphore = xSemaphoreCreateCounting(1, 0)) == NULL) {

2
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_local_data_operation_api.c
View File

@ -19,8 +19,6 @@
#include "btc/btc_manage.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_defs.h"

2
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_low_power_api.c
View File

@ -18,8 +18,6 @@
#include "btc/btc_manage.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_defs.h"

16
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_networking_api.c
View File

@ -19,8 +19,6 @@
#include "btc/btc_manage.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_networking_api.h"
@ -41,7 +39,7 @@ static esp_err_t ble_mesh_send_msg(esp_ble_mesh_model_t *model,
btc_msg_t msg = {0};
esp_err_t status;
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
if (device_role > ROLE_FAST_PROV) {
return ESP_ERR_INVALID_ARG;
@ -118,7 +116,7 @@ static esp_err_t ble_mesh_send_msg(esp_ble_mesh_model_t *model,
esp_err_t esp_ble_mesh_register_custom_model_callback(esp_ble_mesh_model_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_MODEL, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -198,7 +196,7 @@ esp_err_t esp_ble_mesh_node_local_reset(void)
{
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -218,7 +216,7 @@ esp_err_t esp_ble_mesh_provisioner_set_node_name(int index, const char *name)
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -251,7 +249,7 @@ esp_err_t esp_ble_mesh_provisioner_add_local_app_key(const uint8_t app_key[16],
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -283,7 +281,7 @@ esp_err_t esp_ble_mesh_provisioner_bind_app_key_to_local_model(uint16_t element_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -306,7 +304,7 @@ esp_err_t esp_ble_mesh_provisioner_add_local_net_key(const uint8_t net_key[16],
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;

42
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_provisioning_api.c
View File

@ -18,8 +18,6 @@
#include "btc/btc_manage.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_provisioning_api.h"
@ -29,7 +27,7 @@
esp_err_t esp_ble_mesh_register_prov_callback(esp_ble_mesh_prov_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_PROV, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -44,7 +42,7 @@ esp_err_t esp_ble_mesh_node_prov_enable(esp_ble_mesh_prov_bearer_t bearers)
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -60,7 +58,7 @@ esp_err_t esp_ble_mesh_node_prov_disable(esp_ble_mesh_prov_bearer_t bearers)
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -81,7 +79,7 @@ esp_err_t esp_ble_mesh_node_set_oob_pub_key(uint8_t pub_key_x[32], uint8_t pub_k
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -104,7 +102,7 @@ esp_err_t esp_ble_mesh_node_input_number(uint32_t number)
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -124,7 +122,7 @@ esp_err_t esp_ble_mesh_node_input_string(const char *string)
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -145,7 +143,7 @@ esp_err_t esp_ble_mesh_set_unprovisioned_device_name(const char *name)
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -168,7 +166,7 @@ esp_err_t esp_ble_mesh_provisioner_read_oob_pub_key(uint8_t link_idx, uint8_t pu
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -191,7 +189,7 @@ esp_err_t esp_ble_mesh_provisioner_input_string(const char *string, uint8_t link
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -214,7 +212,7 @@ esp_err_t esp_ble_mesh_provisioner_input_number(uint32_t number, uint8_t link_id
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -232,7 +230,7 @@ esp_err_t esp_ble_mesh_provisioner_prov_enable(esp_ble_mesh_prov_bearer_t bearer
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -249,7 +247,7 @@ esp_err_t esp_ble_mesh_provisioner_prov_disable(esp_ble_mesh_prov_bearer_t beare
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -271,7 +269,7 @@ esp_err_t esp_ble_mesh_provisioner_add_unprov_dev(esp_ble_mesh_unprov_dev_add_t
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -280,7 +278,7 @@ esp_err_t esp_ble_mesh_provisioner_add_unprov_dev(esp_ble_mesh_unprov_dev_add_t
arg.provisioner_dev_add.add_dev.addr_type = add_dev->addr_type;
arg.provisioner_dev_add.add_dev.oob_info = add_dev->oob_info;
arg.provisioner_dev_add.add_dev.bearer = add_dev->bearer;
memcpy(arg.provisioner_dev_add.add_dev.addr, add_dev->addr, sizeof(esp_bd_addr_t));
memcpy(arg.provisioner_dev_add.add_dev.addr, add_dev->addr, sizeof(esp_ble_mesh_bd_addr_t));
memcpy(arg.provisioner_dev_add.add_dev.uuid, add_dev->uuid, 16);
arg.provisioner_dev_add.flags = flags;
return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_mesh_prov_args_t), NULL)
@ -297,7 +295,7 @@ esp_err_t esp_ble_mesh_provisioner_delete_dev(esp_ble_mesh_device_delete_t *del_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -306,7 +304,7 @@ esp_err_t esp_ble_mesh_provisioner_delete_dev(esp_ble_mesh_device_delete_t *del_
arg.provisioner_dev_del.del_dev.flag = del_dev->flag;
if (del_dev->flag & DEL_DEV_ADDR_FLAG) {
arg.provisioner_dev_del.del_dev.addr_type = del_dev->addr_type;
memcpy(arg.provisioner_dev_del.del_dev.addr, del_dev->addr, sizeof(esp_bd_addr_t));
memcpy(arg.provisioner_dev_del.del_dev.addr, del_dev->addr, sizeof(esp_ble_mesh_bd_addr_t));
} else if (del_dev->flag & DEL_DEV_UUID_FLAG) {
memcpy(arg.provisioner_dev_del.del_dev.uuid, del_dev->uuid, 16);
}
@ -320,7 +318,7 @@ esp_err_t esp_ble_mesh_provisioner_set_dev_uuid_match(const uint8_t *match_val,
btc_ble_mesh_prov_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -346,7 +344,7 @@ esp_err_t esp_ble_mesh_provisioner_set_prov_data_info(esp_ble_mesh_prov_data_inf
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -379,7 +377,7 @@ esp_err_t esp_ble_mesh_set_fast_prov_info(esp_ble_mesh_fast_prov_info_t *fast_pr
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -408,7 +406,7 @@ esp_err_t esp_ble_mesh_set_fast_prov_action(esp_ble_mesh_fast_prov_action_t acti
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;

8
components/bt/esp_ble_mesh/api/core/esp_ble_mesh_proxy_api.c
View File

@ -18,8 +18,6 @@
#include "btc/btc_manage.h"
#include "esp_err.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_prov.h"
#include "esp_ble_mesh_defs.h"
@ -28,7 +26,7 @@ esp_err_t esp_ble_mesh_proxy_identity_enable(void)
{
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -41,7 +39,7 @@ esp_err_t esp_ble_mesh_proxy_gatt_enable(void)
{
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;
@ -54,7 +52,7 @@ esp_err_t esp_ble_mesh_proxy_gatt_disable(void)
{
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_PROV;

2
components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_provisioning_api.h
View File

@ -259,7 +259,7 @@ esp_err_t esp_ble_mesh_provisioner_delete_dev(esp_ble_mesh_device_delete_t *del_
* @param[in] bearer: Adv packet received from PB-GATT or PB-ADV bearer.
*
*/
typedef void (*esp_ble_mesh_prov_adv_cb_t)(const esp_bd_addr_t addr, const esp_ble_addr_type_t addr_type,
typedef void (*esp_ble_mesh_prov_adv_cb_t)(const esp_ble_mesh_bd_addr_t addr, const esp_ble_mesh_addr_type_t addr_type,
const uint8_t adv_type, const uint8_t *dev_uuid,
uint16_t oob_info, esp_ble_mesh_prov_bearer_t bearer);

47
components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h
View File

@ -17,8 +17,6 @@
#include <stdint.h>
#include "esp_bt_defs.h"
#include "mesh_proxy.h"
#include "mesh_access.h"
#include "mesh_main.h"
@ -31,6 +29,16 @@
#include "model_opcode.h"
#include "mesh_common.h"
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#define ESP_BLE_HOST_STATUS_ENABLED ESP_BLUEDROID_STATUS_ENABLED
#define ESP_BLE_HOST_STATUS_CHECK(status) ESP_BLUEDROID_STATUS_CHECK(status)
#else
#define ESP_BLE_HOST_STATUS_ENABLED 0
#define ESP_BLE_HOST_STATUS_CHECK(status) do {} while (0)
#endif
/*!< The maximum length of a BLE Mesh message, including Opcode, Payload and TransMIC */
#define ESP_BLE_MESH_SDU_MAX_LEN 384
@ -790,6 +798,30 @@ typedef enum {
.input_action = in_act, \
}
typedef uint8_t UINT8;
typedef uint16_t UINT16;
typedef uint32_t UINT32;
typedef uint64_t UINT64;
#define BT_OCTET32_LEN 32
typedef UINT8 BT_OCTET32[BT_OCTET32_LEN]; /* octet array: size 32 */
#ifndef BD_ADDR_LEN
#define BD_ADDR_LEN 6
typedef uint8_t BD_ADDR[BD_ADDR_LEN];
#endif
typedef uint8_t esp_ble_mesh_bd_addr_t[BD_ADDR_LEN];
/// BLE device address type
typedef enum {
ESP_BLE_MESH_ADDR_TYPE_PUBLIC = 0x00,
ESP_BLE_MESH_ADDR_TYPE_RANDOM = 0x01,
ESP_BLE_MESH_ADDR_TYPE_RPA_PUBLIC = 0x02,
ESP_BLE_MESH_ADDR_TYPE_RPA_RANDOM = 0x03,
} esp_ble_mesh_addr_type_t;
typedef struct esp_ble_mesh_model esp_ble_mesh_model_t;
/** Abstraction that describes a BLE Mesh Element.
@ -1110,8 +1142,8 @@ typedef uint8_t esp_ble_mesh_dev_add_flag_t;
/** Information of the device which is going to be added for provisioning. */
typedef struct {
esp_bd_addr_t addr; /*!< Device address */
esp_ble_addr_type_t addr_type; /*!< Device address type */
esp_ble_mesh_bd_addr_t addr; /*!< Device address */
esp_ble_mesh_addr_type_t addr_type; /*!< Device address type */
uint8_t uuid[16]; /*!< Device UUID */
uint16_t oob_info; /*!< Device OOB Info */
/*!< ADD_DEV_START_PROV_NOW_FLAG shall not be set if the bearer has both PB-ADV and PB-GATT enabled */
@ -1124,8 +1156,8 @@ typedef struct {
typedef struct {
union {
struct {
esp_bd_addr_t addr; /*!< Device address */
esp_ble_addr_type_t addr_type; /*!< Device address type */
esp_ble_mesh_bd_addr_t addr; /*!< Device address */
esp_ble_mesh_addr_type_t addr_type; /*!< Device address type */
};
uint8_t uuid[16]; /*!< Device UUID */
};
@ -1287,6 +1319,7 @@ typedef union {
*/
struct ble_mesh_provision_complete_evt_param {
uint16_t net_idx; /*!< NetKey Index */
uint8_t net_key[16]; /*!< NetKey */
uint16_t addr; /*!< Primary address */
uint8_t flags; /*!< Flags */
uint32_t iv_index; /*!< IV Index */
@ -1339,7 +1372,7 @@ typedef union {
struct ble_mesh_provisioner_recv_unprov_adv_pkt_param {
uint8_t dev_uuid[16]; /*!< Device UUID of the unprovisoned device */
uint8_t addr[6]; /*!< Device address of the unprovisoned device */
esp_ble_addr_type_t addr_type; /*!< Device address type */
esp_ble_mesh_addr_type_t addr_type; /*!< Device address type */
uint16_t oob_info; /*!< OOB Info of the unprovisoned device */
uint8_t adv_type; /*!< Avertising type of the unprovisoned device */
esp_ble_mesh_prov_bearer_t bearer; /*!< Bearer of the unprovisoned device */

11
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_config_model_api.c
View File

@ -17,22 +17,19 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_config_model.h"
#include "esp_ble_mesh_config_model_api.h"
esp_err_t esp_ble_mesh_register_config_client_callback(esp_ble_mesh_cfg_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_CONFIG_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
esp_err_t esp_ble_mesh_register_config_server_callback(esp_ble_mesh_cfg_server_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_CONFIG_SERVER, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -47,7 +44,7 @@ esp_err_t esp_ble_mesh_config_client_get_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_CONFIG_CLIENT;
@ -69,7 +66,7 @@ esp_err_t esp_ble_mesh_config_client_set_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_CONFIG_CLIENT;

9
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_generic_model_api.c
View File

@ -17,15 +17,12 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_generic_model.h"
#include "esp_ble_mesh_generic_model_api.h"
esp_err_t esp_ble_mesh_register_generic_client_callback(esp_ble_mesh_generic_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_GENERIC_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -40,7 +37,7 @@ esp_err_t esp_ble_mesh_generic_client_get_state(esp_ble_mesh_client_common_param
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_GENERIC_CLIENT;
@ -62,7 +59,7 @@ esp_err_t esp_ble_mesh_generic_client_set_state(esp_ble_mesh_client_common_param
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_GENERIC_CLIENT;

13
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_health_model_api.c
View File

@ -17,22 +17,19 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_health_model.h"
#include "esp_ble_mesh_health_model_api.h"
esp_err_t esp_ble_mesh_register_health_client_callback(esp_ble_mesh_health_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_HEALTH_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
esp_err_t esp_ble_mesh_register_health_server_callback(esp_ble_mesh_health_server_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_HEALTH_SERVER, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -47,7 +44,7 @@ esp_err_t esp_ble_mesh_health_client_get_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_HEALTH_CLIENT;
@ -69,7 +66,7 @@ esp_err_t esp_ble_mesh_health_client_set_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_HEALTH_CLIENT;
@ -86,7 +83,7 @@ esp_err_t esp_ble_mesh_health_server_fault_update(esp_ble_mesh_elem_t *element)
btc_ble_mesh_health_server_args_t arg = {0};
btc_msg_t msg = {0};
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_HEALTH_SERVER;

9
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_lighting_model_api.c
View File

@ -17,15 +17,12 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_lighting_model.h"
#include "esp_ble_mesh_lighting_model_api.h"
esp_err_t esp_ble_mesh_register_light_client_callback(esp_ble_mesh_light_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_LIGHTING_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -40,7 +37,7 @@ esp_err_t esp_ble_mesh_light_client_get_state(esp_ble_mesh_client_common_param_t
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_LIGHTING_CLIENT;
@ -62,7 +59,7 @@ esp_err_t esp_ble_mesh_light_client_set_state(esp_ble_mesh_client_common_param_t
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_LIGHTING_CLIENT;

9
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_sensor_model_api.c
View File

@ -17,15 +17,12 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_sensor_model.h"
#include "esp_ble_mesh_sensor_model_api.h"
esp_err_t esp_ble_mesh_register_sensor_client_callback(esp_ble_mesh_sensor_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_SENSOR_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -40,7 +37,7 @@ esp_err_t esp_ble_mesh_sensor_client_get_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_SENSOR_CLIENT;
@ -62,7 +59,7 @@ esp_err_t esp_ble_mesh_sensor_client_set_state(esp_ble_mesh_client_common_param_
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_SENSOR_CLIENT;

9
components/bt/esp_ble_mesh/api/models/esp_ble_mesh_time_scene_model_api.c
View File

@ -17,15 +17,12 @@
#include "btc/btc_task.h"
#include "btc/btc_manage.h"
#include "esp_bt_defs.h"
#include "esp_bt_main.h"
#include "btc_ble_mesh_time_scene_model.h"
#include "esp_ble_mesh_time_scene_model_api.h"
esp_err_t esp_ble_mesh_register_time_scene_client_callback(esp_ble_mesh_time_scene_client_cb_t callback)
{
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
return (btc_profile_cb_set(BTC_PID_TIME_SCENE_CLIENT, callback) == 0 ? ESP_OK : ESP_FAIL);
}
@ -40,7 +37,7 @@ esp_err_t esp_ble_mesh_time_scene_client_get_state(esp_ble_mesh_client_common_pa
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_TIME_SCENE_CLIENT;
@ -62,7 +59,7 @@ esp_err_t esp_ble_mesh_time_scene_client_set_state(esp_ble_mesh_client_common_pa
return ESP_ERR_INVALID_ARG;
}
ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
msg.sig = BTC_SIG_API_CALL;
msg.pid = BTC_PID_TIME_SCENE_CLIENT;

5
components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c
View File

@ -522,7 +522,7 @@ static void btc_ble_mesh_link_close_cb(bt_mesh_prov_bearer_t bearer)
return;
}
static void btc_ble_mesh_complete_cb(u16_t net_idx, u16_t addr, u8_t flags, u32_t iv_index)
static void btc_ble_mesh_complete_cb(u16_t net_idx, const u8_t net_key[16], u16_t addr, u8_t flags, u32_t iv_index)
{
esp_ble_mesh_prov_cb_param_t mesh_param = {0};
btc_msg_t msg = {0};
@ -531,6 +531,7 @@ static void btc_ble_mesh_complete_cb(u16_t net_idx, u16_t addr, u8_t flags, u32_
LOG_DEBUG("%s", __func__);
mesh_param.node_prov_complete.net_idx = net_idx;
memcpy(mesh_param.node_prov_complete.net_key, net_key, 16);
mesh_param.node_prov_complete.addr = addr;
mesh_param.node_prov_complete.flags = flags;
mesh_param.node_prov_complete.iv_index = iv_index;
@ -688,7 +689,7 @@ static void btc_ble_mesh_provisioner_recv_unprov_adv_pkt_cb(
}
memcpy(mesh_param.provisioner_recv_unprov_adv_pkt.dev_uuid, dev_uuid, 16);
memcpy(mesh_param.provisioner_recv_unprov_adv_pkt.addr, addr, ESP_BD_ADDR_LEN);
memcpy(mesh_param.provisioner_recv_unprov_adv_pkt.addr, addr, BLE_MESH_ADDR_LEN);
mesh_param.provisioner_recv_unprov_adv_pkt.addr_type = addr_type;
mesh_param.provisioner_recv_unprov_adv_pkt.oob_info = oob_info;
mesh_param.provisioner_recv_unprov_adv_pkt.adv_type = adv_type;

1
components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_prov.h
View File

@ -21,7 +21,6 @@
#include "freertos/semphr.h"
#include "btc/btc_task.h"
#include "esp_bt_defs.h"
#include "mesh_access.h"
#include "mesh_buf.h"

2
components/bt/esp_ble_mesh/mesh_core/adv.c
View File

@ -388,7 +388,7 @@ void bt_mesh_adv_init(void)
xBleMeshQueue = xQueueCreate(150, sizeof(bt_mesh_msg_t));
configASSERT(xBleMeshQueue);
int ret = xTaskCreatePinnedToCore(adv_thread, "BLE_Mesh_ADV_Task", 3072, NULL,
configMAX_PRIORITIES - 7, NULL, TASK_PINNED_TO_CORE);
configMAX_PRIORITIES - 7, NULL, ADV_TASK_CORE);
configASSERT(ret == pdTRUE);
}

38
components/bt/esp_ble_mesh/mesh_core/mesh_bearer_adapt.c → components/bt/esp_ble_mesh/mesh_core/bluedroid_host/mesh_bearer_adapt.c
View File

@ -19,6 +19,8 @@
#include "stack/hcimsgs.h"
#include "osi/future.h"
#include "osi/allocator.h"
#include "bt_common.h"
#include "device/controller.h"
#include "mbedtls/aes.h"
@ -32,6 +34,8 @@
#include "provisioner_prov.h"
#include "mesh_common.h"
struct bt_mesh_dev bt_mesh_dev;
#define BLE_MESH_BTM_CHECK_STATUS(func) do { \
tBTM_STATUS __status = (func); \
if ((__status != BTM_SUCCESS) && (__status != BTM_CMD_STARTED)) { \
@ -97,6 +101,40 @@ static struct bt_mesh_prov_conn_cb *bt_mesh_gattc_conn_cb;
static tBTA_GATTC_IF bt_mesh_gattc_if;
#endif /* defined(CONFIG_BLE_MESH_PROVISIONER) && CONFIG_BLE_MESH_PROVISIONER */
esp_err_t bt_mesh_host_init(void)
{
return ESP_OK;
}
void bt_mesh_hci_init(void)
{
const uint8_t *features = controller_get_interface()->get_features_ble()->as_array;
if (features != NULL) {
memcpy(bt_mesh_dev.features[0], features, 8);
memcpy(bt_mesh_dev.le.features, features, 8);
}
/**
* Currently 20ms non-connectable adv interval is supported, and we need to add
* a flag to indicate this support.
*/
#ifdef CONFIG_BLE_MESH_HCI_5_0
bt_mesh_dev.hci_version = BLE_MESH_HCI_VERSION_5_0;
#else
bt_mesh_dev.hci_version = controller_get_interface()->get_bt_version()->hci_version;
#endif
bt_mesh_dev.lmp_version = controller_get_interface()->get_bt_version()->lmp_version;
bt_mesh_dev.hci_revision = controller_get_interface()->get_bt_version()->hci_revision;
bt_mesh_dev.lmp_subversion = controller_get_interface()->get_bt_version()->lmp_subversion;
bt_mesh_dev.manufacturer = controller_get_interface()->get_bt_version()->manufacturer;
const uint8_t *p = controller_get_interface()->get_ble_supported_states();
uint64_t states_fh = 0, states_sh = 0;
STREAM_TO_UINT32(states_fh, p);
STREAM_TO_UINT32(states_sh, p);
bt_mesh_dev.le.states = (states_sh << 32) | states_fh;
}
static void bt_mesh_scan_results_change_2_bta(tBTM_INQ_RESULTS *p_inq, u8_t *p_eir,
tBTA_DM_SEARCH_CBACK *p_scan_cback)
{

17
components/bt/esp_ble_mesh/mesh_core/include/mesh_bearer_adapt.h
View File

@ -16,8 +16,23 @@
#include "mesh_uuid.h"
/* BLE Mesh Max Connection Count */
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#define BLE_MESH_MAX_CONN CONFIG_BT_ACL_CONNECTIONS
#define ADV_TASK_CORE TASK_PINNED_TO_CORE
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
#define BLE_MESH_MAX_CONN CONFIG_BT_NIMBLE_MAX_CONNECTIONS
#ifdef CONFIG_BT_NIMBLE_PINNED_TO_CORE
#define ADV_TASK_CORE (CONFIG_BT_NIMBLE_PINNED_TO_CORE < portNUM_PROCESSORS ? CONFIG_BT_NIMBLE_PINNED_TO_CORE : tskNO_AFFINITY)
#else
#define ADV_TASK_CORE (0)
#endif
#endif
/* BD ADDR types */
#define BLE_MESH_ADDR_PUBLIC 0x00
#define BLE_MESH_ADDR_RANDOM 0x01
@ -620,6 +635,8 @@ struct bt_mesh_gatt_attr {
.attr_count = ARRAY_SIZE(_attrs), \
}
esp_err_t bt_mesh_host_init(void);
int bt_le_adv_start(const struct bt_mesh_adv_param *param,
const struct bt_mesh_adv_data *ad, size_t ad_len,
const struct bt_mesh_adv_data *sd, size_t sd_len);

3
components/bt/esp_ble_mesh/mesh_core/include/mesh_main.h
View File

@ -164,11 +164,12 @@ struct bt_mesh_prov {
* assigned the specified NetKeyIndex and primary element address.
*
* @param net_idx NetKeyIndex given during provisioning.
* @param net_key NetKey given during provisioning.
* @param addr Primary element address.
* @param flags Key Refresh & IV Update flags
* @param iv_index IV Index.
*/
void (*complete)(u16_t net_idx, u16_t addr, u8_t flags, u32_t iv_index);
void (*complete)(u16_t net_idx, const u8_t net_key[16], u16_t addr, u8_t flags, u32_t iv_index);
/** @brief Node has been reset.
*

6
components/bt/esp_ble_mesh/mesh_core/include/mesh_trace.h
View File

@ -47,6 +47,12 @@
#define MESH_TRACE_TAG "BLE_MESH"
#define LOG_ERROR(format, ... ) {if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) esp_log_write(ESP_LOG_ERROR, "BT_LOG", LOG_FORMAT(E, format), esp_log_timestamp(), "BT_LOG", ##__VA_ARGS__); }
#define LOG_WARN(format, ... ) {if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) esp_log_write(ESP_LOG_WARN, "BT_LOG", LOG_FORMAT(W, format), esp_log_timestamp(), "BT_LOG", ##__VA_ARGS__); }
#define LOG_INFO(format, ... ) {if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) esp_log_write(ESP_LOG_INFO, "BT_LOG", LOG_FORMAT(I, format), esp_log_timestamp(), "BT_LOG", ##__VA_ARGS__); }
#define LOG_DEBUG(format, ... ) {if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) esp_log_write(ESP_LOG_DEBUG, "BT_LOG", LOG_FORMAT(D, format), esp_log_timestamp(), "BT_LOG", ##__VA_ARGS__); }
#define LOG_VERBOSE(format, ... ) {if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) esp_log_write(ESP_LOG_VERBOSE, "BT_LOG", LOG_FORMAT(V, format), esp_log_timestamp(), "BT_LOG", ##__VA_ARGS__); }
#if (LOG_LOCAL_LEVEL >= 4)
#define BLE_MESH_LOG_LOCAL_LEVEL_MAPPING (LOG_LOCAL_LEVEL + 1)
#else

45
components/bt/esp_ble_mesh/mesh_core/mesh_hci.c
View File

@ -1,45 +0,0 @@
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
* Copyright (c) 2015-2016 Intel Corporation
* Additional Copyright (c) 2018 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "stack/bt_types.h"
#include "device/controller.h"
#include "mesh_hci.h"
struct bt_mesh_dev bt_mesh_dev;
void bt_mesh_hci_init(void)
{
const uint8_t *features = controller_get_interface()->get_features_ble()->as_array;
if (features != NULL) {
memcpy(bt_mesh_dev.features[0], features, 8);
memcpy(bt_mesh_dev.le.features, features, 8);
}
/**
* Currently 20ms non-connectable adv interval is supported, and we need to add
* a flag to indicate this support.
*/
#ifdef CONFIG_BLE_MESH_HCI_5_0
bt_mesh_dev.hci_version = BLE_MESH_HCI_VERSION_5_0;
#else
bt_mesh_dev.hci_version = controller_get_interface()->get_bt_version()->hci_version;
#endif
bt_mesh_dev.lmp_version = controller_get_interface()->get_bt_version()->lmp_version;
bt_mesh_dev.hci_revision = controller_get_interface()->get_bt_version()->hci_revision;
bt_mesh_dev.lmp_subversion = controller_get_interface()->get_bt_version()->lmp_subversion;
bt_mesh_dev.manufacturer = controller_get_interface()->get_bt_version()->manufacturer;
const uint8_t *p = controller_get_interface()->get_ble_supported_states();
uint64_t states_fh = 0, states_sh = 0;
STREAM_TO_UINT32(states_fh, p);
STREAM_TO_UINT32(states_sh, p);
bt_mesh_dev.le.states = (states_sh << 32) | states_fh;
}

3
components/bt/esp_ble_mesh/mesh_core/mesh_kernel.c
View File

@ -14,8 +14,7 @@
#include "osi/alarm.h"
#include "osi/hash_functions.h"
#include "common/bt_trace.h"
#include "common/bt_defs.h"
#include "bt_common.h"
#include "esp_timer.h"

3
components/bt/esp_ble_mesh/mesh_core/net.c
View File

@ -1476,11 +1476,12 @@ void bt_mesh_net_start(void)
u16_t addr = bt_mesh_primary_addr();
u32_t iv_index = bt_mesh.iv_index;
u8_t flags = (u8_t)bt_mesh.sub[0].kr_flag;
const u8_t *net_key = bt_mesh.sub[0].keys[flags].net;
if (bt_mesh_atomic_test_bit(bt_mesh.flags, BLE_MESH_IVU_IN_PROGRESS)) {
flags |= BLE_MESH_NET_FLAG_IVU;
}
bt_mesh_prov_complete(net_idx, addr, flags, iv_index);
bt_mesh_prov_complete(net_idx, net_key, addr, flags, iv_index);
}
}
#endif

1796
components/bt/esp_ble_mesh/mesh_core/nimble_host/mesh_bearer_adapt.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
components/bt/esp_ble_mesh/mesh_core/prov.c
View File

@ -1744,10 +1744,10 @@ int bt_mesh_prov_init(const struct bt_mesh_prov *prov_info)
return 0;
}
void bt_mesh_prov_complete(u16_t net_idx, u16_t addr, u8_t flags, u32_t iv_index)
void bt_mesh_prov_complete(u16_t net_idx, const u8_t net_key[16], u16_t addr, u8_t flags, u32_t iv_index)
{
if (prov->complete) {
prov->complete(net_idx, addr, flags, iv_index);
prov->complete(net_idx, net_key, addr, flags, iv_index);
}
}

2
components/bt/esp_ble_mesh/mesh_core/prov.h
View File

@ -28,7 +28,7 @@ const struct bt_mesh_prov *bt_mesh_prov_get(void);
int bt_mesh_prov_init(const struct bt_mesh_prov *prov);
void bt_mesh_prov_complete(u16_t net_idx, u16_t addr, u8_t flags, u32_t iv_index);
void bt_mesh_prov_complete(u16_t net_idx, const u8_t net_key[16], u16_t addr, u8_t flags, u32_t iv_index);
void bt_mesh_prov_reset(void);
#endif /* _PROV_H_ */

1
components/bt/esp_ble_mesh/mesh_core/settings.c
View File

@ -538,6 +538,7 @@ static int cfg_set(const char *name)
return 0;
}
memcpy(&stored_cfg.cfg, &val, sizeof(val));
stored_cfg.valid = true;
BT_DBG("Restore configuration state");
return 0;

1
components/bt/host/bluedroid/api/esp_gap_bt_api.c
View File

@ -17,6 +17,7 @@
#include "esp_bt_main.h"
#include "esp_gap_bt_api.h"
#include "common/bt_trace.h"
#include "bta/bta_api.h"
#include "btc/btc_manage.h"
#include "btc_gap_bt.h"
#include "btc/btc_storage.h"

1
components/bt/host/nimble/Kconfig.in
View File

@ -53,6 +53,7 @@ config BT_NIMBLE_PINNED_TO_CORE
config BT_NIMBLE_TASK_STACK_SIZE
int "NimBLE Host task stack size"
depends on BT_NIMBLE_ENABLED
default 5120 if BLE_MESH
default 4096
help
This configures stack size of NimBLE host task

5
components/esp32/CMakeLists.txt
View File

@ -62,6 +62,11 @@ else()
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32.extram.bss.ld")
endif()
if(NOT CONFIG_COMPILER_CXX_RTTI)
# This has to be linked before esp32.project.ld
target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32.discard-rtti.ld")
endif()
# Process the template file through the linker script generation mechanism, and use the output for linking the
# final binary
target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32.project.ld.in"

21
components/esp32/component.mk
View File

@ -5,18 +5,23 @@
COMPONENT_SRCDIRS := .
ifdef CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
# This linker script must come before esp32.project.ld
LINKER_SCRIPTS += esp32.extram.bss.ld
# This linker script must come before esp32.project.ld
LINKER_SCRIPTS += esp32.extram.bss.ld
endif
#Linker scripts used to link the final application.
#Warning: These linker scripts are only used when the normal app is compiled; the bootloader
#specifies its own scripts.
ifndef CONFIG_COMPILER_CXX_RTTI
# This linker script must come before esp32.project.ld
LINKER_SCRIPTS += esp32.discard-rtti.ld
endif
# Linker scripts used to link the final application.
# Warning: These linker scripts are only used when the normal app is compiled; the bootloader
# specifies its own scripts.
LINKER_SCRIPTS += $(COMPONENT_BUILD_DIR)/esp32.project.ld esp32.peripherals.ld
#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
#linker will ignore panic_highint_hdl.S as it has no other files depending on any
#symbols in it.
# ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
# linker will ignore panic_highint_hdl.S as it has no other files depending on any
# symbols in it.
COMPONENT_ADD_LDFLAGS += -L $(COMPONENT_PATH)/ld \
-T esp32_out.ld \
-u ld_include_panic_highint_hdl \

11
components/esp32/ld/esp32.discard-rtti.ld Normal file
View File

@ -0,0 +1,11 @@
/* This is only included if CONFIG_COMPILER_CXX_RTTI is not set, to
* move RTTI sections of libstdc++ to an unused non-loadable memory region.
*/
SECTIONS
{
.rodata.discard-rtti (NOLOAD):
{
*libstdc++.a:(.rodata._ZTI* .rodata._ZTS*)
} > discard_seg
}

5
components/esp32/ld/esp32.ld
View File

@ -100,6 +100,11 @@ MEMORY
/* external memory ,including data and text */
extern_ram_seg(RWX) : org = 0x3F800000,
len = 0x400000
/* This is not a memory range which can really be accessed; we use it as a "bitbucket"
where non-loadable sections, which aren't used at run time, can be discarded.
*/
discard_seg (R) : org = 0x00000000, len = 0x10000000
}
#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)

2
components/esp_wifi/lib_esp32

@ -1 +1 @@
Subproject commit 23b783ed58af8a3cbf787fe72beec1305924d7f7
Subproject commit 1068594fee5fd8a73b353c4e77ff3b44d111393d

2
components/fatfs/vfs/vfs_fat_sdmmc.c
View File

@ -159,6 +159,8 @@ fail:
ff_diskio_unregister(pdrv);
free(s_card);
s_card = NULL;
free(s_base_path);
s_base_path = NULL;
return err;
}

12
components/heap/heap_caps.c
View File

@ -333,6 +333,18 @@ IRAM_ATTR void *heap_caps_calloc( size_t n, size_t size, uint32_t caps)
return result;
}
size_t heap_caps_get_total_size(uint32_t caps)
{
size_t total_size = 0;
heap_t *heap;
SLIST_FOREACH(heap, &registered_heaps, next) {
if (heap_caps_match(heap, caps)) {
total_size += (heap->end - heap->start);
}
}
return total_size;
}
size_t heap_caps_get_free_size( uint32_t caps )
{
size_t ret = 0;

14
components/heap/include/esp_heap_caps.h
View File

@ -101,6 +101,20 @@ void *heap_caps_realloc( void *ptr, size_t size, int caps);
*/
void *heap_caps_calloc(size_t n, size_t size, uint32_t caps);
/**
* @brief Get the total size of all the regions that have the given capabilities
*
* This function takes all regions capable of having the given capabilities allocated in them
* and adds up the total space they have.
*
* @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type
* of memory
*
* @return total size in bytes
*/
size_t heap_caps_get_total_size(uint32_t caps);
/**
* @brief Get the total free size of all the regions that have the given capabilities
*

2
components/lwip/lwip

@ -1 +1 @@
Subproject commit 8c801667e8586ae6dedf80d13aaaec71b7b9a33d
Subproject commit 89932176f598bb1b6595c65bfc7832334e0a1e08

8
components/mbedtls/port/net_sockets.c
View File

@ -198,14 +198,6 @@ static int net_would_block( const mbedtls_net_context *ctx )
{
int error = errno;
/*
* Never return 'WOULD BLOCK' on a non-blocking socket
*/
if ( ( fcntl( ctx->fd, F_GETFL, 0) & O_NONBLOCK ) != O_NONBLOCK ) {
errno = error;
return ( 0 );
}
switch ( errno = error ) {
#if defined EAGAIN
case EAGAIN:

4
components/mdns/mdns.c
View File

@ -3062,7 +3062,7 @@ static void _mdns_handle_system_event(esp_event_base_t event_base,
switch(event_id) {
case WIFI_EVENT_STA_CONNECTED:
if (!tcpip_adapter_dhcpc_get_status(TCPIP_ADAPTER_IF_STA, &dcst)) {
if (dcst != TCPIP_ADAPTER_DHCP_STARTED) {
if (dcst == TCPIP_ADAPTER_DHCP_STOPPED) {
_mdns_enable_pcb(TCPIP_ADAPTER_IF_STA, MDNS_IP_PROTOCOL_V4);
}
}
@ -3087,7 +3087,7 @@ static void _mdns_handle_system_event(esp_event_base_t event_base,
switch (event_id) {
case ETHERNET_EVENT_CONNECTED:
if (!tcpip_adapter_dhcpc_get_status(TCPIP_ADAPTER_IF_ETH, &dcst)) {
if (dcst != TCPIP_ADAPTER_DHCP_STARTED) {
if (dcst == TCPIP_ADAPTER_DHCP_STOPPED) {
_mdns_enable_pcb(TCPIP_ADAPTER_IF_ETH, MDNS_IP_PROTOCOL_V4);
}
}

2
components/mqtt/esp-mqtt

@ -1 +1 @@
Subproject commit fb3d2107cdac440d84f2fab81ea9b5217aa4ba1f
Subproject commit e3b013e2db58124ea68cf7c8f44a8cba6e1572b7

3
components/mqtt/weekend_test/mqtt_publish_test.py
View File

@ -81,13 +81,12 @@ def test_single_config(dut, transport, qos, repeat, published):
try:
if transport in ["ws", "wss"]:
client = mqtt.Client(transport="websockets")
client.ws_set_options(path="/ws", headers=None)
else:
client = mqtt.Client()
client.on_connect = on_connect
client.on_message = on_message
if transport in ["ssl", "wss"]:
client.tls_set(None, None, None, cert_reqs=ssl.CERT_NONE, tls_version=ssl.PROTOCOL_TLSv1, ciphers=None)
client.tls_set(None, None, None, cert_reqs=ssl.CERT_NONE, tls_version=ssl.PROTOCOL_TLSv1_2, ciphers=None)
client.tls_insecure_set(True)
print("Connecting...")
client.connect(broker_host[transport], broker_port[transport], 60)

17
components/soc/esp32/include/hal/spi_flash_ll.h
View File

@ -202,21 +202,6 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
return dev->ext2.st != 0;
}
/**
* Set phases for user-defined transaction to read
*
* @param dev Beginning address of the peripheral registers.
*/
static inline void spi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
};
dev->user = user;
}
/*------------------------------------------------------------------------------
* Configs
*----------------------------------------------------------------------------*/
@ -239,7 +224,7 @@ static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
* @param dev Beginning address of the peripheral registers.
* @param read_mode I/O mode to use in the following transactions.
*/
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_read_mode_t read_mode)
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);

29
components/soc/include/hal/spi_flash_hal.h
View File

@ -155,23 +155,38 @@ esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, boo
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
/**
* Configure the SPI host hardware registers for the specified read mode.
* @brief Configure the SPI host hardware registers for the specified io mode.
*
* Note that calling this configures SPI host registers, so if running any
* other commands as part of set_read_mode() then these must be run before
* other commands as part of set_io_mode() then these must be run before
* calling this function.
*
* The command value, address length and dummy cycles are configured according
* to the format of read commands:
*
* - command: 8 bits, value set.
* - address: 24 bits
* - dummy: cycles to compensate the input delay
* - out & in data: 0 bits.
*
* The following commands still need to:
*
* - Read data: set address value and data (length and contents), no need
* to touch command and dummy phases.
* - Common read: set command value, address value (or length to 0 if not used)
* - Common write: set command value, address value (or length to 0 if not
* used), disable dummy phase, and set output data.
*
* @param driver The driver context
* @param read_mode The HW read mode to use
* @param io_mode The HW read mode to use
* @param addr_bitlen Length of the address phase, in bits
* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
* @param read_command Actual reading command to send to flash chip on the bus.
* @param command Actual reading command to send to flash chip on the bus.
*
* @return always return ESP_OK.
*/
esp_err_t spi_flash_hal_configure_host_read_mode(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode,
uint32_t addr_bitlen, uint32_t dummy_cyclelen_base,
uint32_t read_command);
esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
/**
* Poll until the last operation is done.

8
components/soc/include/hal/spi_flash_types.h
View File

@ -61,7 +61,7 @@ typedef enum {
SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
} esp_flash_read_mode_t;
} esp_flash_io_mode_t;
///Slowest io mode supported by ESP32, currently SlowRd
#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
@ -130,9 +130,11 @@ struct spi_flash_host_driver_t {
*/
bool (*host_idle)(spi_flash_host_driver_t *driver);
/**
* Configure the host to work at different read mode.
* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
*/
esp_err_t (*configure_host_read_mode)(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode, uint32_t addr_bitlen, uint32_t dummy_bitlen_base, uint32_t read_command);
esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
uint32_t addr_bitlen, int dummy_bitlen_base,
esp_flash_io_mode_t io_mode);
/**
* Internal use, poll the HW until the last operation is done.
*/

5
components/soc/src/hal/spi_flash_hal.c
View File

@ -67,8 +67,3 @@ esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_
ESP_EARLY_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
return ESP_OK;
}
static inline spi_dev_t *get_spi_dev(spi_flash_host_driver_t *chip_drv)
{
return ((spi_flash_memspi_data_t *)chip_drv->driver_data)->spi;
}

93
components/soc/src/hal/spi_flash_hal_iram.c
View File

@ -19,22 +19,22 @@
#define ADDRESS_MASK_24BIT 0xFFFFFF
static inline spi_dev_t *get_spi_dev(spi_flash_host_driver_t *chip_drv)
static inline spi_dev_t *get_spi_dev(spi_flash_host_driver_t *host)
{
return ((spi_flash_memspi_data_t *)chip_drv->driver_data)->spi;
return ((spi_flash_memspi_data_t *)host->driver_data)->spi;
}
void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver)
void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *host)
{
while (!spi_flash_ll_cmd_is_done(get_spi_dev(driver))) {
while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) {
//nop
}
}
esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver)
esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *host)
{
spi_flash_memspi_data_t *drv_data = (spi_flash_memspi_data_t *)driver->driver_data;
spi_dev_t *dev = get_spi_dev(driver);
spi_flash_memspi_data_t *drv_data = (spi_flash_memspi_data_t *)host->driver_data;
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_reset(dev);
spi_flash_ll_set_cs_pin(dev, drv_data->cs_num);
spi_flash_ll_set_clock(dev, &drv_data->clock_conf);
@ -52,89 +52,98 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver)
return ESP_OK;
}
esp_err_t spi_flash_hal_configure_host_read_mode(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode,
uint32_t addr_bitlen, uint32_t dummy_cyclelen_base,
uint32_t read_command)
esp_err_t spi_flash_hal_configure_host_io_mode(
spi_flash_host_driver_t *host,
uint32_t command,
uint32_t addr_bitlen,
int dummy_cyclelen_base,
esp_flash_io_mode_t io_mode)
{
// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
int dummy_cyclelen = dummy_cyclelen_base + ((spi_flash_memspi_data_t *)driver->driver_data)->extra_dummy;
int dummy_cyclelen = dummy_cyclelen_base + ((spi_flash_memspi_data_t *)host->driver_data)->extra_dummy;
spi_dev_t *dev = get_spi_dev(driver);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_set_command8(dev, command);
spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
spi_flash_ll_set_command8(dev, read_command);
spi_flash_ll_read_phase(dev);
spi_flash_ll_set_dummy(dev, dummy_cyclelen);
spi_flash_ll_set_read_mode(dev, read_mode);
//disable all data phases, enable them later if needed
spi_flash_ll_set_miso_bitlen(dev, 0);
spi_flash_ll_set_mosi_bitlen(dev, 0);
spi_flash_ll_set_read_mode(dev, io_mode);
return ESP_OK;
}
esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *chip_drv, spi_flash_trans_t *trans)
esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *host, spi_flash_trans_t *trans)
{
chip_drv->configure_host_read_mode(chip_drv, SPI_FLASH_FASTRD, 0, 0, 0);
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_flash_ll_set_command8(dev, trans->command);
spi_flash_ll_set_addr_bitlen(dev, 0);
host->configure_host_io_mode(host, trans->command, 0, 0, SPI_FLASH_FASTRD);
spi_dev_t *dev = get_spi_dev(host);
//disable dummy if no input phase
if (trans->miso_len == 0) {
spi_flash_ll_set_dummy(dev, 0);
}
spi_flash_ll_set_miso_bitlen(dev, trans->miso_len);
spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len);
spi_flash_ll_write_word(dev, trans->mosi_data);
spi_flash_ll_user_start(dev);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
spi_flash_ll_get_buffer_data(dev, trans->miso_data, 8);
return ESP_OK;
}
void spi_flash_hal_erase_chip(spi_flash_host_driver_t *chip_drv)
void spi_flash_hal_erase_chip(spi_flash_host_driver_t *host)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_erase_chip(dev);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
}
void spi_flash_hal_erase_sector(spi_flash_host_driver_t *chip_drv, uint32_t start_address)
void spi_flash_hal_erase_sector(spi_flash_host_driver_t *host, uint32_t start_address)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_set_addr_bitlen(dev, 24);
spi_flash_ll_set_address(dev, start_address & ADDRESS_MASK_24BIT);
spi_flash_ll_erase_sector(dev);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
}
void spi_flash_hal_erase_block(spi_flash_host_driver_t *chip_drv, uint32_t start_address)
void spi_flash_hal_erase_block(spi_flash_host_driver_t *host, uint32_t start_address)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_set_addr_bitlen(dev, 24);
spi_flash_ll_set_address(dev, start_address & ADDRESS_MASK_24BIT);
spi_flash_ll_erase_block(dev);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
}
void spi_flash_hal_program_page(spi_flash_host_driver_t *chip_drv, const void *buffer, uint32_t address, uint32_t length)
void spi_flash_hal_program_page(spi_flash_host_driver_t *host, const void *buffer, uint32_t address, uint32_t length)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_set_addr_bitlen(dev, 24);
spi_flash_ll_set_address(dev, (address & ADDRESS_MASK_24BIT) | (length << 24));
spi_flash_ll_program_page(dev, buffer, length);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
}
esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *chip_drv, void *buffer, uint32_t address, uint32_t read_len)
esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *host, void *buffer, uint32_t address, uint32_t read_len)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
//the command is already set by ``spi_flash_hal_configure_host_read_mode`` before.
spi_dev_t *dev = get_spi_dev(host);
//the command is already set by ``spi_flash_hal_configure_host_io_mode`` before.
spi_flash_ll_set_address(dev, address << 8);
spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
spi_flash_ll_user_start(dev);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
spi_flash_ll_get_buffer_data(dev, buffer, read_len);
return ESP_OK;
}
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *chip_drv)
bool spi_flash_hal_host_idle(spi_flash_host_driver_t *host)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
bool idle = spi_flash_ll_host_idle(dev);
// Not clear if this is necessary, or only necessary if
@ -146,10 +155,10 @@ bool spi_flash_hal_host_idle(spi_flash_host_driver_t *chip_drv)
return idle;
}
esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp)
esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *host, bool wp)
{
spi_dev_t *dev = get_spi_dev(chip_drv);
spi_dev_t *dev = get_spi_dev(host);
spi_flash_ll_set_write_protect(dev, wp);
chip_drv->poll_cmd_done(chip_drv);
host->poll_cmd_done(host);
return ESP_OK;
}

49
components/spi_flash/CMakeLists.txt
View File

@ -1,30 +1,46 @@
set(priv_requires bootloader_support soc)
if(BOOTLOADER_BUILD)
# on ESP32, we will include spi_flash_rom_patch.c
# but on other platforms no source files are needed for bootloader
set(srcs)
if (CONFIG_IDF_TARGET_ESP32)
# ESP32 Bootloader needs SPIUnlock from this file, but doesn't
# need other parts of this component
set(srcs "spi_flash_rom_patch.c")
else()
# but on other platforms no source files are needed for bootloader
set(srcs)
endif()
set(cache_srcs "")
else()
set(srcs
set(cache_srcs
"cache_utils.c"
"flash_mmap.c"
"flash_ops.c"
"partition.c"
)
set(srcs
"partition.c")
if (CONFIG_IDF_TARGET_ESP32)
list(APPEND srcs
"spi_flash_rom_patch.c")
endif()
# New implementation after IDF v4.0
list(APPEND srcs
"spi_flash_chip_drivers.c"
"spi_flash_chip_generic.c"
"spi_flash_chip_issi.c"
"spi_flash_rom_patch.c"
)
"spi_flash_chip_gd.c")
if (NOT CONFIG_IDF_TARGET_ESP32S2BETA)
# TODO: workaround until ESP32-S2 supports new API, can be always included
list(APPEND srcs "esp_flash_spi_init.c"
"memspi_host_driver.c"
"spi_flash_os_func_app.c"
"spi_flash_os_func_noos.c"
"memspi_host_driver.c"
"esp_flash_api.c"
)
list(APPEND srcs
"memspi_host_driver.c")
list(APPEND cache_srcs
"esp_flash_api.c"
"esp_flash_spi_init.c"
"spi_flash_os_func_app.c"
"spi_flash_os_func_noos.c")
endif()
list(APPEND srcs ${cache_srcs})
set(priv_requires bootloader_support app_update soc)
endif()
@ -38,3 +54,6 @@ idf_component_register(SRCS "${srcs}"
PRIV_INCLUDE_DIRS private_include
LDFRAGMENTS linker.lf)
# Avoid cache miss by unexpected inlineing when built by -Os
set_source_files_properties(${cache_srcs} PROPERTIES COMPILE_FLAGS
"-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once")

19
components/spi_flash/Kconfig
View File

@ -99,8 +99,23 @@ menu "SPI Flash driver"
bool "ISSI"
default y
help
Enable this to support auto detection of ISSI chips if chip vendor not specified.
This adds support for variant chips, however will extend detecting time.
Enable this to support auto detection of ISSI chips if chip vendor not directly
given by ``chip_drv`` member of the chip struct. This adds support for variant
chips, however will extend detecting time.
config SPI_FLASH_SUPPORT_GD_CHIP
bool "GigaDevice"
default y
help
Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
modules, please don't disable this, otherwise your flash may not work in 4-bit
mode.
This adds support for variant chips, however will extend detecting time and image
size. Note that the default chip driver supports the GD chips with product ID
60H.
endmenu #auto detect flash chips
endmenu

98
components/spi_flash/esp_flash_api.c
View File

@ -60,8 +60,9 @@ static const char io_mode_str[][IO_STR_LEN] = {
"qio",
};
_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_read_mode_t defined in spi_flash_ll.h");
_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_io_mode_t defined in spi_flash_ll.h");
esp_err_t esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id);
/* Static function to notify OS of a new SPI flash operation.
@ -115,6 +116,18 @@ esp_err_t IRAM_ATTR esp_flash_init(esp_flash_t *chip)
return ESP_ERR_INVALID_ARG;
}
//read chip id
uint32_t flash_id;
int retries = 10;
do {
err = esp_flash_read_chip_id(chip, &flash_id);
} while (err == ESP_ERR_FLASH_NOT_INITIALISED && retries-- > 0);
if (err != ESP_OK) {
return err;
}
chip->chip_id = flash_id;
if (!esp_flash_chip_driver_initialized(chip)) {
// Detect chip_drv
err = detect_spi_flash_chip(chip);
@ -139,38 +152,43 @@ esp_err_t IRAM_ATTR esp_flash_init(esp_flash_t *chip)
if (err == ESP_OK) {
// Try to set the flash mode to whatever default mode was chosen
err = chip->chip_drv->set_read_mode(chip);
err = chip->chip_drv->set_io_mode(chip);
if (err == ESP_ERR_FLASH_NO_RESPONSE && !esp_flash_is_quad_mode(chip)) {
//some chips (e.g. Winbond) don't support to clear QE, treat as success
err = ESP_OK;
}
}
// Done: all fields on 'chip' are initialised
return spiflash_end(chip, err);
}
//this is not public, but useful in unit tests
esp_err_t IRAM_ATTR esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id)
{
esp_err_t err = spiflash_start(chip);
if (err != ESP_OK) {
return err;
}
// Send generic RDID command twice, check for a matching result and retry in case we just powered on (inner
// function fails if it sees all-ones or all-zeroes.)
err = chip->host->read_id(chip->host, flash_id);
if (err == ESP_OK) { // check we see the same ID twice, in case of transient power-on errors
uint32_t new_id;
err = chip->host->read_id(chip->host, &new_id);
if (err == ESP_OK && (new_id != *flash_id)) {
err = ESP_ERR_FLASH_NOT_INITIALISED;
}
}
return spiflash_end(chip, err);
}
static esp_err_t IRAM_ATTR detect_spi_flash_chip(esp_flash_t *chip)
{
esp_err_t err;
uint32_t flash_id;
int retries = 10;
do {
err = spiflash_start(chip);
if (err != ESP_OK) {
return err;
}
// Send generic RDID command twice, check for a matching result and retry in case we just powered on (inner
// function fails if it sees all-ones or all-zeroes.)
err = chip->host->read_id(chip->host, &flash_id);
if (err == ESP_OK) { // check we see the same ID twice, in case of transient power-on errors
uint32_t new_id;
err = chip->host->read_id(chip->host, &new_id);
if (err == ESP_OK && (new_id != flash_id)) {
err = ESP_ERR_FLASH_NOT_INITIALISED;
}
}
err = spiflash_end(chip, err);
} while (err != ESP_OK && retries-- > 0);
uint32_t flash_id = chip->chip_id;
// Detect the chip and set the chip_drv structure for it
const spi_flash_chip_t **drivers = esp_flash_registered_chips;
@ -617,6 +635,36 @@ esp_err_t IRAM_ATTR esp_flash_read_encrypted(esp_flash_t *chip, uint32_t address
return spi_flash_read_encrypted(address, out_buffer, length);
}
// test only, non-public
IRAM_ATTR esp_err_t esp_flash_get_io_mode(esp_flash_t* chip, bool* qe)
{
VERIFY_OP(get_io_mode);
esp_flash_io_mode_t io_mode;
esp_err_t err = spiflash_start(chip);
if (err != ESP_OK) {
return err;
}
err = chip->chip_drv->get_io_mode(chip, &io_mode);
err = spiflash_end(chip, err);
if (err == ESP_OK) {
*qe = (io_mode == SPI_FLASH_QOUT);
}
return err;
}
IRAM_ATTR esp_err_t esp_flash_set_io_mode(esp_flash_t* chip, bool qe)
{
VERIFY_OP(set_io_mode);
chip->read_mode = (qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD);
esp_err_t err = spiflash_start(chip);
if (err != ESP_OK) {
return err;
}
err = chip->chip_drv->set_io_mode(chip);
return spiflash_end(chip, err);
}
#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
esp_err_t esp_flash_app_disable_protect(bool disable)
{

2
components/spi_flash/esp_flash_spi_init.c
View File

@ -62,7 +62,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
esp_flash_t *esp_flash_default_chip = NULL;
static IRAM_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux)
static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux)
{
//Not using spicommon_cs_initialize since we don't want to put the whole
//spi_periph_signal into the DRAM. Copy these data from flash before the

10
components/spi_flash/flash_ops.c
View File

@ -519,7 +519,17 @@ esp_err_t IRAM_ATTR spi_flash_read(size_t src, void *dstv, size_t size)
goto out;
}
COUNTER_ADD_BYTES(read, read_size);
#ifdef ESP_PLATFORM
if (esp_ptr_external_ram(dstv)) {
spi_flash_guard_end();
memcpy(dstv, ((uint8_t *) t) + left_off, size);
spi_flash_guard_start();
} else {
memcpy(dstv, ((uint8_t *) t) + left_off, size);
}
#else
memcpy(dstv, ((uint8_t *) t) + left_off, size);
#endif
goto out;
}
uint8_t *dstc = (uint8_t *) dstv;

19
components/spi_flash/include/esp_flash.h
View File

@ -63,8 +63,9 @@ struct esp_flash_t {
const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized.
void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``.
esp_flash_read_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation.
uint32_t chip_id; ///< Detected chip id.
};
@ -286,6 +287,22 @@ esp_err_t esp_flash_read_encrypted(esp_flash_t *chip, uint32_t address, void *ou
extern esp_flash_t *esp_flash_default_chip;
/*******************************************************************************
* Utility Functions
******************************************************************************/
/**
* @brief Returns true if chip is configured for Quad I/O or Quad Fast Read.
*
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
*
* @return true if flash works in quad mode, otherwise false
*/
static inline bool esp_flash_is_quad_mode(const esp_flash_t *chip)
{
return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
}
#ifdef __cplusplus
}
#endif

2
components/spi_flash/include/esp_flash_spi_init.h
View File

@ -22,7 +22,7 @@ typedef struct {
spi_host_device_t host_id; ///< Bus to use
int cs_id; ///< CS pin (signal) to use
int cs_io_num; ///< GPIO pin to output the CS signal
esp_flash_read_mode_t io_mode; ///< IO mode to read from the Flash
esp_flash_io_mode_t io_mode; ///< IO mode to read from the Flash
esp_flash_speed_t speed; ///< Speed of the Flash clock
int input_delay_ns; ///< Input delay of the data pins, in ns. Set to 0 if unknown.
} esp_flash_spi_device_config_t;

2
components/spi_flash/include/memspi_host_driver.h
View File

@ -32,7 +32,7 @@
.read = spi_flash_hal_read, \
.max_read_bytes = SPI_FLASH_HAL_MAX_READ_BYTES, \
.host_idle = spi_flash_hal_host_idle, \
.configure_host_read_mode = spi_flash_hal_configure_host_read_mode, \
.configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \
.poll_cmd_done = spi_flash_hal_poll_cmd_done, \
.flush_cache = memspi_host_flush_cache, \
}

8
components/spi_flash/include/spi_flash_chip_driver.h
View File

@ -149,7 +149,13 @@ struct spi_flash_chip_t {
*
* Can return ESP_ERR_FLASH_UNSUPPORTED_HOST or ESP_ERR_FLASH_UNSUPPORTED_CHIP if the specified mode is unsupported.
*/
esp_err_t (*set_read_mode)(esp_flash_t *chip);
esp_err_t (*set_io_mode)(esp_flash_t *chip);
/*
* Get whether the Quad Enable (QE) is set. (*out_io_mode)=SPI_FLASH_QOUT if
* enabled, otherwise disabled
*/
esp_err_t (*get_io_mode)(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode);
};
/* Pointer to an array of pointers to all known drivers for flash chips. This array is used

32
components/spi_flash/include/spi_flash_chip_gd.h Normal file
View File

@ -0,0 +1,32 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include "esp_flash.h"
#include "spi_flash_chip_driver.h"
/**
* GD (GigaDevice) SPI flash chip_drv, uses all the above functions for its operations. In
* default autodetection, this is used as a catchall if a more specific chip_drv
* is not found.
*
* Note that this is for GD chips with product ID 40H (GD25Q) and 60H (GD25LQ). The chip diver uses
* different commands to write the SR2 register according to the chip ID. For GD25Q40 - GD25Q16
* chips, and GD25LQ chips, WRSR (01H) command is used; while WRSR2 (31H) is used for GD25Q32 -
* GD25Q127 chips.
*/
extern const spi_flash_chip_t esp_flash_chip_gd;

118
components/spi_flash/include/spi_flash_chip_generic.h
View File

@ -213,7 +213,21 @@ esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_m
* - ESP_ERR_TIMEOUT if not idle before timeout
* - or other error passed from the ``set_write_protect`` or ``common_command`` function of host driver
*/
esp_err_t spi_flash_chip_generic_set_read_mode(esp_flash_t *chip);
esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip);
/**
* Get whether the Quad Enable (QE) is set.
*
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
* @param out_quad_mode Pointer to store the output mode.
* - SPI_FLASH_QOUT: QE is enabled
* - otherwise: QE is disabled
*
* @return
* - ESP_OK if success
* - or other error passed from the ``common_command`` function of host driver
*/
esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_quad_mode);
/**
* Generic SPI flash chip_drv, uses all the above functions for its operations.
@ -244,6 +258,78 @@ extern const spi_flash_chip_t esp_flash_chip_generic;
*/
esp_err_t spi_flash_generic_wait_host_idle(esp_flash_t *chip, uint32_t *timeout_ms);
/// Function pointer type for reading status register with QE bit.
typedef esp_err_t (*esp_flash_rdsr_func_t)(esp_flash_t* chip, uint32_t* out_sr);
/**
* Use RDSR2 (35H) to read bit 15-8 of the SR, and RDSR (05H) to read bit 7-0.
*
* @param chip Pointer to SPI flash chip to use.
* @param out_sr Pointer to buffer to hold the status register, 16 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr);
/**
* Use RDSR2 (35H) to read bit 15-8 of the SR.
*
* @param chip Pointer to SPI flash chip to use.
* @param out_sr Pointer to buffer to hold the status register, 8 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr);
/**
* Use RDSR (05H) to read bit 7-0 of the SR.
*
* @param chip Pointer to SPI flash chip to use.
* @param out_sr Pointer to buffer to hold the status register, 8 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr);
/// Function pointer type for writing status register with QE bit.
typedef esp_err_t (*esp_flash_wrsr_func_t)(esp_flash_t* chip, uint32_t sr);
/**
* Use WRSR (01H) to write bit 7-0 of the SR.
*
* @param chip Pointer to SPI flash chip to use.
* @param sr Value of the status register to write, 8 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr);
/**
* Use WRSR (01H) to write bit 15-0 of the SR.
*
* @param chip Pointer to SPI flash chip to use.
* @param sr Value of the status register to write, 16 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr);
/**
* Use WRSR2 (31H) to write bit 15-8 of the SR.
*
* @param chip Pointer to SPI flash chip to use.
* @param sr Value of the status register to write, 8 bits.
*
* @return ESP_OK if success, otherwise error code passed from the
* `common_command` function of the host driver.
*/
esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr);
/**
* @brief Utility function for set_read_mode chip_drv function. If required,
* set and check the QE bit in the flash chip to enable the QIO/QOUT mode.
@ -253,16 +339,19 @@ esp_err_t spi_flash_generic_wait_host_idle(esp_flash_t *chip, uint32_t *timeout_
*
* Registers to actually do Quad transtions and command to be sent in reading
* should also be configured via
* spi_flash_chip_generic_config_host_read_mode().
* spi_flash_chip_generic_config_host_io_mode().
*
* @param qe_rdsr_command SPI flash command to read status register
* @param qe_wrsr_command SPI flash command to write status register
* @param qe_sr_bitwidth Width of the status register these commands operate on, in bits.
* @param qe_sr_bit Bit mask for enabling Quad Enable functions on this chip.
* Note that the bit length and qe position of wrsr_func, rdsr_func and
* qe_sr_bit should be consistent.
*
* @param chip Pointer to SPI flash chip to use.
* @param wrsr_func Function pointer for writing the status register
* @param rdsr_func Function pointer for reading the status register
* @param qe_sr_bit status with the qe bit only.
*
* @return always ESP_OK (currently).
*/
esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, unsigned qe_sr_bit);
esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit);
/**
* @brief Configure the host registers to use the specified read mode set in
@ -278,17 +367,4 @@ esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_comm
* - ESP_ERR_FLASH_NOT_INITIALISED if chip not initialized properly
* - or other error passed from the ``configure_host_mode`` function of host driver
*/
esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip);
/**
* @brief Returns true if chip is configured for Quad I/O or Quad Fast Read.
*
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
*
* @return true if flash works in quad mode, otherwise false
*/
static inline bool spi_flash_is_quad_mode(const esp_flash_t *chip)
{
return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
}
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip);

1
components/spi_flash/linker.lf
View File

@ -4,5 +4,6 @@ entries:
spi_flash_rom_patch (noflash_text)
spi_flash_chip_generic (noflash)
spi_flash_chip_issi (noflash)
spi_flash_chip_gd(noflash)
memspi_host_driver (noflash)

4
components/spi_flash/memspi_host_driver.c
View File

@ -38,7 +38,7 @@ esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_d
return ESP_OK;
}
esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *chip_drv, uint32_t *id)
esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *host, uint32_t *id)
{
//NOTE: we do have a read id function, however it doesn't work in high freq
spi_flash_trans_t t = {
@ -47,7 +47,7 @@ esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *chip_drv, uint32_t *id
.mosi_len = 0,
.miso_len = 24
};
chip_drv->common_command(chip_drv, &t);
host->common_command(host, &t);
uint32_t raw_flash_id = t.miso_data[0];
ESP_EARLY_LOGV(TAG, "raw_chip_id: %X\n", raw_flash_id);
if (raw_flash_id == 0xFFFFFF || raw_flash_id == 0) {

4
components/spi_flash/spi_flash_chip_drivers.c
View File

@ -16,6 +16,7 @@
#include "spi_flash_chip_driver.h"
#include "spi_flash_chip_generic.h"
#include "spi_flash_chip_issi.h"
#include "spi_flash_chip_gd.h"
#include "sdkconfig.h"
/*
@ -30,6 +31,9 @@
static const spi_flash_chip_t *default_registered_chips[] = {
#ifdef CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP
&esp_flash_chip_issi,
#endif
#ifdef CONFIG_SPI_FLASH_SUPPORT_GD_CHIP
&esp_flash_chip_gd,
#endif
&esp_flash_chip_generic,
NULL,

108
components/spi_flash/spi_flash_chip_gd.c Normal file
View File

@ -0,0 +1,108 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdlib.h>
#include "spi_flash_chip_generic.h"
#include "spi_flash_defs.h"
#define FLASH_ID_MASK 0xFF00
#define FLASH_SIZE_MASK 0xFF
#define GD25Q_PRODUCT_ID 0x4000
#define GD25LQ_PRODUCT_ID 0x6000
#define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
((chip_id) & FLASH_SIZE_MASK) <= 0x15)
/* Driver for GD flash chip */
esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
{
/* Check manufacturer and product IDs match our desired masks */
const uint8_t MFG_ID = 0xC8;
if (flash_id >> 16 != MFG_ID) {
return ESP_ERR_NOT_FOUND;
}
uint32_t product_id = flash_id & FLASH_ID_MASK;
if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
return ESP_ERR_NOT_FOUND;
}
return ESP_OK;
}
esp_err_t spi_flash_chip_gd_set_io_mode(esp_flash_t *chip)
{
if (WRSR_16B_REQUIRED(chip->chip_id)) {
const uint32_t qe = 1<<9;
return spi_flash_common_set_io_mode(chip,
spi_flash_common_write_status_16b_wrsr,
spi_flash_common_read_status_16b_rdsr_rdsr2,
qe);
} else {
const uint32_t qe = 1<<1;
return spi_flash_common_set_io_mode(chip,
spi_flash_common_write_status_8b_wrsr2,
spi_flash_common_read_status_8b_rdsr2,
qe);
}
}
esp_err_t spi_flash_chip_gd_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
{
/* GD uses bit 1 of SR2 as Quad Enable */
const uint8_t BIT_QE = 1 << 1;
uint32_t sr;
esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
if (ret == ESP_OK) {
*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
}
return ret;
}
static const char chip_name[] = "gd";
// The issi chip can use the functions for generic chips except from set read mode and probe,
// So we only replace these two functions.
const spi_flash_chip_t esp_flash_chip_gd = {
.name = chip_name,
.probe = spi_flash_chip_gd_probe,
.reset = spi_flash_chip_generic_reset,
.detect_size = spi_flash_chip_generic_detect_size,
.erase_chip = spi_flash_chip_generic_erase_chip,
.erase_sector = spi_flash_chip_generic_erase_sector,
.erase_block = spi_flash_chip_generic_erase_block,
.sector_size = 4 * 1024,
.block_erase_size = 64 * 1024,
.get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
.set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
// TODO support protected regions on ISSI flash
.num_protectable_regions = 0,
.protectable_regions = NULL,
.get_protected_regions = NULL,
.set_protected_regions = NULL,
.read = spi_flash_chip_generic_read,
.write = spi_flash_chip_generic_write,
.program_page = spi_flash_chip_generic_page_program,
.page_size = 256,
.write_encrypted = spi_flash_chip_generic_write_encrypted,
.wait_idle = spi_flash_chip_generic_wait_idle,
.set_io_mode = spi_flash_chip_gd_set_io_mode,
.get_io_mode = spi_flash_chip_gd_get_io_mode,
};

210
components/spi_flash/spi_flash_chip_generic.c
View File

@ -60,12 +60,8 @@ esp_err_t spi_flash_chip_generic_reset(esp_flash_t *chip)
esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size)
{
uint32_t id = 0;
uint32_t id = chip->chip_id;
*size = 0;
esp_err_t err = chip->host->read_id(chip->host, &id);
if (err != ESP_OK) {
return err;
}
/* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
* 0xC0 or similar. */
@ -144,7 +140,7 @@ esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t
{
esp_err_t err = ESP_OK;
// Configure the host, and return
spi_flash_chip_generic_config_host_read_mode(chip);
spi_flash_chip_generic_config_host_io_mode(chip);
while (err == ESP_OK && length > 0) {
uint32_t read_len = MIN(length, chip->host->max_read_bytes);
@ -277,7 +273,7 @@ esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_m
return (timeout_ms > 0) ? ESP_OK : ESP_ERR_TIMEOUT;
}
esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip)
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip)
{
uint32_t dummy_cyclelen_base;
uint32_t addr_bitlen;
@ -320,62 +316,33 @@ esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip)
return ESP_ERR_FLASH_NOT_INITIALISED;
}
return chip->host->configure_host_read_mode(chip->host, chip->read_mode, addr_bitlen, dummy_cyclelen_base, read_command);
return chip->host->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base,
chip->read_mode);
}
esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, unsigned qe_sr_bit)
{
if (spi_flash_is_quad_mode(chip)) {
// Ensure quad modes are enabled, using the Quad Enable parameters supplied.
spi_flash_trans_t t = {
.command = qe_rdsr_command,
.mosi_data = 0,
.mosi_len = 0,
.miso_len = qe_sr_bitwidth,
};
chip->host->common_command(chip->host, &t);
unsigned sr = t.miso_data[0];
ESP_EARLY_LOGV(TAG, "set_read_mode: status before 0x%x", sr);
if ((sr & qe_sr_bit) == 0) {
//some chips needs the write protect to be disabled before writing to Status Register
chip->chip_drv->set_chip_write_protect(chip, false);
sr |= qe_sr_bit;
spi_flash_trans_t t = {
.command = qe_wrsr_command,
.mosi_data = sr,
.mosi_len = qe_sr_bitwidth,
.miso_len = 0,
};
chip->host->common_command(chip->host, &t);
/* Check the new QE bit has stayed set */
spi_flash_trans_t t_rdsr = {
.command = qe_rdsr_command,
.mosi_data = 0,
.mosi_len = 0,
.miso_len = qe_sr_bitwidth
};
chip->host->common_command(chip->host, &t_rdsr);
sr = t_rdsr.miso_data[0];
ESP_EARLY_LOGV(TAG, "set_read_mode: status after 0x%x", sr);
if ((sr & qe_sr_bit) == 0) {
return ESP_ERR_FLASH_NO_RESPONSE;
}
chip->chip_drv->set_chip_write_protect(chip, true);
}
}
return ESP_OK;
}
esp_err_t spi_flash_chip_generic_set_read_mode(esp_flash_t *chip)
esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
{
// On "generic" chips, this involves checking
// bit 1 (QE) of RDSR2 (35h) result
// (it works this way on GigaDevice & Fudan Micro chips, probably others...)
const uint8_t BIT_QE = 1 << 1;
return spi_flash_common_set_read_mode(chip, CMD_RDSR2, CMD_WRSR2, 8, BIT_QE);
uint32_t sr;
esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
if (ret == ESP_OK) {
*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
}
return ret;
}
esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip)
{
// On "generic" chips, this involves checking
// bit 9 (QE) of RDSR (05h) result
const uint32_t BIT_QE = 1 << 9;
return spi_flash_common_set_io_mode(chip,
spi_flash_common_write_status_16b_wrsr,
spi_flash_common_read_status_16b_rdsr_rdsr2,
BIT_QE);
}
static const char chip_name[] = "generic";
@ -409,5 +376,134 @@ const spi_flash_chip_t esp_flash_chip_generic = {
.write_encrypted = spi_flash_chip_generic_write_encrypted,
.wait_idle = spi_flash_chip_generic_wait_idle,
.set_read_mode = spi_flash_chip_generic_set_read_mode,
.set_io_mode = spi_flash_chip_generic_set_io_mode,
.get_io_mode = spi_flash_chip_generic_get_io_mode,
};
/*******************************************************************************
* Utility functions
******************************************************************************/
static esp_err_t spi_flash_common_read_qe_sr(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_sr_bitwidth, uint32_t *sr)
{
spi_flash_trans_t t = {
.command = qe_rdsr_command,
.mosi_data = 0,
.mosi_len = 0,
.miso_len = qe_sr_bitwidth,
};
esp_err_t ret = chip->host->common_command(chip->host, &t);
*sr = t.miso_data[0];
return ret;
}
static esp_err_t spi_flash_common_write_qe_sr(esp_flash_t *chip, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, uint32_t qe)
{
spi_flash_trans_t t = {
.command = qe_wrsr_command,
.mosi_data = qe,
.mosi_len = qe_sr_bitwidth,
.miso_len = 0,
};
return chip->host->common_command(chip->host, &t);
}
esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
{
uint32_t sr, sr2;
esp_err_t ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, &sr2);
if (ret == ESP_OK) {
ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, &sr);
}
if (ret == ESP_OK) {
*out_sr = (sr & 0xff) | ((sr2 & 0xff) << 8);
}
return ret;
}
esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
{
return spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, out_sr);
}
esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr)
{
return spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, out_sr);
}
esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr)
{
return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 16, sr);
}
esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr)
{
return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 8, sr);
}
esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr)
{
return spi_flash_common_write_qe_sr(chip, CMD_WRSR2, 8, sr);
}
esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit)
{
esp_err_t ret = ESP_OK;
const bool is_quad_mode = esp_flash_is_quad_mode(chip);
bool update_config = false;
const bool force_check = true; //in case some chips doesn't support erase QE
bool need_check = is_quad_mode;
if (force_check) {
need_check = true;
}
uint32_t sr_update;
if (need_check) {
// Ensure quad modes are enabled, using the Quad Enable parameters supplied.
uint32_t sr;
ret = (*rdsr_func)(chip, &sr);
if (ret != ESP_OK) {
return ret;
}
ESP_EARLY_LOGD(TAG, "set_io_mode: status before 0x%x", sr);
if (is_quad_mode) {
sr_update = sr | qe_sr_bit;
} else {
sr_update = sr & (~qe_sr_bit);
}
ESP_EARLY_LOGV(TAG, "set_io_mode: status update 0x%x", sr_update);
if (sr != sr_update) {
update_config = true;
}
}
if (update_config) {
//some chips needs the write protect to be disabled before writing to Status Register
chip->chip_drv->set_chip_write_protect(chip, false);
ret = (*wrsr_func)(chip, sr_update);
if (ret != ESP_OK) {
return ret;
}
ret = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
if (ret != ESP_OK) {
return ret;
}
/* Check the new QE bit has stayed set */
uint32_t sr;
ret = (*rdsr_func)(chip, &sr);
if (ret != ESP_OK) {
return ret;
}
ESP_EARLY_LOGD(TAG, "set_io_mode: status after 0x%x", sr);
if (sr != sr_update) {
ret = ESP_ERR_FLASH_NO_RESPONSE;
}
chip->chip_drv->set_chip_write_protect(chip, true);
}
return ret;
}

23
components/spi_flash/spi_flash_chip_issi.c
View File

@ -35,13 +35,29 @@ esp_err_t spi_flash_chip_issi_probe(esp_flash_t *chip, uint32_t flash_id)
return ESP_OK;
}
esp_err_t spi_flash_chip_issi_set_read_mode(esp_flash_t *chip)
esp_err_t spi_flash_chip_issi_set_io_mode(esp_flash_t *chip)
{
/* ISSI uses bit 6 of "basic" SR as Quad Enable */
const uint8_t BIT_QE = 1 << 6;
return spi_flash_common_set_read_mode(chip, CMD_RDSR, CMD_WRSR, 8, BIT_QE);
return spi_flash_common_set_io_mode(chip,
spi_flash_common_write_status_8b_wrsr,
spi_flash_common_read_status_8b_rdsr,
BIT_QE);
}
esp_err_t spi_flash_chip_issi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
{
/* ISSI uses bit 6 of "basic" SR as Quad Enable */
const uint8_t BIT_QE = 1 << 6;
uint32_t sr;
esp_err_t ret = spi_flash_common_read_status_8b_rdsr(chip, &sr);
if (ret == ESP_OK) {
*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
}
return ret;
}
static const char chip_name[] = "issi";
// The issi chip can use the functions for generic chips except from set read mode and probe,
@ -73,5 +89,6 @@ const spi_flash_chip_t esp_flash_chip_issi = {
.write_encrypted = spi_flash_chip_generic_write_encrypted,
.wait_idle = spi_flash_chip_generic_wait_idle,
.set_read_mode = spi_flash_chip_issi_set_read_mode,
.set_io_mode = spi_flash_chip_issi_set_io_mode,
.get_io_mode = spi_flash_chip_issi_get_io_mode,
};

6
components/spi_flash/test/CMakeLists.txt
View File

@ -4,4 +4,8 @@ if(IDF_TARGET STREQUAL "esp32")
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS "."
REQUIRES unity test_utils spi_flash bootloader_support app_update)
REQUIRES unity test_utils spi_flash bootloader_support app_update)
if(CONFIG_SPI_FLASH_USE_LEGACY_IMPL)
set(COMPONENT_SRCEXCLUDE "test_esp_flash.c" "test_partition_ext.c")
endif()

4
components/spi_flash/test/component.mk
View File

@ -4,3 +4,7 @@
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
ifdef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
COMPONENT_OBJEXCLUDE += test_esp_flash.o test_partition_ext.o
endif

359
components/spi_flash/test/esp32/test_esp_flash.c
View File

@ -16,19 +16,18 @@
#include "unity.h"
#include "driver/gpio.h"
#include "soc/io_mux_reg.h"
#include "sdkconfig.h"
#define FUNC_SPI 1
static uint8_t sector_buf[4096];
// #define TEST_SPI1_CS1
// #define TEST_SPI2_CS0
// #define TEST_SPI3_CS0
#define TEST_SPI_SPEED ESP_FLASH_10MHZ
#define TEST_SPI_READ_MODE SPI_FLASH_FASTRD
//#define FORCE_GPIO_MATRIX
#define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk
#define HSPI_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define HSPI_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define HSPI_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
@ -41,40 +40,56 @@ static uint8_t sector_buf[4096];
#define VSPI_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
#define VSPI_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#if defined TEST_SPI1_CS1
# define TEST_HOST SPI_HOST
# define TEST_CS 1
// #define TEST_CS_PIN 14
# define TEST_CS_PIN 16 //the pin which is usually used by the PSRAM
// #define TEST_CS_PIN 27
# define TEST_INPUT_DELAY 0
# define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk
#elif defined TEST_SPI2_CS0
# define TEST_HOST HSPI_HOST
# define TEST_CS 0
# define TEST_CS_PIN HSPI_IOMUX_PIN_NUM_CS
# define TEST_INPUT_DELAY 20
#elif defined TEST_SPI3_CS0
# define TEST_HOST VSPI_HOST
# define TEST_CS 0
# define TEST_CS_PIN VSPI_IOMUX_PIN_NUM_CS
# define TEST_INPUT_DELAY 0
#define ALL_TEST_NUM (sizeof(config_list)/sizeof(flashtest_config_t))
typedef void (*flash_test_func_t)(esp_flash_t* chip);
#define FLASH_TEST_CASE(STR, FUNC_TO_RUN) \
TEST_CASE(STR, "[esp_flash]") {flash_test_func(FUNC_TO_RUN, 1);}
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
// These tests needs external flash, right on the place of psram
#define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN)
#else
# define SKIP_EXTENDED_CHIP_TEST
#define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \
TEST_CASE(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, ALL_TEST_NUM);}
#endif
//currently all the configs are the same with esp_flash_spi_device_config_t, no more information required
typedef esp_flash_spi_device_config_t flashtest_config_t;
static const char TAG[] = "test_esp_flash";
#ifndef SKIP_EXTENDED_CHIP_TEST
static esp_flash_t *test_chip = NULL;
flashtest_config_t config_list[] = {
// 0 always reserved for main flash
{
.host_id = -1, // no need to init
},
{
.io_mode = TEST_SPI_READ_MODE,
.speed = TEST_SPI_SPEED,
.host_id = SPI_HOST,
.cs_id = 1,
.cs_io_num = 16, //the pin which is usually used by the PSRAM
.input_delay_ns = 0,
},
/* current runner doesn't have a flash on HSPI
{
.io_mode = TEST_SPI_READ_MODE,
.speed = TEST_SPI_SPEED,
.host = HSPI_HOST,
.cs_id = 0,
.cs_io_num = HSPI_IOMUX_PIN_NUM_CS,
.input_delay_ns = 20,
},
*/
{
.io_mode = TEST_SPI_READ_MODE,
.speed = TEST_SPI_SPEED,
.host_id = VSPI_HOST,
.cs_id = 0,
.cs_io_num = VSPI_IOMUX_PIN_NUM_CS,
.input_delay_ns = 0,
},
};
static void setup_bus(spi_host_device_t host_id)
{
@ -127,33 +142,50 @@ static void release_bus(int host_id)
}
}
static void setup_new_chip(esp_flash_read_mode_t io_mode, esp_flash_speed_t speed)
static void setup_new_chip(const flashtest_config_t* test_cfg, esp_flash_t** out_chip)
{
//the bus should be initialized before the flash is attached to the bus
setup_bus(TEST_HOST);
if (test_cfg->host_id == -1) {
*out_chip = NULL;
return;
}
setup_bus(test_cfg->host_id);
esp_flash_spi_device_config_t dev_cfg = {
.host_id = TEST_HOST,
.io_mode = io_mode,
.speed = speed,
.cs_id = TEST_CS,
.cs_io_num = TEST_CS_PIN,
.input_delay_ns = TEST_INPUT_DELAY,
.host_id = test_cfg->host_id,
.io_mode = test_cfg->io_mode,
.speed = test_cfg->speed,
.cs_id = test_cfg->cs_id,
.cs_io_num = test_cfg->cs_io_num,
.input_delay_ns = test_cfg->input_delay_ns,
};
esp_err_t err = spi_bus_add_flash_device(&test_chip, &dev_cfg);
esp_flash_t* init_chip;
esp_err_t err = spi_bus_add_flash_device(&init_chip, &dev_cfg);
TEST_ESP_OK(err);
err = esp_flash_init(test_chip);
err = esp_flash_init(init_chip);
TEST_ESP_OK(err);
*out_chip = init_chip;
}
void teardown_test_chip(void)
void teardown_test_chip(esp_flash_t* chip, spi_host_device_t host)
{
spi_bus_remove_flash_device(test_chip);
test_chip = NULL;
release_bus(TEST_HOST);
//happen to work when chip==NULL
spi_bus_remove_flash_device(chip);
release_bus(host);
}
#endif
static void flash_test_func(flash_test_func_t func, int test_num)
{
for (int i = 0; i < test_num; i++) {
flashtest_config_t* config = &config_list[i];
esp_flash_t* chip;
setup_new_chip(config, &chip);
(*func)(chip);
teardown_test_chip(chip, config->host_id);
}
}
/* ---------- Test code start ------------*/
static void test_metadata(esp_flash_t *chip)
{
@ -164,15 +196,8 @@ static void test_metadata(esp_flash_t *chip)
printf("Flash ID %08x detected size %d bytes\n", id, size);
}
TEST_CASE("SPI flash metadata functions", "[esp_flash]")
{
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_metadata(test_chip);
teardown_test_chip();
#endif
test_metadata(NULL);
}
FLASH_TEST_CASE("SPI flash metadata functions", test_metadata);
FLASH_TEST_CASE_3("SPI flash metadata functions", test_metadata);
static uint32_t erase_test_region(esp_flash_t *chip, int num_sectors)
{
@ -203,7 +228,7 @@ static uint32_t erase_test_region(esp_flash_t *chip, int num_sectors)
return offs;
}
void test_simple_read_write(void *chip)
void test_simple_read_write(esp_flash_t *chip)
{
ESP_LOGI(TAG, "Testing chip %p...", chip);
uint32_t offs = erase_test_region(chip, 1);
@ -230,17 +255,10 @@ void test_simple_read_write(void *chip)
}
}
TEST_CASE("SPI flash simple read/write", "[esp_flash]")
{
test_simple_read_write(NULL);
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_simple_read_write(test_chip);
teardown_test_chip();
#endif
}
FLASH_TEST_CASE("SPI flash simple read/write", test_simple_read_write);
FLASH_TEST_CASE_3("SPI flash simple read/write", test_simple_read_write);
void test_unaligned_read_write(void *chip)
void test_unaligned_read_write(esp_flash_t *chip)
{
ESP_LOGI(TAG, "Testing chip %p...", chip);
uint32_t offs = erase_test_region(chip, 2);
@ -258,17 +276,10 @@ void test_unaligned_read_write(void *chip)
TEST_ASSERT(memcmp(buf, msg, strlen(msg) + 1) == 0);
}
TEST_CASE("SPI flash unaligned read/write", "[esp_flash]")
{
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_unaligned_read_write(test_chip);
teardown_test_chip();
#endif
test_unaligned_read_write(NULL);
}
FLASH_TEST_CASE("SPI flash unaligned read/write", test_unaligned_read_write);
FLASH_TEST_CASE_3("SPI flash unaligned read/write", test_unaligned_read_write);
void test_single_read_write(void *chip)
void test_single_read_write(esp_flash_t* chip)
{
ESP_LOGI(TAG, "Testing chip %p...", chip);
uint32_t offs = erase_test_region(chip, 2);
@ -284,21 +295,14 @@ void test_single_read_write(void *chip)
}
}
TEST_CASE("SPI flash single byte reads/writes", "[esp_flash]")
{
test_single_read_write(NULL);
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_single_read_write(test_chip);
teardown_test_chip();
#endif
}
FLASH_TEST_CASE("SPI flash single byte reads/writes", test_single_read_write);
FLASH_TEST_CASE_3("SPI flash single byte reads/writes", test_single_read_write);
/* this test is notable because it generates a lot of unaligned reads/writes,
and also reads/writes across both a sector boundary & many page boundaries.
*/
void test_three_byte_read_write(void *chip)
void test_three_byte_read_write(esp_flash_t *chip)
{
ESP_LOGI(TAG, "Testing chip %p...", chip);
uint32_t offs = erase_test_region(chip, 2);
@ -315,15 +319,8 @@ void test_three_byte_read_write(void *chip)
}
}
TEST_CASE("SPI flash three byte reads/writes", "[esp_flash]")
{
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_three_byte_read_write(test_chip);
teardown_test_chip();
#endif
test_three_byte_read_write(NULL);
}
FLASH_TEST_CASE("SPI flash three byte reads/writes", test_three_byte_read_write);
FLASH_TEST_CASE_3("SPI flash three byte reads/writes", test_three_byte_read_write);
void test_erase_large_region(esp_flash_t *chip)
{
@ -355,15 +352,8 @@ void test_erase_large_region(esp_flash_t *chip)
TEST_ASSERT_EQUAL_HEX32(0xFFFFFFFF, readback);
}
TEST_CASE("SPI flash erase large region", "[esp_flash]")
{
test_erase_large_region(NULL);
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_erase_large_region(test_chip);
teardown_test_chip();
#endif
}
FLASH_TEST_CASE("SPI flash erase large region", test_erase_large_region);
FLASH_TEST_CASE_3("SPI flash erase large region", test_erase_large_region);
static void test_write_protection(esp_flash_t* chip)
{
@ -385,15 +375,8 @@ static void test_write_protection(esp_flash_t* chip)
}
}
TEST_CASE("Test esp_flash can enable/disable write protetion", "[esp_flash]")
{
test_write_protection(NULL);
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_write_protection(test_chip);
teardown_test_chip();
#endif
}
FLASH_TEST_CASE("Test esp_flash can enable/disable write protetion", test_write_protection);
FLASH_TEST_CASE_3("Test esp_flash can enable/disable write protetion", test_write_protection);
static const uint8_t large_const_buffer[16400] = {
203, // first byte
@ -410,8 +393,73 @@ static void test_write_large_buffer(esp_flash_t *chip, const uint8_t *source, si
static void write_large_buffer(esp_flash_t *chip, const esp_partition_t *part, const uint8_t *source, size_t length);
static void read_and_check(esp_flash_t *chip, const esp_partition_t *part, const uint8_t *source, size_t length);
TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash]")
// Internal functions for testing, from esp_flash_api.c
esp_err_t esp_flash_set_io_mode(esp_flash_t* chip, bool qe);
esp_err_t esp_flash_get_io_mode(esp_flash_t* chip, bool* qe);
esp_err_t esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id);
static bool check_winbond_chip(esp_flash_t* chip)
{
uint32_t flash_id;
esp_err_t ret = esp_flash_read_chip_id(chip, &flash_id);
TEST_ESP_OK(ret);
if ((flash_id >> 16) == 0xEF) {
return true;
} else {
return false;
}
}
static void test_toggle_qe(esp_flash_t* chip)
{
bool qe;
if (chip == NULL) {
chip = esp_flash_default_chip;
}
esp_flash_io_mode_t io_mode_before = chip->read_mode;
esp_err_t ret = esp_flash_get_io_mode(chip, &qe);
TEST_ESP_OK(ret);
bool is_winbond_chip = check_winbond_chip(chip);
for (int i = 0; i < 4; i ++) {
ESP_LOGI(TAG, "write qe: %d->%d", qe, !qe);
qe = !qe;
chip->read_mode = qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD;
ret = esp_flash_set_io_mode(chip, qe);
if (is_winbond_chip && !qe && ret == ESP_ERR_FLASH_NO_RESPONSE) {
//allows clear qe failure for Winbond chips
ret = ESP_OK;
}
TEST_ESP_OK(ret);
bool qe_read;
ret = esp_flash_get_io_mode(chip, &qe_read);
TEST_ESP_OK(ret);
ESP_LOGD(TAG, "qe read: %d", qe_read);
if (qe != qe_read && !qe && is_winbond_chip) {
ESP_LOGE(TAG, "cannot clear QE bit, this may be normal for Winbond chips.");
chip->read_mode = io_mode_before;
return;
}
TEST_ASSERT_EQUAL(qe, qe_read);
}
//restore the io_mode after test
chip->read_mode = io_mode_before;
}
FLASH_TEST_CASE("Test esp_flash_write can toggle QE bit", test_toggle_qe);
FLASH_TEST_CASE_3("Test esp_flash_write can toggle QE bit", test_toggle_qe);
void test_permutations(flashtest_config_t* config)
{
//replace config pointer with pointer to internal temporary config
flashtest_config_t temp_cfg;
memcpy(&temp_cfg, config, sizeof(flashtest_config_t));
flashtest_config_t* cfg = &temp_cfg;
esp_flash_t* chip;
const int length = sizeof(large_const_buffer);
uint8_t *source_buf = malloc(length);
TEST_ASSERT_NOT_NULL(source_buf);
@ -423,60 +471,75 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash
const esp_partition_t *part = get_test_data_partition();
TEST_ASSERT(part->size > length + 2 + SPI_FLASH_SEC_SIZE);
#ifndef SKIP_EXTENDED_CHIP_TEST
//use the lowest speed to write and read to make sure success
setup_new_chip(TEST_SPI_READ_MODE, ESP_FLASH_SPEED_MIN);
write_large_buffer(test_chip, part, source_buf, length);
read_and_check(test_chip, part, source_buf, length);
teardown_test_chip();
//write data to be read, and use the lowest speed to write and read to make sure success
cfg->io_mode = SPI_FLASH_READ_MODE_MIN;
cfg->speed = ESP_FLASH_SPEED_MIN;
setup_new_chip(cfg, &chip);
write_large_buffer(chip, part, source_buf, length);
read_and_check(chip, part, source_buf, length);
teardown_test_chip(chip, cfg->host_id);
esp_flash_read_mode_t io_mode = SPI_FLASH_READ_MODE_MIN;
while (io_mode != SPI_FLASH_READ_MODE_MAX) {
if (config->host_id != -1) {
esp_flash_speed_t speed = ESP_FLASH_SPEED_MIN;
while (speed != ESP_FLASH_SPEED_MAX) {
ESP_LOGI(TAG, "test flash io mode: %d, speed: %d", io_mode, speed);
setup_new_chip(io_mode, speed);
read_and_check(test_chip, part, source_buf, length);
teardown_test_chip();
//test io_mode in the inner loop to test QE set/clear function, since
//the io mode will switch frequently.
esp_flash_io_mode_t io_mode = SPI_FLASH_READ_MODE_MIN;
while (io_mode != SPI_FLASH_READ_MODE_MAX) {
ESP_LOGI(TAG, "test flash io mode: %d, speed: %d", io_mode, speed);
cfg->io_mode = io_mode;
cfg->speed = speed;
setup_new_chip(cfg, &chip);
read_and_check(chip, part, source_buf, length);
teardown_test_chip(chip, cfg->host_id);
io_mode++;
}
speed++;
}
io_mode++;
} else {
//test main flash
write_large_buffer(NULL, part, source_buf, length);
read_and_check(NULL, part, source_buf, length);
}
#endif
//test main flash BTW
write_large_buffer(NULL, part, source_buf, length);
read_and_check(NULL, part, source_buf, length);
free(source_buf);
}
TEST_CASE("Test esp_flash_write large const buffer", "[esp_flash]")
TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash]")
{
//buffer in flash
test_write_large_buffer(NULL, large_const_buffer, sizeof(large_const_buffer));
#ifndef SKIP_EXTENDED_CHIP_TEST
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_write_large_buffer(test_chip, large_const_buffer, sizeof(large_const_buffer));
teardown_test_chip();
#endif
test_permutations(&config_list[0]);
}
#ifndef SKIP_EXTENDED_CHIP_TEST
TEST_CASE("Test esp_flash_write large RAM buffer", "[esp_flash]")
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]")
{
for (int i = 0; i < ALL_TEST_NUM; i++) {
test_permutations(&config_list[i]);
}
}
#endif
static void test_write_large_const_buffer(esp_flash_t* chip)
{
test_write_large_buffer(chip, large_const_buffer, sizeof(large_const_buffer));
}
FLASH_TEST_CASE("Test esp_flash_write large const buffer", test_write_large_const_buffer);
FLASH_TEST_CASE_3("Test esp_flash_write large const buffer", test_write_large_const_buffer);
static void test_write_large_ram_buffer(esp_flash_t* chip)
{
// buffer in RAM
uint8_t *source_buf = malloc(sizeof(large_const_buffer));
TEST_ASSERT_NOT_NULL(source_buf);
memcpy(source_buf, large_const_buffer, sizeof(large_const_buffer));
setup_new_chip(TEST_SPI_READ_MODE, TEST_SPI_SPEED);
test_write_large_buffer(test_chip, source_buf, sizeof(large_const_buffer));
teardown_test_chip();
test_write_large_buffer(chip, source_buf, sizeof(large_const_buffer));
free(source_buf);
}
#endif
FLASH_TEST_CASE("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer);
FLASH_TEST_CASE_3("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer);
static void write_large_buffer(esp_flash_t *chip, const esp_partition_t *part, const uint8_t *source, size_t length)
{

34
components/spi_flash/test/test_read_write.c
View File

@ -28,6 +28,7 @@
#include "soc/timer_periph.h"
#include "esp_heap_caps.h"
#define MIN_BLOCK_SIZE 12
/* Base offset in flash for tests. */
static size_t start;
@ -285,4 +286,37 @@ TEST_CASE("spi_flash_write can write from external RAM buffer", "[spi_flash]")
free(buf_int);
}
TEST_CASE("spi_flash_read less than 16 bytes into buffer in external RAM", "[spi_flash]")
{
uint8_t *buf_ext_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(buf_ext_8);
uint8_t *buf_int_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(buf_int_8);
uint8_t data_8[MIN_BLOCK_SIZE];
for (int i = 0; i < MIN_BLOCK_SIZE; i++) {
data_8[i] = i;
}
const esp_partition_t *part = get_test_data_partition();
TEST_ESP_OK(spi_flash_erase_range(part->address, SPI_FLASH_SEC_SIZE));
TEST_ESP_OK(spi_flash_write(part->address, data_8, MIN_BLOCK_SIZE));
TEST_ESP_OK(spi_flash_read(part->address, buf_ext_8, MIN_BLOCK_SIZE));
TEST_ESP_OK(spi_flash_read(part->address, buf_int_8, MIN_BLOCK_SIZE));
TEST_ASSERT_EQUAL(0, memcmp(buf_ext_8, data_8, MIN_BLOCK_SIZE));
TEST_ASSERT_EQUAL(0, memcmp(buf_int_8, data_8, MIN_BLOCK_SIZE));
if (buf_ext_8) {
free(buf_ext_8);
buf_ext_8 = NULL;
}
if (buf_int_8) {
free(buf_int_8);
buf_int_8 = NULL;
}
}
#endif // CONFIG_SPIRAM

7
components/spiffs/Kconfig
View File

@ -76,6 +76,13 @@ menu "SPIFFS Configuration"
SPIFFS_OBJ_NAME_LEN + SPIFFS_META_LENGTH should not exceed
SPIFFS_PAGE_SIZE - 64.
config SPIFFS_FOLLOW_SYMLINKS
bool "Enable symbolic links for image creation"
default "n"
help
If this option is enabled, symbolic links are taken into account
during partition image creation.
config SPIFFS_USE_MAGIC
bool "Enable SPIFFS Filesystem Magic"
default "y"

9
components/spiffs/Makefile.projbuild
View File

@ -13,6 +13,12 @@ else
USE_MAGIC_LEN = ""
endif
ifdef CONFIG_SPIFFS_FOLLOW_SYMLINKS
FOLLOW_SYMLINKS = "--follow-symlinks"
else
FOLLOW_SYMLINKS = ""
endif
# spiffs_create_partition_image
#
# Create a spiffs image of the specified directory on the host during build and optionally
@ -27,6 +33,7 @@ $(1)_bin: $(PARTITION_TABLE_BIN) $(SPIFFS_IMAGE_DEPENDS) | check_python_dependen
--page-size=$(CONFIG_SPIFFS_PAGE_SIZE) \
--obj-name-len=$(CONFIG_SPIFFS_OBJ_NAME_LEN) \
--meta-len=$(CONFIG_SPIFFS_META_LENGTH) \
$(FOLLOW_SYMLINKS) \
$(USE_MAGIC) \
$(USE_MAGIC_LEN)
@ -43,4 +50,4 @@ endef
ESPTOOL_ALL_FLASH_ARGS += $(foreach partition,$(SPIFFSGEN_FLASH_IN_PROJECT), \
$(shell $(GET_PART_INFO) --partition-table-file $(PARTITION_TABLE_BIN) \
get_partition_info --partition-name $(partition) --info offset) $(BUILD_DIR_BASE)/$(partition).bin)
get_partition_info --partition-name $(partition) --info offset) $(BUILD_DIR_BASE)/$(partition).bin)

7
components/spiffs/project_include.cmake
View File

@ -25,6 +25,10 @@ function(spiffs_create_partition_image partition base_dir)
set(use_magic_len "--use-magic-len")
endif()
if(CONFIG_SPIFFS_FOLLOW_SYMLINKS)
set(follow_symlinks "--follow-symlinks")
endif()
# Execute SPIFFS image generation; this always executes as there is no way to specify for CMake to watch for
# contents of the base dir changing.
add_custom_target(spiffs_${partition}_bin ALL
@ -32,6 +36,7 @@ function(spiffs_create_partition_image partition base_dir)
--page-size=${CONFIG_SPIFFS_PAGE_SIZE}
--obj-name-len=${CONFIG_SPIFFS_OBJ_NAME_LEN}
--meta-len=${CONFIG_SPIFFS_META_LENGTH}
${follow_symlinks}
${use_magic}
${use_magic_len}
DEPENDS ${arg_DEPENDS}
@ -46,4 +51,4 @@ function(spiffs_create_partition_image partition base_dir)
else()
esptool_py_flash_project_args(${partition} ${offset} ${image_file})
endif()
endfunction()
endfunction()

7
components/spiffs/spiffsgen.py
View File

@ -488,6 +488,11 @@ def main():
action="store_true",
default=True)
parser.add_argument("--follow-symlinks",
help="Take into account symbolic links during partition image creation.",
action="store_true",
default=False)
parser.add_argument("--use-magic-len",
help="Use position in memory to create different magic numbers for each block. Specify if CONFIG_SPIFFS_USE_MAGIC_LENGTH.",
action="store_true",
@ -513,7 +518,7 @@ def main():
spiffs = SpiffsFS(image_size, spiffs_build_default)
for root, dirs, files in os.walk(args.base_dir):
for root, dirs, files in os.walk(args.base_dir, followlinks=args.follow_symlinks):
for f in files:
full_path = os.path.join(root, f)
spiffs.create_file("/" + os.path.relpath(full_path, args.base_dir).replace("\\", "/"), full_path)

6
components/spiffs/test_spiffs_host/Makefile
View File

@ -87,7 +87,11 @@ $(TEST_PROGRAM): lib $(TEST_OBJ_FILES) $(SPI_FLASH_SIM_BUILD_DIR)/$(SPI_FLASH_SI
# Use spiffs source directory as the test image
spiffs_image: ../spiffs $(shell find ../spiffs -type d) $(shell find ../spiffs -type -f -name '*')
../spiffsgen.py 2097152 ../spiffs image.bin
# Creation of test symlinks unfortunately causes rerun of spiffsgen.py every make invoke
rm -f ../spiffs/include ../spiffs/CMakeLists.txt
ln -s ../include ../spiffs/include
ln -s ../CMakeLists.txt ../spiffs/CMakeLists.txt
../spiffsgen.py --follow-symlinks 2097152 ../spiffs image.bin
test: $(TEST_PROGRAM) spiffs_image
./$(TEST_PROGRAM)

25
components/spiffs/test_spiffs_host/test_spiffs.cpp
View File

@ -1,9 +1,13 @@
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <dirent.h>
#include <limits.h>
#include <unistd.h>
#include "esp_partition.h"
#include "spiffs.h"
@ -96,7 +100,18 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path
while ((entry = readdir(dir)) != NULL) {
char *name = entry->d_name;
if (entry->d_type == DT_DIR) {
char path[PATH_MAX] = { 0 };
// Read the file from host FS
strcpy(path, cur_path);
strcat(path, "/");
strcat(path, name);
struct stat sb;
stat(path, &sb);
if (S_ISDIR(sb.st_mode)) {
if (!strcmp(name, ".") || !strcmp(name, ".."))
continue;
cur_path[len] = '/';
@ -104,13 +119,6 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path
check_spiffs_files(fs, base_path, cur_path);
cur_path[len] = '\0';
} else {
char path[PATH_MAX];
// Read the file from host FS
strcpy(path, cur_path);
strcat(path, "/");
strcat(path, name);
FILE* f = fopen(path , "r");
REQUIRE(f);
fseek(f, 0, SEEK_END);
@ -126,6 +134,7 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path
// Read the file from SPIFFS
char *spiffs_path = path + strlen(base_path);
spiffs_res = SPIFFS_open(fs, spiffs_path, SPIFFS_RDONLY, 0);
REQUIRE(spiffs_res > SPIFFS_OK);
spiffs_file fd = spiffs_res;

269
docs/en/api-reference/peripherals/spi_slave.rst
View File

@ -1,84 +1,108 @@
SPI Slave driver
=================
SPI Slave Driver
================
Overview
--------
SPI Slave driver is a program that controls ESP32's SPI peripherals while they function as slaves.
The ESP32 has four SPI peripheral devices, called SPI0, SPI1, HSPI and VSPI. SPI0 is entirely dedicated to
the flash cache the ESP32 uses to map the SPI flash device it is connected to into memory. SPI1 is
connected to the same hardware lines as SPI0 and is used to write to the flash chip. HSPI and VSPI
are free to use, and with the spi_slave driver, these can be used as a SPI slave, driven from a
connected SPI master.
The spi_slave driver
^^^^^^^^^^^^^^^^^^^^^
Overview of ESP32's SPI peripherals
-----------------------------------
ESP32 integrates two general purpose SPI controllers which can be used as slave nodes driven by an off-chip SPI master
- SPI2, sometimes referred to as HSPI
- SPI3, sometimes referred to as VSPI
SPI2 and SPI3 have independent signal buses with the same respective names.
The spi_slave driver allows using the HSPI and/or VSPI peripheral as a
full-duplex SPI slave. It can send/receive transactions within 64 bytes, or
make use of DMA to send/receive transactions longer than that. However, there
are some `known issues <spi_dma_known_issues>`_ when the DMA is enabled.
Terminology
^^^^^^^^^^^
-----------
The spi_slave driver uses the following terms:
The terms used in relation to the SPI slave driver are given in the table below.
* Host: The SPI peripheral inside the ESP32 initiating the SPI transmissions. One of HSPI or VSPI.
* Bus: The SPI bus, common to all SPI devices connected to a master. In general the bus consists of the
miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
signals in parallel. Each SPI slave is also connected to one CS signal.
- miso - Also known as q, this is the output of the serial stream from the ESP32 to the SPI master
- mosi - Also known as d, this is the output of the serial stream from the SPI master to the ESP32
- sclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal
- cs - Chip Select. An active Chip Select delineates a single transaction to/from a slave.
* Transaction: One instance of CS going active, data transfer from and to a master happening, and
CS going inactive again. Transactions are atomic, as in they will never be interrupted by another
transaction.
================= =========================================================================================
Term Definition
================= =========================================================================================
**Host** The SPI controller peripheral external to ESP32 that initiates SPI transmissions over the bus, and acts as an SPI Master.
**Device** SPI slave device, in this case the SPI2 and SPI3 controllers. Each Device shares the MOSI, MISO and SCLK signals but is only active on the bus when the Host asserts the Device's individual CS line.
**Bus** A signal bus, common to all Devices connected to one Host. In general, a bus includes the following lines: MISO, MOSI, SCLK, one or more CS lines, and, optionally, QUADWP and QUADHD. So Devices are connected to the same lines, with the exception that each Device has its own CS line. Several Devices can also share one CS line if connected in the daisy-chain manner.
- **MISO** Master In, Slave Out, a.k.a. Q. Data transmission from a Device to Host.
- **MOSI** Master In, Slave Out, a.k.a. D. Data transmission from a Host to Device.
- **SCLK** Serial Clock. Oscillating signal generated by a Host that keeps the transmission of data bits in sync.
- **CS** Chip Select. Allows a Host to select individual Device(s) connected to the bus in order to send or receive data.
- **QUADWP** Write Protect signal. Only used for 4-bit (qio/qout) transactions.
- **QUADHD** Hold signal. Only used for 4-bit (qio/qout) transactions.
- **Assertion** The action of activating a line. The opposite action of returning the line back to inactive (back to idle) is called *de-assertion*.
**Transaction** One instance of a Host asserting a CS line, transferring data to and from a Device, and de-asserting the CS line. Transactions are atomic, which means they can never be interrupted by another transaction.
**Launch edge** Edge of the clock at which the source register *launches* the signal onto the line.
**Latch edge** Edge of the clock at which the destination register *latches in* the signal.
================= =========================================================================================
SPI transactions
^^^^^^^^^^^^^^^^
A full-duplex SPI transaction starts with the master pulling CS low. After this happens, the master
starts sending out clock pulses on the CLK line: every clock pulse causes a data bit to be shifted from
the master to the slave on the MOSI line and vice versa on the MISO line. At the end of the transaction,
the master makes CS high again.
Driver Features
---------------
.. note:: The SPI slave peripheral relies on the control of software very
much. The master shouldn't start a transaction when the slave hasn't prepared
for it. Using one more GPIO as the handshake signal to sync is a good idea.
For more details, see :ref:`transaction_interval`.
The SPI slave driver allows using the SPI2 and/or SPI3 peripherals as full-duplex Devices. The driver can send/receive transactions up to 64 bytes in length, or utilize DMA to send/receive longer transactions. However, there are some :ref:`known issues <spi_dma_known_issues>` related to DMA.
GPIO matrix and IOMUX
^^^^^^^^^^^^^^^^^^^^^
Most peripheral signals in ESP32 can connect directly to a specific GPIO,
which is called its IOMUX pin. When a peripheral signal is routed to a pin
other than its IOMUX pin, ESP32 uses the less direct GPIO matrix to make this
connection.
SPI Transactions
----------------
If the driver is configured with all SPI signals set to their specific IOMUX
pins (or left unconnected), it will bypass the GPIO matrix. If any SPI signal
is configured to a pin other than its IOMUx pin, the driver will
automatically route all the signals via the GPIO Matrix. The GPIO matrix
samples all signals at 80MHz and sends them between the GPIO and the
peripheral.
A full-duplex SPI transaction begins when the Host asserts the CS line and starts sending out clock pulses on the SCLK line. Every clock pulse, a data bit is shifted from the Host to the Device on the MOSI line and back on the MISO line at the same time. At the end of the transaction, the Host de-asserts the CS line.
When the GPIO matrix is used, setup time of MISO is more easily violated,
since the output delay of MISO signal is increased.
The attributes of a transaction are determined by the configuration structure for an SPI host acting as a slave device :cpp:type:`spi_slave_interface_config_t`, and transaction configuration structure :cpp:type:`spi_slave_transaction_t`.
.. note:: More details about influence of output delay on the maximum clock
frequency, see :ref:`timing_considerations` below.
As not every transaction requires both writing and reading data, you have a choice to configure the :cpp:type:`spi_transaction_t` structure for TX only, RX only, or TX and RX transactions. If :cpp:member:`spi_slave_transaction_t::rx_buffer` is set to NULL, the read phase will be skipped. If :cpp:member:`spi_slave_transaction_t::tx_buffer` is set to NULL, the write phase will be skipped.
IOMUX pins for SPI controllers are as below:
.. note::
A Host should not start a transaction before its Device is ready for receiving data. It is recommended to use another GPIO pin for a handshake signal to sync the Devices. For more details, see :ref:`transaction_interval`.
Driver Usage
------------
- Initialize an SPI peripheral as a Device by calling the function cpp:func:`spi_slave_initialize`. Make sure to set the correct I/O pins in the struct :cpp:type:`bus_config`. Set the unused signals to ``-1``. If transactions will be longer than 32 bytes, allow a DMA channel 1 or 2 by setting the parameter ``dma_chan`` to ``1`` or ``2`` respectively. Otherwise, set ``dma_chan`` to ``0``.
- Before initiating transactions, fill one or more :cpp:type:`spi_slave_transaction_t` structs with the transaction parameters required. Either queue all transactions by calling the function :cpp:func:`spi_slave_queue_trans` and, at a later time, query the result by using the function :cpp:func:`spi_slave_get_trans_result`, or handle all requests individually by feeding them into :cpp:func:`spi_slave_transmit`. The latter two functions will be blocked until the Host has initiated and finished a transaction, causing the queued data to be sent and received.
- (Optional) To unload the SPI slave driver, call :cpp:func:`spi_slave_free`.
Transaction Data and Master/Slave Length Mismatches
---------------------------------------------------
Normally, the data that needs to be transferred to or from a Device is read or written to a chunk of memory indicated by the :cpp:member:`rx_buffer` and :cpp:member:`tx_buffer` members of the :cpp:type:`spi_transaction_t` structure. The SPI driver can be configured to use DMA for transfers, in which case these buffers must be allocated in DMA-capable memory using ``pvPortMallocCaps(size, MALLOC_CAP_DMA)``.
The amount of data that the driver can read or write to the buffers is limited by the member :cpp:member:`spi_transaction_t::length`. However, this member does not define the actual length of an SPI transaction. A transaction's length is determined by a Host which drives the clock and CS lines. The actual length of the transmission can be read only after a transaction is finished from the member :cpp:member:`spi_slave_transaction_t::trans_len`.
If the length of the transmission is greater than the buffer length, only the initial number of bits specified in the :cpp:member:`length` member will be sent and received. In this case, :cpp:member:`trans_len` is set to :cpp:member:`length` instead of the actual transaction length. To meet the actual transaction length requirements, set :cpp:member:`length` to a value greater than the maximum :cpp:member:`trans_len` expected. If the transmission length is shorter than the buffer length, only the data equal to the length of the buffer will be transmitted.
.. Warning::
The ESP32 DMA hardware has a limit to the number of bytes sent by a Host and received by a Device. The transaction length must be longer than 8 bytes and a multiple of 4 bytes; otherwise, the SPI hardware might fail to receive the last 1 to 7 bytes.
GPIO Matrix and IO_MUX
----------------------
Most of ESP32's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix.
If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. The GPIO matrix samples all signals at 80 MHz and transmits them between the GPIO and the peripheral.
If the driver is configured so that all SPI signals are either routed to their dedicated IO_MUX pins or are not connected at all, the GPIO matrix will be bypassed.
The GPIO matrix introduces flexibility of routing but also increases the input delay of the MISO signal, which makes MISO setup time violations more likely. If SPI needs to operate at high speeds, use dedicated IO_MUX pins.
.. note::
For more details about the influence of the MISO input delay on the maximum clock frequency, see :ref:`timing_considerations`.
The IO_MUX pins for SPI buses are given below.
+----------+------+------+
| Pin Name | HSPI | VSPI |
| Pin Name | SPI2 | SPI3 |
+ +------+------+
| | GPIO Number |
+==========+======+======+
@ -95,139 +119,74 @@ IOMUX pins for SPI controllers are as below:
| QUADHD | 4 | 21 |
+----------+------+------+
note * Only the first device attaching to the bus can use CS0 pin.
Using the spi_slave driver
^^^^^^^^^^^^^^^^^^^^^^^^^^^
- Initialize a SPI peripheral as a slave by calling ``spi_slave_initialize``. Make sure to set the
correct IO pins in the ``bus_config`` struct. Take care to set signals that are not needed to -1.
A DMA channel (either 1 or 2) must be given if transactions will be larger than 32 bytes, if not
the dma_chan parameter may be 0.
- To set up a transaction, fill one or more spi_transaction_t structure with any transaction
parameters you need. Either queue all transactions by calling ``spi_slave_queue_trans``, later
quering the result using ``spi_slave_get_trans_result``, or handle all requests synchroneously
by feeding them into ``spi_slave_transmit``. The latter two functions will block until the
master has initiated and finished a transaction, causing the queued data to be sent and received.
- Optional: to unload the SPI slave driver, call ``spi_slave_free``.
* Only the first Device attached to the bus can use the CS0 pin.
Transaction data and master/slave length mismatches
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Normally, data to be transferred to or from a device will be read from or written to a chunk of memory
indicated by the ``rx_buffer`` and ``tx_buffer`` members of the transaction structure. The SPI driver
may decide to use DMA for transfers, so these buffers should be allocated in DMA-capable memory using
``pvPortMallocCaps(size, MALLOC_CAP_DMA)``.
The amount of data written to the buffers is limited by the ``length`` member of the transaction structure:
the driver will never read/write more data than indicated there. The ``length`` cannot define the actual
length of the SPI transaction; this is determined by the master as it drives the clock and CS lines. The actual length
transferred can be read from the ``trans_len`` member of the ``spi_slave_transaction_t`` structure after transaction.
In case the length of the transmission is larger than the buffer length, only the start of the transmission
will be sent and received, and the ``trans_len`` is set to ``length`` instead of the actual length. It's recommended to
set ``length`` longer than the maximum length expected if the ``trans_len`` is required. In case the transmission
length is shorter than the buffer length, only data up to the length of the buffer will be exchanged.
Warning: Due to a design peculiarity in the ESP32, if the amount of bytes sent by the master or the length
of the transmission queues in the slave driver, in bytes, is not both larger than eight and dividable by
four, the SPI hardware can fail to write the last one to seven bytes to the receive buffer.
Speed and Timing considerations
Speed and Timing Considerations
-------------------------------
.. _transaction_interval:
Transaction interval
Transaction Interval
^^^^^^^^^^^^^^^^^^^^
The SPI slave is designed as s general purpose device controlled by the CPU.
Different from dedicated devices, CPU-based SPI slave doesn't have too much
pre-defined registers. All transactions should be triggered by the CPU, which
means the response speed would not be real-time, and there'll always be
noticeable intervals between transfers.
The ESP32 SPI slave peripherals are designed as general purpose Devices controlled by a CPU. As opposed to dedicated slaves, CPU-based SPI Devices have a limited number of pre-defined registers. All transactions must be handled by the CPU, which means that the transfers and responses are not real-time, and there might be noticeable latency.
During the transaction intervals, the device is not prepared for
transactions, the response is not meaningful at all. It is suggested to use
:cpp:func:`spi_slave_queue_trans` with :cpp:func:`spi_slave_get_trans_result`
to shorten the interval to half the case when using
:cpp:func:`spi_slave_transmit`.
As a solution, a Device's response rate can be doubled by using the functions :cpp:func:`spi_slave_queue_trans` and then :cpp:func:`spi_slave_get_trans_result` instead of using :cpp:func:`spi_slave_transmit`.
The master should always wait for the slave to be ready to start new
transactions. Suggested way is to use a gpio by the slave to indicate whether
it's ready. The example is in :example:`peripherals/spi_slave`.
You can also configure a GPIO pin through which the Device will signal to the Host when it is ready for a new transaction. A code example of this can be found in :example:`peripherals/spi_slave`.
SCLK frequency requirement
^^^^^^^^^^^^^^^^^^^^^^^^^^
The spi slave is designed to work under 10MHz or lower. The clock and data
cannot be recognized or received correctly if the clock is too fast or
doesn't have a 50% duty cycle.
SCLK Frequency Requirements
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Moreover, there are more requirements if the data meets the timing
requirement:
The SPI slaves are designed to operate at up to 10 MHz. The data cannot be recognized or received correctly if the clock is too fast or does not have a 50% duty cycle.
On top of that, there are additional requirements for the data to meet the timing constraints:
- Read (MOSI):
Given that the MOSI is valid right at the launch edge, the slave can
read data correctly. Luckily, it's usually the case for most masters.
The Device can read data correctly only if the data is already set at the launch edge. Although it is usually the case for most masters.
- Write (MISO):
To meet the requirement that MISO is stable before the next latch edge of
SPI clock, the output delay of MISO signal should be shorter than half a
clock. The output delay and frequency limitation (given that the clock is
balanced) of different cases are as below :
The output delay of the MISO signal needs to be shorter than half of a clock cycle period so that the MISO line is stable before the next latch edge. Given that the clock is balanced, the output delay and frequency limitations in different cases are given below.
+-------------+---------------------------+------------------------+
| | Output delay of MISO (ns) | Freq. limit (MHZ) |
| | Output delay of MISO (ns) | Freq. limit (MHz) |
+=============+===========================+========================+
| IOMUX | 43.75 | <11.4 |
| IO_MUX | 43.75 | <11.4 |
+-------------+---------------------------+------------------------+
| GPIO matrix | 68.75 | <7.2 |
+-------------+---------------------------+------------------------+
Note:
1. Random error will happen if the frequency exactly equals the
limitation
2. The clock uncertainty between master and slave (12.5ns) is
included.
3. The output delay is measured under ideal case (free of load). When
the loading of MISO pin is too heavy, the output delay will be longer,
and the maximum allowed frequency will be lower.
1. If the frequency is equal to the limitation, it can lead to random errors.
2. The clock uncertainty between Host and Device (12.5ns) is included.
3. The output delay is measured under ideal circumstances (no load). If the MISO pin is heavily loaded, the output delay will be longer, and the maximum allowed frequency will be lower.
Exception: The frequency is allowed to be higher if the master has more tolerance for the MISO setup time, e.g., latch data at the next edge than expected, or configurable latching time.
There is an exceptions: The frequency is allowed to be higher if the
master has more toleration for the MISO setup time, e.g. latch data at
the next edge than expected, or configurable latching time.
.. _spi_dma_known_issues:
Restrictions and Known issues
-------------------------------
Restrictions and Known Issues
-----------------------------
1. If the DMA is enabled, the rx buffer should be WORD aligned, i.e. Start
from the boundary of 32-bit and have length of multiples of 4 bytes. Or the
DMA may write incorrectly or out of the boundary.The driver will check for
this.
1. If DMA is enabled, the rx buffer should be word-aligned (starting from a 32-bit boundary and having a length of multiples of 4 bytes). Otherwise, DMA may write incorrectly or not in a boundary aligned manner. The driver reports an error if this condition is not satisfied.
Also, master should write lengths which are a multiple of 4 bytes. Data
longer than that will be discarded.
Also, a Host should write lengths that are multiples of 4 bytes. The data with inappropriate lengths will be discarded.
2. Furthurmore, the DMA requires a spi mode 1/3 timing. When using spi mode
0/2, the MISO signal has to output half a clock earlier to meet the timing.
The new timing is as below:
2. Furthermore, DMA requires SPI modes 1 and 3. For SPI modes 0 and 2, the MISO signal has to be launched half a clock cycle earlier to meet the timing. The new timing is as follows:
.. image:: /../_static/spi_slave_miso_dma.png
The hold time after the latch edge is 68.75ns (when GPIO matrix is
bypassed), no longer half a SPI clock. The master should sample immediately
at the latch edge, or communicate in mode 1/3. Or just initial the spi
slave without DMA.
If DMA is enabled, a Device's launch edge is half of an SPI clock cycle ahead of the normal time, shifting to the Master's actual latch edge. In this case, if the GPIO matrix is bypassed, the hold time for data sampling is 68.75 ns and no longer a half of an SPI clock cycle. If the GPIO matrix is used, the hold time will increase to 93.75 ns. The Host should sample the data immediately at the latch edge or communicate in SPI modes 1 or 3. If your Host cannot meet these timing requirements, initialize your Device without DMA.
Application Example
-------------------
Slave/master communication: :example:`peripherals/spi_slave`.
The code example for Device/Host communication can be found in the :example:`peripherals/spi_slave` directory of ESP-IDF examples.
API Reference
-------------

28
docs/en/api-reference/protocols/mqtt.rst
View File

@ -32,30 +32,30 @@ URI
- Curently support ``mqtt``, ``mqtts``, ``ws``, ``wss`` schemes
- MQTT over TCP samples:
- ``mqtt://iot.eclipse.org``: MQTT over TCP, default port 1883:
- ``mqtt://iot.eclipse.org:1884`` MQTT over TCP, port 1884:
- ``mqtt://username:password@iot.eclipse.org:1884`` MQTT over TCP,
- ``mqtt://mqtt.eclipse.org``: MQTT over TCP, default port 1883:
- ``mqtt://mqtt.eclipse.org:1884`` MQTT over TCP, port 1884:
- ``mqtt://username:password@mqtt.eclipse.org:1884`` MQTT over TCP,
port 1884, with username and password
- MQTT over SSL samples:
- ``mqtts://iot.eclipse.org``: MQTT over SSL, port 8883
- ``mqtts://iot.eclipse.org:8884``: MQTT over SSL, port 8884
- ``mqtts://mqtt.eclipse.org``: MQTT over SSL, port 8883
- ``mqtts://mqtt.eclipse.org:8884``: MQTT over SSL, port 8884
- MQTT over Websocket samples:
- ``ws://iot.eclipse.org:80/ws``
- ``ws://mqtt.eclipse.org:80/mqtt``
- MQTT over Websocket Secure samples:
- ``wss://iot.eclipse.org:443/ws``
- ``wss://mqtt.eclipse.org:443/mqtt``
- Minimal configurations:
.. code:: c
const esp_mqtt_client_config_t mqtt_cfg = {
.uri = "mqtt://iot.eclipse.org",
.uri = "mqtt://mqtt.eclipse.org",
// .user_context = (void *)your_context
};
esp_mqtt_client_handle_t client = esp_mqtt_client_init(&mqtt_cfg);
@ -71,25 +71,25 @@ URI
.. code:: c
const esp_mqtt_client_config_t mqtt_cfg = {
.uri = "mqtt://iot.eclipse.org:1234",
.uri = "mqtt://mqtt.eclipse.org:1234",
.port = 4567,
};
//MQTT client will connect to iot.eclipse.org using port 4567
//MQTT client will connect to mqtt.eclipse.org using port 4567
SSL
^^^
- Get certificate from server, example: ``iot.eclipse.org``
``openssl s_client -showcerts -connect iot.eclipse.org:8883 </dev/null 2>/dev/null|openssl x509 -outform PEM >iot_eclipse_org.pem``
- Get certificate from server, example: ``mqtt.eclipse.org``
``openssl s_client -showcerts -connect mqtt.eclipse.org:8883 </dev/null 2>/dev/null|openssl x509 -outform PEM >mqtt_eclipse_org.pem``
- Check the sample application: ``examples/mqtt_ssl``
- Configuration:
.. code:: cpp
const esp_mqtt_client_config_t mqtt_cfg = {
.uri = "mqtts://iot.eclipse.org:8883",
.uri = "mqtts://mqtt.eclipse.org:8883",
.event_handle = mqtt_event_handler,
.cert_pem = (const char *)iot_eclipse_org_pem_start,
.cert_pem = (const char *)mqtt_eclipse_org_pem_start,
};
For more options on ``esp_mqtt_client_config_t``, please refer to API reference below

1
examples/bluetooth/esp_ble_mesh/ble_mesh_client_model/main/CMakeLists.txt
View File

@ -1,4 +1,5 @@
set(COMPONENT_SRCS "ble_mesh_demo_main.c"
"ble_mesh_demo_init.c"
"board.c")
set(COMPONENT_ADD_INCLUDEDIRS ".")

143
examples/bluetooth/esp_ble_mesh/ble_mesh_client_model/main/ble_mesh_demo_init.c Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright (c) 2017 Intel Corporation
* Additional Copyright (c) 2018 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <string.h>
#include <sdkconfig.h>
/* BLE */
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
#include "esp_nimble_hci.h"
#include "nimble/nimble_port.h"
#include "nimble/nimble_port_freertos.h"
#include "host/ble_hs.h"
#include "host/util/util.h"
#include "console/console.h"
#endif
#include "esp_ble_mesh_defs.h"
#include "ble_mesh_demo_init.h"
#include "esp_ble_mesh_common_api.h"
#ifdef CONFIG_BT_BLUEDROID_ENABLED
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid + 2, esp_bt_dev_get_address(), BD_ADDR_LEN);
}
esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
static SemaphoreHandle_t mesh_sem;
static uint8_t own_addr_type;
void ble_store_config_init(void);
static uint8_t addr_val[6] = {0};
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid + 2, addr_val, BD_ADDR_LEN);
}
static void mesh_on_reset(int reason)
{
ESP_LOGI(TAG, "Resetting state; reason=%d", reason);
}
static void mesh_on_sync(void)
{
int rc;
rc = ble_hs_util_ensure_addr(0);
assert(rc == 0);
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
ESP_LOGI(TAG, "error determining address type; rc=%d", rc);
return;
}
rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL);
xSemaphoreGive(mesh_sem);
}
void mesh_host_task(void *param)
{
ESP_LOGI(TAG, "BLE Host Task Started");
/* This function will return only when nimble_port_stop() is executed */
nimble_port_run();
nimble_port_freertos_deinit();
}
esp_err_t bluetooth_init(void)
{
mesh_sem = xSemaphoreCreateBinary();
if (mesh_sem == NULL) {
ESP_LOGE(TAG, "Failed to create mesh semaphore");
return ESP_FAIL;
}
ESP_ERROR_CHECK(esp_nimble_hci_and_controller_init());
nimble_port_init();
/* Initialize the NimBLE host configuration. */
ble_hs_cfg.reset_cb = mesh_on_reset;
ble_hs_cfg.sync_cb = mesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
/* XXX Need to have template for store */
ble_store_config_init();
nimble_port_freertos_init(mesh_host_task);
xSemaphoreTake(mesh_sem, portMAX_DELAY);
return ESP_OK;
}
#endif

18
examples/bluetooth/esp_ble_mesh/ble_mesh_client_model/main/ble_mesh_demo_init.h Normal file
View File

@ -0,0 +1,18 @@
/*
This example code is in the Public Domain (or CC0 licensed, at your option.)
Unless required by applicable law or agreed to in writing, this
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef _BLE_MESH_DEMO_INIT_H_
#define _BLE_MESH_DEMO_INIT_H_
#define TAG "ble_mesh_client"
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid);
esp_err_t bluetooth_init(void);
#endif

56
examples/bluetooth/esp_ble_mesh/ble_mesh_client_model/main/ble_mesh_demo_main.c
View File

@ -13,9 +13,6 @@
#include "esp_log.h"
#include "nvs_flash.h"
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#include "esp_ble_mesh_common_api.h"
#include "esp_ble_mesh_provisioning_api.h"
#include "esp_ble_mesh_networking_api.h"
@ -23,8 +20,7 @@
#include "esp_ble_mesh_generic_model_api.h"
#include "board.h"
#define TAG "ble_mesh_client"
#include "ble_mesh_demo_init.h"
#define CID_ESP 0x02E5
@ -450,8 +446,6 @@ static int ble_mesh_init(void)
{
int err = 0;
memcpy(dev_uuid + 2, esp_bt_dev_get_address(), ESP_BD_ADDR_LEN);
esp_ble_mesh_register_prov_callback(esp_ble_mesh_prov_cb);
esp_ble_mesh_register_custom_model_callback(esp_ble_mesh_model_cb);
esp_ble_mesh_register_generic_client_callback(esp_ble_mesh_generic_cb);
@ -471,45 +465,6 @@ static int ble_mesh_init(void)
return err;
}
static esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ret = nvs_flash_init();
if (ret == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
ret = nvs_flash_init();
}
ESP_ERROR_CHECK(ret);
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
void app_main(void)
{
int err;
@ -518,12 +473,21 @@ void app_main(void)
board_init();
err = nvs_flash_init();
if (err == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
err = nvs_flash_init();
}
ESP_ERROR_CHECK(err);
err = bluetooth_init();
if (err) {
ESP_LOGE(TAG, "esp32_bluetooth_init failed (err %d)", err);
return;
}
ble_mesh_get_dev_uuid(dev_uuid);
/* Initialize the Bluetooth Mesh Subsystem */
err = ble_mesh_init();
if (err) {

6
examples/bluetooth/esp_ble_mesh/ble_mesh_console/ble_mesh_provisioner/main/ble_mesh_register_provisioner_cmd.c
View File

@ -82,7 +82,7 @@ ble_mesh_provisioner_add_key_t provisioner_add_key;
void ble_mesh_regist_provisioner_cmd(void);
void ble_mesh_prov_adv_cb(const esp_bd_addr_t addr, const esp_ble_addr_type_t addr_type, const uint8_t adv_type,
void ble_mesh_prov_adv_cb(const esp_ble_mesh_bd_addr_t addr, const esp_ble_mesh_addr_type_t addr_type, const uint8_t adv_type,
const uint8_t *dev_uuid, uint16_t oob_info, esp_ble_mesh_prov_bearer_t bearer);
void ble_mesh_register_mesh_provisioner(void)
@ -90,12 +90,12 @@ void ble_mesh_register_mesh_provisioner(void)
ble_mesh_regist_provisioner_cmd();
}
void ble_mesh_prov_adv_cb(const esp_bd_addr_t addr, const esp_ble_addr_type_t addr_type, const uint8_t adv_type,
void ble_mesh_prov_adv_cb(const esp_ble_mesh_bd_addr_t addr, const esp_ble_mesh_addr_type_t addr_type, const uint8_t adv_type,
const uint8_t *dev_uuid, uint16_t oob_info, esp_ble_mesh_prov_bearer_t bearer)
{
ESP_LOGD(TAG, "enter %s\n", __func__);
ESP_LOGI(TAG, "scan device address:");
esp_log_buffer_hex(TAG, addr, sizeof(esp_bd_addr_t));
esp_log_buffer_hex(TAG, addr, sizeof(esp_ble_mesh_bd_addr_t));
ESP_LOGI(TAG, "scan device uuid:");
esp_log_buffer_hex(TAG, dev_uuid, 16);
ESP_LOGD(TAG, "exit %s\n", __func__);

3
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_client/main/CMakeLists.txt
View File

@ -1,4 +1,5 @@
set(COMPONENT_SRCS "ble_mesh_demo_main.c")
set(COMPONENT_SRCS "ble_mesh_demo_main.c"
"ble_mesh_demo_init.c")
set(COMPONENT_ADD_INCLUDEDIRS ".")

143
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_client/main/ble_mesh_demo_init.c Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright (c) 2017 Intel Corporation
* Additional Copyright (c) 2018 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <string.h>
#include <sdkconfig.h>
/* BLE */
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
#include "esp_nimble_hci.h"
#include "nimble/nimble_port.h"
#include "nimble/nimble_port_freertos.h"
#include "host/ble_hs.h"
#include "host/util/util.h"
#include "console/console.h"
#endif
#include "esp_ble_mesh_defs.h"
#include "ble_mesh_demo_init.h"
#include "esp_ble_mesh_common_api.h"
#ifdef CONFIG_BT_BLUEDROID_ENABLED
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid, esp_bt_dev_get_address(), BD_ADDR_LEN);
}
esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
static SemaphoreHandle_t mesh_sem;
static uint8_t own_addr_type;
void ble_store_config_init(void);
static uint8_t addr_val[6] = {0};
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid + 2, addr_val, BD_ADDR_LEN);
}
static void mesh_on_reset(int reason)
{
ESP_LOGI(TAG, "Resetting state; reason=%d", reason);
}
static void mesh_on_sync(void)
{
int rc;
rc = ble_hs_util_ensure_addr(0);
assert(rc == 0);
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
ESP_LOGI(TAG, "error determining address type; rc=%d", rc);
return;
}
rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL);
xSemaphoreGive(mesh_sem);
}
void mesh_host_task(void *param)
{
ESP_LOGI(TAG, "BLE Host Task Started");
/* This function will return only when nimble_port_stop() is executed */
nimble_port_run();
nimble_port_freertos_deinit();
}
esp_err_t bluetooth_init(void)
{
mesh_sem = xSemaphoreCreateBinary();
if (mesh_sem == NULL) {
ESP_LOGE(TAG, "Failed to create mesh semaphore");
return ESP_FAIL;
}
ESP_ERROR_CHECK(esp_nimble_hci_and_controller_init());
nimble_port_init();
/* Initialize the NimBLE host configuration. */
ble_hs_cfg.reset_cb = mesh_on_reset;
ble_hs_cfg.sync_cb = mesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
/* XXX Need to have template for store */
ble_store_config_init();
nimble_port_freertos_init(mesh_host_task);
xSemaphoreTake(mesh_sem, portMAX_DELAY);
return ESP_OK;
}
#endif

18
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_client/main/ble_mesh_demo_init.h Normal file
View File

@ -0,0 +1,18 @@
/*
This example code is in the Public Domain (or CC0 licensed, at your option.)
Unless required by applicable law or agreed to in writing, this
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef _BLE_MESH_DEMO_INIT_H_
#define _BLE_MESH_DEMO_INIT_H_
#define TAG "FAST_PROV_CLIENT_DEMO"
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid);
esp_err_t bluetooth_init(void);
#endif

73
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_client/main/ble_mesh_demo_main.c
View File

@ -19,10 +19,6 @@
#include "esp_log.h"
#include "nvs_flash.h"
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#include "esp_gap_ble_api.h"
#include "esp_ble_mesh_defs.h"
#include "esp_ble_mesh_common_api.h"
#include "esp_ble_mesh_provisioning_api.h"
@ -33,8 +29,7 @@
#include "esp_fast_prov_common.h"
#include "esp_fast_prov_operation.h"
#include "esp_fast_prov_client_model.h"
#define TAG "FAST_PROV_CLIENT_DEMO"
#include "ble_mesh_demo_init.h"
#define PROV_OWN_ADDR 0x0001
#define APP_KEY_OCTET 0x12
@ -191,8 +186,8 @@ static void provisioner_prov_complete(int node_index, const uint8_t uuid[16], ui
}
}
static void example_recv_unprov_adv_pkt(uint8_t dev_uuid[16], uint8_t addr[ESP_BD_ADDR_LEN],
esp_ble_addr_type_t addr_type, uint16_t oob_info,
static void example_recv_unprov_adv_pkt(uint8_t dev_uuid[16], uint8_t addr[BLE_MESH_ADDR_LEN],
esp_ble_mesh_addr_type_t addr_type, uint16_t oob_info,
uint8_t adv_type, esp_ble_mesh_prov_bearer_t bearer)
{
esp_ble_mesh_unprov_dev_add_t add_dev = {0};
@ -532,8 +527,6 @@ static esp_err_t ble_mesh_init(void)
{
esp_err_t err;
memcpy(dev_uuid, esp_bt_dev_get_address(), 6);
prov_info.unicast_min = prov.prov_start_address + prov_info.max_node_num;
prov_info.match_len = sizeof(match);
memcpy(prov_info.match_val, match, sizeof(match));
@ -544,18 +537,18 @@ static esp_err_t ble_mesh_init(void)
esp_ble_mesh_register_config_client_callback(example_config_client_callback);
esp_ble_mesh_register_generic_client_callback(example_generic_client_callback);
err = esp_ble_mesh_provisioner_set_dev_uuid_match(match, 0x02, 0x00, false);
if (err != ESP_OK) {
ESP_LOGE(TAG, "%s: Failed to set matching device UUID", __func__);
return ESP_FAIL;
}
err = esp_ble_mesh_init(&prov, &comp);
if (err != ESP_OK) {
ESP_LOGE(TAG, "%s: Failed to initialize BLE Mesh", __func__);
return ESP_FAIL;
}
err = esp_ble_mesh_provisioner_set_dev_uuid_match(match, 0x02, 0x00, false);
if (err != ESP_OK) {
ESP_LOGE(TAG, "%s: Failed to set matching device UUID", __func__);
return ESP_FAIL;
}
err = esp_ble_mesh_client_model_init(&vnd_models[0]);
if (err != ESP_OK) {
ESP_LOGE(TAG, "%s: Failed to initialize fast prov client model", __func__);
@ -579,57 +572,27 @@ static esp_err_t ble_mesh_init(void)
return err;
}
esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ret = nvs_flash_init();
if (ret == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
ret = nvs_flash_init();
}
ESP_ERROR_CHECK(ret);
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
void app_main(void)
{
int err;
ESP_LOGI(TAG, "Initializing...");
err = nvs_flash_init();
if (err == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
err = nvs_flash_init();
}
ESP_ERROR_CHECK(err);
err = bluetooth_init();
if (err) {
ESP_LOGE(TAG, "esp32_bluetooth_init failed (err %d)", err);
return;
}
ble_mesh_get_dev_uuid(dev_uuid);
/* Initialize the Bluetooth Mesh Subsystem */
err = ble_mesh_init();
if (err) {

1
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_server/main/CMakeLists.txt
View File

@ -1,4 +1,5 @@
set(COMPONENT_SRCS "ble_mesh_demo_main.c"
"ble_mesh_demo_init.c"
"board.c")
set(COMPONENT_ADD_INCLUDEDIRS ".")

143
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_server/main/ble_mesh_demo_init.c Normal file
View File

@ -0,0 +1,143 @@
/*
* Copyright (c) 2017 Intel Corporation
* Additional Copyright (c) 2018 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <string.h>
#include <sdkconfig.h>
/* BLE */
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
#include "esp_nimble_hci.h"
#include "nimble/nimble_port.h"
#include "nimble/nimble_port_freertos.h"
#include "host/ble_hs.h"
#include "host/util/util.h"
#include "console/console.h"
#endif
#include "esp_ble_mesh_defs.h"
#include "ble_mesh_demo_init.h"
#include "esp_ble_mesh_common_api.h"
#ifdef CONFIG_BT_BLUEDROID_ENABLED
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid + 2, esp_bt_dev_get_address(), BD_ADDR_LEN);
}
esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
#endif
#ifdef CONFIG_BT_NIMBLE_ENABLED
static SemaphoreHandle_t mesh_sem;
static uint8_t own_addr_type;
void ble_store_config_init(void);
static uint8_t addr_val[6] = {0};
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid)
{
memcpy(dev_uuid + 2, addr_val, BD_ADDR_LEN);
}
static void mesh_on_reset(int reason)
{
ESP_LOGI(TAG, "Resetting state; reason=%d", reason);
}
static void mesh_on_sync(void)
{
int rc;
rc = ble_hs_util_ensure_addr(0);
assert(rc == 0);
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
ESP_LOGI(TAG, "error determining address type; rc=%d", rc);
return;
}
rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL);
xSemaphoreGive(mesh_sem);
}
void mesh_host_task(void *param)
{
ESP_LOGI(TAG, "BLE Host Task Started");
/* This function will return only when nimble_port_stop() is executed */
nimble_port_run();
nimble_port_freertos_deinit();
}
esp_err_t bluetooth_init(void)
{
mesh_sem = xSemaphoreCreateBinary();
if (mesh_sem == NULL) {
ESP_LOGE(TAG, "Failed to create mesh semaphore");
return ESP_FAIL;
}
ESP_ERROR_CHECK(esp_nimble_hci_and_controller_init());
nimble_port_init();
/* Initialize the NimBLE host configuration. */
ble_hs_cfg.reset_cb = mesh_on_reset;
ble_hs_cfg.sync_cb = mesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
/* XXX Need to have template for store */
ble_store_config_init();
nimble_port_freertos_init(mesh_host_task);
xSemaphoreTake(mesh_sem, portMAX_DELAY);
return ESP_OK;
}
#endif

18
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_server/main/ble_mesh_demo_init.h Normal file
View File

@ -0,0 +1,18 @@
/*
This example code is in the Public Domain (or CC0 licensed, at your option.)
Unless required by applicable law or agreed to in writing, this
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef _BLE_MESH_DEMO_INIT_H_
#define _BLE_MESH_DEMO_INIT_H_
#define TAG "FAST_PROV_SERVER_DEMO"
void ble_mesh_get_dev_uuid(uint8_t *dev_uuid);
esp_err_t bluetooth_init(void);
#endif

66
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/ble_mesh_fast_prov_server/main/ble_mesh_demo_main.c
View File

@ -18,10 +18,6 @@
#include "esp_log.h"
#include "nvs_flash.h"
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_bt_device.h"
#include "esp_ble_mesh_defs.h"
#include "esp_ble_mesh_common_api.h"
#include "esp_ble_mesh_networking_api.h"
@ -33,8 +29,7 @@
#include "esp_fast_prov_operation.h"
#include "esp_fast_prov_client_model.h"
#include "esp_fast_prov_server_model.h"
#define TAG "FAST_PROV_SERVER_DEMO"
#include "ble_mesh_demo_init.h"
extern struct _led_state led_state[3];
extern struct k_delayed_work send_self_prov_node_addr_timer;
@ -336,8 +331,8 @@ static void provisioner_prov_complete(int node_idx, const uint8_t uuid[16], uint
}
}
static void example_recv_unprov_adv_pkt(uint8_t dev_uuid[16], uint8_t addr[ESP_BD_ADDR_LEN],
esp_ble_addr_type_t addr_type, uint16_t oob_info,
static void example_recv_unprov_adv_pkt(uint8_t dev_uuid[16], uint8_t addr[BLE_MESH_ADDR_LEN],
esp_ble_mesh_addr_type_t addr_type, uint16_t oob_info,
uint8_t adv_type, esp_ble_mesh_prov_bearer_t bearer)
{
esp_ble_mesh_unprov_dev_add_t add_dev = {0};
@ -358,7 +353,7 @@ static void example_recv_unprov_adv_pkt(uint8_t dev_uuid[16], uint8_t addr[ESP_B
add_dev.oob_info = oob_info;
add_dev.bearer = (uint8_t)bearer;
memcpy(add_dev.uuid, dev_uuid, 16);
memcpy(add_dev.addr, addr, ESP_BD_ADDR_LEN);
memcpy(add_dev.addr, addr, BLE_MESH_ADDR_LEN);
flag = ADD_DEV_RM_AFTER_PROV_FLAG | ADD_DEV_START_PROV_NOW_FLAG | ADD_DEV_FLUSHABLE_DEV_FLAG;
err = esp_ble_mesh_provisioner_add_unprov_dev(&add_dev, flag);
if (err != ESP_OK) {
@ -733,9 +728,6 @@ static esp_err_t ble_mesh_init(void)
{
esp_err_t err;
/* First two bytes of device uuid is compared with match value by Provisioner */
memcpy(dev_uuid + 2, esp_bt_dev_get_address(), 6);
esp_ble_mesh_register_prov_callback(example_ble_mesh_provisioning_cb);
esp_ble_mesh_register_custom_model_callback(example_ble_mesh_custom_model_cb);
esp_ble_mesh_register_config_client_callback(example_ble_mesh_config_client_cb);
@ -774,47 +766,6 @@ static esp_err_t ble_mesh_init(void)
return ESP_OK;
}
static esp_err_t bluetooth_init(void)
{
esp_err_t ret;
ret = nvs_flash_init();
if (ret == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
ret = nvs_flash_init();
}
ESP_ERROR_CHECK(ret);
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
ESP_LOGE(TAG, "%s initialize controller failed", __func__);
return ret;
}
ret = esp_bt_controller_enable(ESP_BT_MODE_BLE);
if (ret) {
ESP_LOGE(TAG, "%s enable controller failed", __func__);
return ret;
}
ret = esp_bluedroid_init();
if (ret) {
ESP_LOGE(TAG, "%s init bluetooth failed", __func__);
return ret;
}
ret = esp_bluedroid_enable();
if (ret) {
ESP_LOGE(TAG, "%s enable bluetooth failed", __func__);
return ret;
}
return ret;
}
void app_main(void)
{
esp_err_t err;
@ -827,12 +778,21 @@ void app_main(void)
return;
}
err = nvs_flash_init();
if (err == ESP_ERR_NVS_NO_FREE_PAGES) {
ESP_ERROR_CHECK(nvs_flash_erase());
err = nvs_flash_init();
}
ESP_ERROR_CHECK(err);
err = bluetooth_init();
if (err) {
ESP_LOGE(TAG, "esp32_bluetooth_init failed (err %d)", err);
return;
}
ble_mesh_get_dev_uuid(dev_uuid);
/* Initialize the Bluetooth Mesh Subsystem */
err = ble_mesh_init();
if (err) {

1
examples/bluetooth/esp_ble_mesh/ble_mesh_node/main/CMakeLists.txt
View File

@ -1,4 +1,5 @@
set(COMPONENT_SRCS "ble_mesh_demo_main.c"
"ble_mesh_demo_init.c"
"board.c")
set(COMPONENT_ADD_INCLUDEDIRS ".")

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