diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c index 14ae6f12fb..ed3d8755a5 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -76,14 +76,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]") channel_config.sibling_chan = NULL; TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0])); - TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); + gdma_trigger_t fake_ahb_trigger1 = { + .periph = 1, + .bus_id = SOC_GDMA_BUS_AHB, + .instance_id = 0, + }; + gdma_trigger_t fake_ahb_trigger2 = { + .periph = 2, + .bus_id = SOC_GDMA_BUS_AHB, + .instance_id = 1, + }; + TEST_ESP_OK(gdma_connect(tx_channels[0], fake_ahb_trigger1)); // can't connect multiple channels to the same peripheral - TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); - TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_ahb_trigger1)); + TEST_ESP_OK(gdma_connect(tx_channels[1], fake_ahb_trigger2)); - TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); // but rx and tx can connect to the same peripheral - TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + TEST_ESP_OK(gdma_connect(rx_channels[0], fake_ahb_trigger1)); + TEST_ESP_OK(gdma_connect(rx_channels[1], fake_ahb_trigger2)); for (int i = 0; i < 2; i++) { TEST_ESP_OK(gdma_disconnect(tx_channels[i])); TEST_ESP_OK(gdma_disconnect(rx_channels[i])); @@ -135,14 +145,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]") channel_config.sibling_chan = NULL; TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0])); - TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); + gdma_trigger_t fake_axi_trigger1 = { + .periph = 1, + .bus_id = SOC_GDMA_BUS_AXI, + .instance_id = 0, + }; + gdma_trigger_t fake_axi_trigger2 = { + .periph = 2, + .bus_id = SOC_GDMA_BUS_AXI, + .instance_id = 1, + }; + TEST_ESP_OK(gdma_connect(tx_channels[0], fake_axi_trigger1)); // can't connect multiple channels to the same peripheral - TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); - TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_axi_trigger1)); + TEST_ESP_OK(gdma_connect(tx_channels[1], fake_axi_trigger2)); - TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); // but rx and tx can connect to the same peripheral - TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); + TEST_ESP_OK(gdma_connect(rx_channels[0], fake_axi_trigger1)); + TEST_ESP_OK(gdma_connect(rx_channels[1], fake_axi_trigger2)); for (int i = 0; i < 2; i++) { TEST_ESP_OK(gdma_disconnect(tx_channels[i])); TEST_ESP_OK(gdma_disconnect(rx_channels[i])); @@ -153,7 +173,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]") } static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan, - gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, size_t sram_alignment, bool dma_link_in_ext_mem) + gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, size_t sram_alignment, bool dma_link_in_ext_mem) { gdma_strategy_config_t strategy = { @@ -366,7 +386,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup) TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") { test_gdma_m2m_mode(false); -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION // test again with retention test_gdma_m2m_mode(true); #endif @@ -384,7 +404,7 @@ static bool test_gdma_m2m_unalgined_rx_eof_callback(gdma_channel_handle_t dma_ch BaseType_t task_woken = pdFALSE; test_gdma_context_t *user_ctx = (test_gdma_context_t*)user_data; for (int i = 0; i < 3; i++) { - if(user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) { + if (user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) { TEST_ESP_OK(esp_cache_msync(user_ctx->align_array->aligned_buffer[i].aligned_buffer, ALIGN_UP(user_ctx->align_array->aligned_buffer[i].length, user_ctx->split_alignment), ESP_CACHE_MSYNC_FLAG_DIR_M2C)); } } @@ -471,7 +491,7 @@ static void test_gdma_m2m_unalgined_buffer_test(uint8_t *dst_data, uint8_t *src_ // validate the destination data for (int i = 0; i < data_length; i++) { - TEST_ASSERT_EQUAL(i % 256 , dst_data[i + offset_len]); + TEST_ASSERT_EQUAL(i % 256, dst_data[i + offset_len]); } free(stash_buffer); diff --git a/components/hal/esp32c61/include/hal/ahb_dma_ll.h b/components/hal/esp32c61/include/hal/ahb_dma_ll.h index a383788d76..bda732a8a0 100644 --- a/components/hal/esp32c61/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c61/include/hal/ahb_dma_ll.h @@ -27,7 +27,7 @@ extern "C" { #define GDMA_LL_TX_EVENT_MASK (0x3F) // any "dummy" peripheral ID can be used for M2M mode -#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31) +#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFE75) #define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F) #define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) diff --git a/components/soc/esp32c61/include/soc/gdma_channel.h b/components/soc/esp32c61/include/soc/gdma_channel.h index 9c300d1150..30353c1a8f 100644 --- a/components/soc/esp32c61/include/soc/gdma_channel.h +++ b/components/soc/esp32c61/include/soc/gdma_channel.h @@ -9,7 +9,6 @@ // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (1) -#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) #define SOC_GDMA_TRIG_PERIPH_ADC0 (8) @@ -20,7 +19,6 @@ #define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY #define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB -#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB diff --git a/components/soc/esp32c61/register/soc/ahb_dma_reg.h b/components/soc/esp32c61/register/soc/ahb_dma_reg.h index 7b0bec81a0..1fdb0969fa 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_reg.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_reg.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -12,7 +12,7 @@ extern "C" { #endif /** AHB_DMA_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 + * RX channel 0 raw interrupt status register */ #define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) /** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -66,7 +66,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 /** AHB_DMA_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 + * RX channel 0 masked interrupt status register */ #define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) /** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; @@ -120,7 +120,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 /** AHB_DMA_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 + * RX channel 0 interrupt enable register */ #define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) /** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -174,7 +174,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 /** AHB_DMA_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 + * RX channel 0 interrupt clear register */ #define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) /** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; @@ -228,7 +228,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 /** AHB_DMA_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 0 + * RX channel 1 raw interrupt status register */ #define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) /** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -282,7 +282,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 /** AHB_DMA_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 0 + * RX channel 1 masked interrupt status register */ #define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) /** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -336,7 +336,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 /** AHB_DMA_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 0 + * RX channel 1 interrupt enable register */ #define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) /** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -390,7 +390,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 /** AHB_DMA_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 0 + * RX channel 1 interrupt clear register */ #define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) /** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -444,7 +444,7 @@ extern "C" { #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 /** AHB_DMA_OUT_INT_RAW_CH0_REG register - * Raw interrupt status of TX channel 0 + * TX channel 0 raw interrupt status register */ #define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) /** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -491,7 +491,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 /** AHB_DMA_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 + * TX channel 0 masked interrupt status register */ #define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) /** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; @@ -538,7 +538,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 /** AHB_DMA_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 + * TX channel 0 interrupt enable register */ #define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) /** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -585,7 +585,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 /** AHB_DMA_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 + * TX channel 0 interrupt clear register */ #define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) /** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; @@ -632,7 +632,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 /** AHB_DMA_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 0 + * TX channel 1 raw interrupt status register */ #define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) /** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -679,7 +679,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 /** AHB_DMA_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 0 + * TX channel 1 masked interrupt status register */ #define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) /** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -726,7 +726,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 /** AHB_DMA_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 0 + * TX channel 1 interrupt enable register */ #define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) /** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -773,7 +773,7 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 /** AHB_DMA_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 0 + * TX channel 1 interrupt clear register */ #define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) /** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -819,25 +819,6 @@ extern "C" { #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 -/** AHB_DMA_AHB_TEST_REG register - * reserved - */ -#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) -/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTMODE 0x00000007U -#define AHB_DMA_AHB_TESTMODE_M (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S) -#define AHB_DMA_AHB_TESTMODE_V 0x00000007U -#define AHB_DMA_AHB_TESTMODE_S 0 -/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTADDR 0x00000003U -#define AHB_DMA_AHB_TESTADDR_M (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S) -#define AHB_DMA_AHB_TESTADDR_V 0x00000003U -#define AHB_DMA_AHB_TESTADDR_S 4 - /** AHB_DMA_MISC_CONF_REG register * Miscellaneous register */ @@ -850,16 +831,18 @@ extern "C" { #define AHB_DMA_AHBM_RST_INTER_V 0x00000001U #define AHB_DMA_AHBM_RST_INTER_S 0 /** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Configures whether or not to disable the fixed-priority channel arbitration.\\0: - * Enable\\1: Disable\\ + * Configures whether to disable the priority arbitration. + * 0: Enable + * 1: Disable */ #define AHB_DMA_ARB_PRI_DIS (BIT(2)) #define AHB_DMA_ARB_PRI_DIS_M (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S) #define AHB_DMA_ARB_PRI_DIS_V 0x00000001U #define AHB_DMA_ARB_PRI_DIS_S 2 /** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Configures clock gating.\\0: Support clock only when the application writes - * registers.\\ 1: Always force the clock on for registers.\\ + * Configures AHB DMA clock gating. + * 0: Support clock only when the application writes registers + * 1: Always force the clock on for registers */ #define AHB_DMA_CLK_EN (BIT(3)) #define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) @@ -883,46 +866,53 @@ extern "C" { */ #define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70) /** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset RX channel 0 FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH0 (BIT(0)) #define AHB_DMA_IN_RST_CH0_M (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S) #define AHB_DMA_IN_RST_CH0_V 0x00000001U #define AHB_DMA_IN_RST_CH0_S 0 /** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Reserved. + * Configures the owner bit value for inlink write-back. */ #define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) #define AHB_DMA_IN_LOOP_TEST_CH0_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH0_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel 0 to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel 0 to read + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INDSCR_BURST_EN_CH0 (BIT(2)) #define AHB_DMA_INDSCR_BURST_EN_CH0_M (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S) #define AHB_DMA_INDSCR_BURST_EN_CH0_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH0_S 2 /** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_MEM_TRANS_EN_CH0 (BIT(4)) #define AHB_DMA_MEM_TRANS_EN_CH0_M (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S) #define AHB_DMA_MEM_TRANS_EN_CH0_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH0_S 4 /** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channel0.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channel0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_ETM_EN_CH0 (BIT(5)) #define AHB_DMA_IN_ETM_EN_CH0_M (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S) #define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH0_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures maximum burst length for RX channel0. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) @@ -934,8 +924,9 @@ extern "C" { */ #define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74) /** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel 0.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_CHECK_OWNER_CH0 (BIT(12)) #define AHB_DMA_IN_CHECK_OWNER_CH0_M (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S) @@ -943,18 +934,22 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH0_S 12 /** AHB_DMA_INFIFO_STATUS_CH0_REG register - * Receive FIFO status of RX channel 0 + * RX channel 0 FIFO status */ #define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) /** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_INFIFO_FULL_CH0 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH0_M (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S) #define AHB_DMA_INFIFO_FULL_CH0_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH0_S 0 /** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_INFIFO_EMPTY_CH0 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH0_M (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S) @@ -968,35 +963,35 @@ extern "C" { #define AHB_DMA_INFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH0_M (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S) @@ -1008,15 +1003,16 @@ extern "C" { */ #define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) /** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. + * Represents the data popped from AHB DMA RX FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH0 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_M (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S) #define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_S 0 /** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB DMA RX FIFO. + * 0: Invalid. No effect + * 1: Pop */ #define AHB_DMA_INFIFO_POP_CH0 (BIT(12)) #define AHB_DMA_INFIFO_POP_CH0_M (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S) @@ -1028,39 +1024,46 @@ extern "C" { */ #define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) /** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to the current receive descriptor's address when there + * are some errors in current receiving data. + * 0: Not return + * 1: Return */ #define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) #define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 /** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel 0 from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop RX channel 0 from receiving data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_INLINK_STOP_CH0 (BIT(1)) #define AHB_DMA_INLINK_STOP_CH0_M (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S) #define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH0_S 1 /** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel 0 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable RX channel 0 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INLINK_START_CH0 (BIT(2)) #define AHB_DMA_INLINK_START_CH0_M (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S) #define AHB_DMA_INLINK_START_CH0_V 0x00000001U #define AHB_DMA_INLINK_START_CH0_S 2 /** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel 0 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel 0 for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_INLINK_RESTART_CH0 (BIT(3)) #define AHB_DMA_INLINK_RESTART_CH0_M (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S) #define AHB_DMA_INLINK_RESTART_CH0_V 0x00000001U #define AHB_DMA_INLINK_RESTART_CH0_S 3 /** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_INLINK_PARK_CH0 (BIT(4)) #define AHB_DMA_INLINK_PARK_CH0_M (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S) @@ -1068,26 +1071,28 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH0_S 4 /** AHB_DMA_IN_STATE_CH0_REG register - * Receive status of RX channel 0 + * RX channel 0 status */ #define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) /** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * Represents the lower 18 bits of the next receive descriptor address that is + * pre-read (but not processed yet). If the current receive descriptor is the last + * descriptor, then this field represents the address of the current receive + * descriptor. */ #define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_M (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S) #define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_S 18 /** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_STATE_CH0 0x00000007U #define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) @@ -1121,12 +1126,13 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_CH0_REG register - * Current receive descriptor address of RX channel 0 + * Address of the next receive descriptor pointed by the current pre-read receive + * descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90) /** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. + * receive descriptor that is pre-read. */ #define AHB_DMA_INLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH0_M (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S) @@ -1134,12 +1140,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH0_S 0 /** AHB_DMA_IN_DSCR_BF0_CH0_REG register - * The last receive descriptor address of RX channel 0 + * Address of the current pre-read receive descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94) /** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. + * Represents the address of the current receive descriptor x that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH0_M (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S) @@ -1147,12 +1152,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_IN_DSCR_BF1_CH0_REG register - * The second-to-last receive descriptor address of RX channel 0 + * Address of the previous pre-read receive descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98) /** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. + * Represents the address of the previous receive descriptor x-1 that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH0_M (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S) @@ -1164,8 +1168,9 @@ extern "C" { */ #define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) /** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0.The larger of the value, the higher of the + * Configures the priority of RX channel 0. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_RX_PRI_CH0 0x0000000FU #define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) @@ -1177,9 +1182,16 @@ extern "C" { */ #define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0) /** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel 0. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) @@ -1187,11 +1199,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH0_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register - * RX_done Inlink descriptor address of RX channel 0 + * Address of the completed inlink descriptor on RX channel 0 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xb0) /** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . + * Represents the address of the inlink descriptor when this descriptor is completed. */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) @@ -1203,57 +1215,67 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) /** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ + * Configures the reset state of TX channel 0 FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset */ #define AHB_DMA_OUT_RST_CH0 (BIT(0)) #define AHB_DMA_OUT_RST_CH0_M (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S) #define AHB_DMA_OUT_RST_CH0_V 0x00000001U #define AHB_DMA_OUT_RST_CH0_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Reserved. + * Configures the owner bit value for outlink write-back. */ #define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) #define AHB_DMA_OUT_LOOP_TEST_CH0_V 0x00000001U #define AHB_DMA_OUT_LOOP_TEST_CH0_S 1 /** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) #define AHB_DMA_OUT_AUTO_WRBACK_CH0_M (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S) #define AHB_DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH0_S 2 /** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 0 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been + * pushed into FIFO in AHB DMA. + * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been + * popped from FIFO in AHB DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) #define AHB_DMA_OUT_EOF_MODE_CH0_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH0_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 0 reading - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for TX channel 0 reading + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) #define AHB_DMA_OUTDSCR_BURST_EN_CH0_M (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S) #define AHB_DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH0_S 4 /** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for TX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_ETM_EN_CH0 (BIT(6)) #define AHB_DMA_OUT_ETM_EN_CH0_M (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S) #define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH0_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures maximum burst length for TX channel0. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) @@ -1265,8 +1287,9 @@ extern "C" { */ #define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4) /** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel 0.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) #define AHB_DMA_OUT_CHECK_OWNER_CH0_M (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S) @@ -1274,18 +1297,22 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH0_REG register - * Transmit FIFO status of TX channel 0 + * TX channel 0 FIFO status */ #define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) /** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_OUTFIFO_FULL_CH0 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH0_M (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S) #define AHB_DMA_OUTFIFO_FULL_CH0_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH0_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH0_M (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S) @@ -1332,15 +1359,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) /** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Represents the data that need to be pushed into AHB DMA TX FIFO. */ #define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) #define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures whether to push data into AHB DMA TX FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) @@ -1352,31 +1380,36 @@ extern "C" { */ #define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) /** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel 0 from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop TX channel 0 from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_OUTLINK_STOP_CH0 (BIT(0)) #define AHB_DMA_OUTLINK_STOP_CH0_M (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S) #define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH0_S 0 /** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel 0 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable TX channel 0 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTLINK_START_CH0 (BIT(1)) #define AHB_DMA_OUTLINK_START_CH0_M (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S) #define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH0_S 1 /** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel 0 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel 0 for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_OUTLINK_RESTART_CH0 (BIT(2)) #define AHB_DMA_OUTLINK_RESTART_CH0_M (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S) #define AHB_DMA_OUTLINK_RESTART_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_RESTART_CH0_S 2 /** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_OUTLINK_PARK_CH0 (BIT(3)) #define AHB_DMA_OUTLINK_PARK_CH0_M (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S) @@ -1384,26 +1417,28 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH0_S 3 /** AHB_DMA_OUT_STATE_CH0_REG register - * Transmit status of TX channel 0 + * TX channel 0 status */ #define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. + * Represents the lower 18 bits of the next transmit descriptor address that is + * pre-read (but not processed yet). If the current transmit descriptor is the last + * descriptor, then this field represents the address of the current transmit + * descriptor. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_M (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S) #define AHB_DMA_OUT_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_S 18 /** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_STATE_CH0 0x00000007U #define AHB_DMA_OUT_STATE_CH0_M (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S) @@ -1437,12 +1472,13 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_CH0_REG register - * Current transmit descriptor address of TX channel 0 + * Address of the next transmit descriptor pointed by the current pre-read transmit + * descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0) /** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. + * transmit descriptor that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH0_M (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S) @@ -1450,12 +1486,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH0_REG register - * The last transmit descriptor address of TX channel 0 + * Address of the current pre-read transmit descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. + * Represents the address of the current transmit descriptor y that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S) @@ -1463,12 +1498,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH0_REG register - * The second-to-last transmit descriptor address of TX channel 0 + * Address of the previous pre-read transmit descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. + * Represents the address of the previous transmit descriptor y-1 that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S) @@ -1480,8 +1514,9 @@ extern "C" { */ #define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) /** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0.The larger of the value, the higher of the + * Configures the priority of TX channel 0. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_TX_PRI_CH0 0x0000000FU #define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) @@ -1493,9 +1528,16 @@ extern "C" { */ #define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100) /** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 0.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel 0. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) @@ -1503,7 +1545,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH0_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register - * TX done outlink descriptor address of TX channel 0 + * Address of the completed outlink descriptor on TX channel 0 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x110) /** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; @@ -1515,50 +1557,57 @@ extern "C" { #define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S 0 /** AHB_DMA_IN_CONF0_CH1_REG register - * Configuration register 0 of RX channel 0 + * Configuration register 0 of RX channel 1 */ #define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) /** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset RX channel 1 FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH1 (BIT(0)) #define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) #define AHB_DMA_IN_RST_CH1_V 0x00000001U #define AHB_DMA_IN_RST_CH1_S 0 /** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Reserved. + * Configures the owner bit value for inlink write-back. */ #define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) #define AHB_DMA_IN_LOOP_TEST_CH1_V 0x00000001U #define AHB_DMA_IN_LOOP_TEST_CH1_S 1 /** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel 1 to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel 1 to read + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INDSCR_BURST_EN_CH1 (BIT(2)) #define AHB_DMA_INDSCR_BURST_EN_CH1_M (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S) #define AHB_DMA_INDSCR_BURST_EN_CH1_V 0x00000001U #define AHB_DMA_INDSCR_BURST_EN_CH1_S 2 /** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_MEM_TRANS_EN_CH1 (BIT(4)) #define AHB_DMA_MEM_TRANS_EN_CH1_M (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S) #define AHB_DMA_MEM_TRANS_EN_CH1_V 0x00000001U #define AHB_DMA_MEM_TRANS_EN_CH1_S 4 /** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channel1.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channel1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_ETM_EN_CH1 (BIT(5)) #define AHB_DMA_IN_ETM_EN_CH1_M (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S) #define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH1_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures maximum burst length for RX channel1. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) @@ -1566,12 +1615,13 @@ extern "C" { #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S 6 /** AHB_DMA_IN_CONF1_CH1_REG register - * Configuration register 1 of RX channel 0 + * Configuration register 1 of RX channel 1 */ #define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134) /** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel 1.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_IN_CHECK_OWNER_CH1 (BIT(12)) #define AHB_DMA_IN_CHECK_OWNER_CH1_M (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S) @@ -1579,18 +1629,22 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 /** AHB_DMA_INFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 0 + * RX channel 1 FIFO status */ #define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) /** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_INFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_INFIFO_FULL_CH1_M (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S) #define AHB_DMA_INFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_INFIFO_FULL_CH1_S 0 /** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_INFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_INFIFO_EMPTY_CH1_M (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S) @@ -1604,35 +1658,35 @@ extern "C" { #define AHB_DMA_INFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH1_M (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S) @@ -1640,19 +1694,20 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 /** AHB_DMA_IN_POP_CH1_REG register - * Pop control register of RX channel 0 + * Pop control register of RX channel 1 */ #define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) /** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. + * Represents the data popped from AHB DMA RX FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH1 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_M (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S) #define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_S 0 /** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB DMA RX FIFO. + * 0: Invalid. No effect + * 1: Pop */ #define AHB_DMA_INFIFO_POP_CH1 (BIT(12)) #define AHB_DMA_INFIFO_POP_CH1_M (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S) @@ -1660,43 +1715,50 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH1_S 12 /** AHB_DMA_IN_LINK_CH1_REG register - * Linked list descriptor configuration and control register of RX channel 0 + * Linked list descriptor configuration and control register of RX channel 1 */ #define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) /** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to the current receive descriptor's address when there + * are some errors in current receiving data. + * 0: Not return + * 1: Return */ #define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) #define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 /** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel 1 from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop RX channel 1 from receiving data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_INLINK_STOP_CH1 (BIT(1)) #define AHB_DMA_INLINK_STOP_CH1_M (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S) #define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH1_S 1 /** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel 1 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable RX channel 1 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_INLINK_START_CH1 (BIT(2)) #define AHB_DMA_INLINK_START_CH1_M (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S) #define AHB_DMA_INLINK_START_CH1_V 0x00000001U #define AHB_DMA_INLINK_START_CH1_S 2 /** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel 1 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel 1 for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_INLINK_RESTART_CH1 (BIT(3)) #define AHB_DMA_INLINK_RESTART_CH1_M (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S) #define AHB_DMA_INLINK_RESTART_CH1_V 0x00000001U #define AHB_DMA_INLINK_RESTART_CH1_S 3 /** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_INLINK_PARK_CH1 (BIT(4)) #define AHB_DMA_INLINK_PARK_CH1_M (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S) @@ -1704,26 +1766,28 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH1_S 4 /** AHB_DMA_IN_STATE_CH1_REG register - * Receive status of RX channel 0 + * RX channel 1 status */ #define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) /** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * Represents the lower 18 bits of the next receive descriptor address that is + * pre-read (but not processed yet). If the current receive descriptor is the last + * descriptor, then this field represents the address of the current receive + * descriptor. */ #define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_M (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S) #define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_S 18 /** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_STATE_CH1 0x00000007U #define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) @@ -1731,7 +1795,7 @@ extern "C" { #define AHB_DMA_IN_STATE_CH1_S 20 /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when EOF occurs on RX channel 0 + * Receive descriptor address when EOF occurs on RX channel 1 */ #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148) /** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1744,7 +1808,7 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when errors occur of RX channel 0 + * Receive descriptor address when errors occur of RX channel 1 */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1757,12 +1821,13 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_CH1_REG register - * Current receive descriptor address of RX channel 0 + * Address of the next receive descriptor pointed by the current pre-read receive + * descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) /** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. + * receive descriptor that is pre-read. */ #define AHB_DMA_INLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH1_M (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S) @@ -1770,12 +1835,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH1_S 0 /** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * The last receive descriptor address of RX channel 0 + * Address of the current pre-read receive descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) /** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. + * Represents the address of the current receive descriptor x that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH1_M (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S) @@ -1783,12 +1847,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * The second-to-last receive descriptor address of RX channel 0 + * Address of the previous pre-read receive descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) /** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. + * Represents the address of the previous receive descriptor x-1 that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH1_M (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S) @@ -1796,12 +1859,13 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_IN_PRI_CH1_REG register - * Priority register of RX channel 0 + * Priority register of RX channel 1 */ #define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) /** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1.The larger of the value, the higher of the + * Configures the priority of RX channel 1. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_RX_PRI_CH1 0x0000000FU #define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) @@ -1809,13 +1873,20 @@ extern "C" { #define AHB_DMA_RX_PRI_CH1_S 0 /** AHB_DMA_IN_PERI_SEL_CH1_REG register - * Peripheral selection register of RX channel 0 + * Peripheral selection register of RX channel 1 */ #define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160) /** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel 1. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) @@ -1823,11 +1894,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH1_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register - * RX_done Inlink descriptor address of RX channel 0 + * Address of the completed inlink descriptor on RX channel 1 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x170) /** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . + * Represents the address of the inlink descriptor when this descriptor is completed. */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) @@ -1839,57 +1910,67 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) /** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ + * Configures the reset state of TX channel 1 FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset */ #define AHB_DMA_OUT_RST_CH1 (BIT(0)) #define AHB_DMA_OUT_RST_CH1_M (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S) #define AHB_DMA_OUT_RST_CH1_V 0x00000001U #define AHB_DMA_OUT_RST_CH1_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Reserved. + * Configures the owner bit value for outlink write-back. */ #define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) #define AHB_DMA_OUT_LOOP_TEST_CH1_V 0x00000001U #define AHB_DMA_OUT_LOOP_TEST_CH1_S 1 /** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) #define AHB_DMA_OUT_AUTO_WRBACK_CH1_M (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S) #define AHB_DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U #define AHB_DMA_OUT_AUTO_WRBACK_CH1_S 2 /** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 1 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 1 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been + * pushed into FIFO in AHB DMA. + * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been + * popped from FIFO in AHB DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) #define AHB_DMA_OUT_EOF_MODE_CH1_V 0x00000001U #define AHB_DMA_OUT_EOF_MODE_CH1_S 3 /** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 1 reading - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for TX channel 1 reading + * descriptors. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) #define AHB_DMA_OUTDSCR_BURST_EN_CH1_M (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S) #define AHB_DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U #define AHB_DMA_OUTDSCR_BURST_EN_CH1_S 4 /** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 1.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for TX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_ETM_EN_CH1 (BIT(6)) #define AHB_DMA_OUT_ETM_EN_CH1_M (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S) #define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH1_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures maximum burst length for TX channel1. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) @@ -1897,12 +1978,13 @@ extern "C" { #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S 8 /** AHB_DMA_OUT_CONF1_CH1_REG register - * Configuration register 1 of TX channel 0 + * Configuration register 1 of TX channel 1 */ #define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194) /** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel 1.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) #define AHB_DMA_OUT_CHECK_OWNER_CH1_M (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S) @@ -1910,18 +1992,22 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * Transmit FIFO status of TX channel 0 + * TX channel 1 FIFO status */ #define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) /** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ #define AHB_DMA_OUTFIFO_FULL_CH1 (BIT(0)) #define AHB_DMA_OUTFIFO_FULL_CH1_M (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S) #define AHB_DMA_OUTFIFO_FULL_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_FULL_CH1_S 0 /** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ #define AHB_DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) #define AHB_DMA_OUTFIFO_EMPTY_CH1_M (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S) @@ -1964,19 +2050,20 @@ extern "C" { #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_OUT_PUSH_CH1_REG register - * Push control register of TX channel 0 + * Push control register of TX channel 1 */ #define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) /** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Represents the data that need to be pushed into AHB DMA TX FIFO. */ #define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) #define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures whether to push data into AHB DMA TX FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) @@ -1984,35 +2071,40 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 /** AHB_DMA_OUT_LINK_CH1_REG register - * Linked list descriptor configuration and control register of TX channel 0 + * Linked list descriptor configuration and control register of TX channel 1 */ #define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) /** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel 1 from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop TX channel 1 from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ #define AHB_DMA_OUTLINK_STOP_CH1 (BIT(0)) #define AHB_DMA_OUTLINK_STOP_CH1_M (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S) #define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH1_S 0 /** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel 1 for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable TX channel 1 for data transfer. + * 0: Disable + * 1: Enable */ #define AHB_DMA_OUTLINK_START_CH1 (BIT(1)) #define AHB_DMA_OUTLINK_START_CH1_M (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S) #define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH1_S 1 /** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel 1 for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel 1 for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ #define AHB_DMA_OUTLINK_RESTART_CH1 (BIT(2)) #define AHB_DMA_OUTLINK_RESTART_CH1_M (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S) #define AHB_DMA_OUTLINK_RESTART_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_RESTART_CH1_S 2 /** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ #define AHB_DMA_OUTLINK_PARK_CH1 (BIT(3)) #define AHB_DMA_OUTLINK_PARK_CH1_M (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S) @@ -2020,26 +2112,28 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH1_S 3 /** AHB_DMA_OUT_STATE_CH1_REG register - * Transmit status of TX channel 0 + * TX channel 1 status */ #define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. + * Represents the lower 18 bits of the next transmit descriptor address that is + * pre-read (but not processed yet). If the current transmit descriptor is the last + * descriptor, then this field represents the address of the current transmit + * descriptor. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_M (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S) #define AHB_DMA_OUT_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_S 18 /** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_STATE_CH1 0x00000007U #define AHB_DMA_OUT_STATE_CH1_M (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S) @@ -2047,7 +2141,7 @@ extern "C" { #define AHB_DMA_OUT_STATE_CH1_S 20 /** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register - * Transmit descriptor address when EOF occurs on TX channel 0 + * Transmit descriptor address when EOF occurs on TX channel 1 */ #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8) /** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2060,7 +2154,7 @@ extern "C" { #define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register - * The last transmit descriptor address when EOF occurs on TX channel 0 + * The last transmit descriptor address when EOF occurs on TX channel 1 */ #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac) /** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2073,12 +2167,13 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_CH1_REG register - * Current transmit descriptor address of TX channel 0 + * Address of the next transmit descriptor pointed by the current pre-read transmit + * descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) /** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. + * transmit descriptor that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH1_M (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S) @@ -2086,12 +2181,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * The last transmit descriptor address of TX channel 0 + * Address of the current pre-read transmit descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. + * Represents the address of the current transmit descriptor y that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S) @@ -2099,12 +2193,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * The second-to-last transmit descriptor address of TX channel 0 + * Address of the previous pre-read transmit descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. + * Represents the address of the previous transmit descriptor y-1 that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S) @@ -2112,12 +2205,13 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 /** AHB_DMA_OUT_PRI_CH1_REG register - * Priority register of TX channel 0 + * Priority register of TX channel 1 */ #define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) /** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1.The larger of the value, the higher of the + * Configures the priority of TX channel 1. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_TX_PRI_CH1 0x0000000FU #define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) @@ -2125,13 +2219,20 @@ extern "C" { #define AHB_DMA_TX_PRI_CH1_S 0 /** AHB_DMA_OUT_PERI_SEL_CH1_REG register - * Peripheral selection register of TX channel 0 + * Peripheral selection register of TX channel 1 */ #define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0) /** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel 1.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel 1. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) @@ -2139,7 +2240,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH1_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register - * TX done outlink descriptor address of TX channel 0 + * Address of the completed outlink descriptor on TX channel 1 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1d0) /** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2155,7 +2256,8 @@ extern "C" { */ #define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) /** AHB_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel0 + * Configures the weight (i.e the number of tokens) of TX channel0. + * Value range: 0 ~ 15. */ #define AHB_DMA_TX_CH_ARB_WEIGH_CH0 0x0000000FU #define AHB_DMA_TX_CH_ARB_WEIGH_CH0_M (AHB_DMA_TX_CH_ARB_WEIGH_CH0_V << AHB_DMA_TX_CH_ARB_WEIGH_CH0_S) @@ -2167,7 +2269,9 @@ extern "C" { */ #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) /** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for TX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S) @@ -2175,11 +2279,12 @@ extern "C" { #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S 0 /** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register - * TX channel 0 arbitration weight configuration register + * TX channel 1 arbitration weight configuration register */ #define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) /** AHB_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel1 + * Configures the weight (i.e the number of tokens) of TX channel1. + * Value range: 0 ~ 15. */ #define AHB_DMA_TX_CH_ARB_WEIGH_CH1 0x0000000FU #define AHB_DMA_TX_CH_ARB_WEIGH_CH1_M (AHB_DMA_TX_CH_ARB_WEIGH_CH1_V << AHB_DMA_TX_CH_ARB_WEIGH_CH1_S) @@ -2187,11 +2292,13 @@ extern "C" { #define AHB_DMA_TX_CH_ARB_WEIGH_CH1_S 0 /** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG register - * TX channel 0 weight arbitration optimization enable register + * TX channel 1 weight arbitration optimization enable register */ #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) /** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for TX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) #define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S) @@ -2203,7 +2310,8 @@ extern "C" { */ #define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) /** AHB_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel0 + * Configures the weight (i.e the number of tokens) of RX channel0. + * Value range: 0 ~ 15. */ #define AHB_DMA_RX_CH_ARB_WEIGH_CH0 0x0000000FU #define AHB_DMA_RX_CH_ARB_WEIGH_CH0_M (AHB_DMA_RX_CH_ARB_WEIGH_CH0_V << AHB_DMA_RX_CH_ARB_WEIGH_CH0_S) @@ -2215,7 +2323,9 @@ extern "C" { */ #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) /** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for RX channel 0. + * 0: Disable + * 1: Enable */ #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S) @@ -2223,11 +2333,12 @@ extern "C" { #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S 0 /** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register - * RX channel 0 arbitration weight configuration register + * RX channel 1 arbitration weight configuration register */ #define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) /** AHB_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel1 + * Configures the weight (i.e the number of tokens) of RX channel1. + * Value range: 0 ~ 15. */ #define AHB_DMA_RX_CH_ARB_WEIGH_CH1 0x0000000FU #define AHB_DMA_RX_CH_ARB_WEIGH_CH1_M (AHB_DMA_RX_CH_ARB_WEIGH_CH1_V << AHB_DMA_RX_CH_ARB_WEIGH_CH1_S) @@ -2235,11 +2346,13 @@ extern "C" { #define AHB_DMA_RX_CH_ARB_WEIGH_CH1_S 0 /** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG register - * RX channel 0 weight arbitration optimization enable register + * RX channel 1 weight arbitration optimization enable register */ #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) /** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for RX channel 1. + * 0: Disable + * 1: Enable */ #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S) @@ -2247,11 +2360,11 @@ extern "C" { #define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S 0 /** AHB_DMA_IN_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of RX channel 0 + * Linked list descriptor configuration register of RX channel 0 */ #define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) /** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first receive descriptor's address. */ #define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) @@ -2259,11 +2372,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH0_S 0 /** AHB_DMA_IN_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of RX channel 0 + * Linked list descriptor configuration register of RX channel 1 */ #define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) /** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first receive descriptor's address. */ #define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) @@ -2271,11 +2384,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH1_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of TX channel 0 + * Linked list descriptor configuration register of TX channel 0 */ #define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8) /** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first transmit descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH0_M (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S) @@ -2283,11 +2396,11 @@ extern "C" { #define AHB_DMA_OUTLINK_ADDR_CH0_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of TX channel 0 + * Linked list descriptor configuration register of TX channel 1 */ #define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) /** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first transmit descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH1_M (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S) @@ -2347,7 +2460,9 @@ extern "C" { */ #define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4) /** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ + * Configures whether to enable weight arbitration for TX. + * 0: Disable + * 1: Enable */ #define AHB_DMA_WEIGHT_EN_TX (BIT(0)) #define AHB_DMA_WEIGHT_EN_TX_M (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S) @@ -2359,7 +2474,9 @@ extern "C" { */ #define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8) /** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ + * Configures whether to enable weight arbitration for RX. + * 0: Disable + * 1: Enable */ #define AHB_DMA_WEIGHT_EN_RX (BIT(0)) #define AHB_DMA_WEIGHT_EN_RX_M (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S) diff --git a/components/soc/esp32c61/register/soc/ahb_dma_struct.h b/components/soc/esp32c61/register/soc/ahb_dma_struct.h index a029efa783..13a4972de7 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_struct.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_struct.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -12,7 +12,7 @@ extern "C" { /** Group: Interrupt Registers */ /** Type of in_int_raw_chn register - * Raw interrupt status of RX channel 0 + * RX channel n raw interrupt status register */ typedef union { struct { @@ -50,7 +50,7 @@ typedef union { } ahb_dma_in_int_raw_chn_reg_t; /** Type of in_int_st_chn register - * Masked interrupt status of RX channel 0 + * RX channel n masked interrupt status register */ typedef union { struct { @@ -88,7 +88,7 @@ typedef union { } ahb_dma_in_int_st_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel 0 + * RX channel n interrupt enable register */ typedef union { struct { @@ -126,7 +126,7 @@ typedef union { } ahb_dma_in_int_ena_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel 0 + * RX channel n interrupt clear register */ typedef union { struct { @@ -164,7 +164,7 @@ typedef union { } ahb_dma_in_int_clr_chn_reg_t; /** Type of out_int_raw_chn register - * Raw interrupt status of TX channel 0 + * TX channel n raw interrupt status register */ typedef union { struct { @@ -198,7 +198,7 @@ typedef union { } ahb_dma_out_int_raw_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt status of TX channel 0 + * TX channel n masked interrupt status register */ typedef union { struct { @@ -232,7 +232,7 @@ typedef union { } ahb_dma_out_int_st_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel 0 + * TX channel n interrupt enable register */ typedef union { struct { @@ -266,7 +266,7 @@ typedef union { } ahb_dma_out_int_ena_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel 0 + * TX channel n interrupt clear register */ typedef union { struct { @@ -300,27 +300,6 @@ typedef union { } ahb_dma_out_int_clr_chn_reg_t; -/** Group: Debug Registers */ -/** Type of ahb_test register - * reserved - */ -typedef union { - struct { - /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t ahb_testmode:3; - uint32_t reserved_3:1; - /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - uint32_t ahb_testaddr:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_ahb_test_reg_t; - - /** Group: Configuration Registers */ /** Type of misc_conf register * Miscellaneous register @@ -333,13 +312,15 @@ typedef union { uint32_t ahbm_rst_inter:1; uint32_t reserved_1:1; /** arb_pri_dis : R/W; bitpos: [2]; default: 0; - * Configures whether or not to disable the fixed-priority channel arbitration.\\0: - * Enable\\1: Disable\\ + * Configures whether to disable the priority arbitration. + * 0: Enable + * 1: Disable */ uint32_t arb_pri_dis:1; /** clk_en : R/W; bitpos: [3]; default: 0; - * Configures clock gating.\\0: Support clock only when the application writes - * registers.\\ 1: Always force the clock on for registers.\\ + * Configures AHB DMA clock gating. + * 0: Support clock only when the application writes registers + * 1: Always force the clock on for registers */ uint32_t clk_en:1; uint32_t reserved_4:28; @@ -348,37 +329,44 @@ typedef union { } ahb_dma_misc_conf_reg_t; /** Type of in_conf0_chn register - * Configuration register 0 of RX channel 0 + * Configuration register 0 of RX channel n */ typedef union { struct { /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset RX channel n FSM and RX FIFO pointer. */ uint32_t in_rst_chn:1; /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Reserved. + * Configures the owner bit value for inlink write-back. */ uint32_t in_loop_test_chn:1; /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable INCR burst transfer for RX channel n to read - * descriptors.\\0: Disable\\1: Enable\\ + * Configures whether to enable INCR burst transfer for RX channel n to read + * descriptors. + * 0: Disable + * 1: Enable */ uint32_t indscr_burst_en_chn:1; uint32_t reserved_3:1; /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable memory-to-memory data transfer. + * 0: Disable + * 1: Enable */ uint32_t mem_trans_en_chn:1; /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable ETM control for RX channeln.\\0: Disable\\1: - * Enable\\ + * Configures whether to enable ETM control for RX channeln. + * 0: Disable + * 1: Enable */ uint32_t in_etm_en_chn:1; /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ + * Configures maximum burst length for RX channeln. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ uint32_t in_data_burst_mode_sel_chn:2; uint32_t reserved_8:24; @@ -387,14 +375,15 @@ typedef union { } ahb_dma_in_conf0_chn_reg_t; /** Type of in_conf1_chn register - * Configuration register 1 of RX channel 0 + * Configuration register 1 of RX channel n */ typedef union { struct { uint32_t reserved_0:12; /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for RX channel n.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for RX channel n. + * 0: Disable + * 1: Enable */ uint32_t in_check_owner_chn:1; uint32_t reserved_13:19; @@ -403,17 +392,18 @@ typedef union { } ahb_dma_in_conf1_chn_reg_t; /** Type of in_pop_chn register - * Pop control register of RX channel 0 + * Pop control register of RX channel n */ typedef union { struct { /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. + * Represents the data popped from AHB DMA RX FIFO. */ uint32_t infifo_rdata_chn:12; /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: - * Pop\\ + * Configures whether to pop data from AHB DMA RX FIFO. + * 0: Invalid. No effect + * 1: Pop */ uint32_t infifo_pop_chn:1; uint32_t reserved_13:19; @@ -422,32 +412,39 @@ typedef union { } ahb_dma_in_pop_chn_reg_t; /** Type of in_link_chn register - * Linked list descriptor configuration and control register of RX channel 0 + * Linked list descriptor configuration and control register of RX channel n */ typedef union { struct { /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; - * Configures whether or not to return to current receive descriptor's address when - * there are some errors in current receiving data.\\0: Not return\\1: Return\\ + * Configures whether to return to the current receive descriptor's address when there + * are some errors in current receiving data. + * 0: Not return + * 1: Return */ uint32_t inlink_auto_ret_chn:1; /** inlink_stop_chn : WT; bitpos: [1]; default: 0; - * Configures whether or not to stop AHB_DMA's RX channel n from receiving data.\\0: - * Invalid. No effect\\1: Stop\\ + * Configures whether to stop RX channel n from receiving data. + * 0: Invalid. No effect + * 1: Stop */ uint32_t inlink_stop_chn:1; /** inlink_start_chn : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable AHB_DMA's RX channel n for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable RX channel n for data transfer. + * 0: Disable + * 1: Enable */ uint32_t inlink_start_chn:1; /** inlink_restart_chn : WT; bitpos: [3]; default: 0; - * Configures whether or not to restart RX channel n for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart RX channel n for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ uint32_t inlink_restart_chn:1; /** inlink_park_chn : RO; bitpos: [4]; default: 1; - * Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the receive descriptor's FSM. + * 0: Running + * 1: Idle */ uint32_t inlink_park_chn:1; uint32_t reserved_5:27; @@ -455,15 +452,74 @@ typedef union { uint32_t val; } ahb_dma_in_link_chn_reg_t; +/** Type of out_conf0_chn register + * Configuration register 0 of TX channel n + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * Configures the reset state of TX channel n FSM and TX FIFO pointer. + * 0: Release reset + * 1: Reset + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * Configures the owner bit value for outlink write-back. + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Configures whether to enable automatic outlink write-back when all the data in TX + * FIFO has been transmitted. + * 0: Disable + * 1: Enable + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * Configures when to generate EOF flag. + * 0: EOF flag for TX channel n is generated when data to be transmitted has been + * pushed into FIFO in AHB DMA. + * 1: EOF flag for TX channel n is generated when data to be transmitted has been + * popped from FIFO in AHB DMA. + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Configures whether to enable INCR burst transfer for TX channel n reading + * descriptors. + * 0: Disable + * 1: Enable + */ + uint32_t outdscr_burst_en_chn:1; + uint32_t reserved_5:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Configures whether to enable ETM control for TX channel n. + * 0: Disable + * 1: Enable + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:1; + /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; + * Configures maximum burst length for TX channeln. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved + */ + uint32_t out_data_burst_mode_sel_chn:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} ahb_dma_out_conf0_chn_reg_t; + /** Type of out_conf1_chn register - * Configuration register 1 of TX channel 0 + * Configuration register 1 of TX channel n */ typedef union { struct { uint32_t reserved_0:12; /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether or not to enable owner bit check for TX channel n.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable owner bit check for TX channel n. + * 0: Disable + * 1: Enable */ uint32_t out_check_owner_chn:1; uint32_t reserved_13:19; @@ -472,17 +528,18 @@ typedef union { } ahb_dma_out_conf1_chn_reg_t; /** Type of out_push_chn register - * Push control register of TX channel 0 + * Push control register of TX channel n */ typedef union { struct { /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Represents the data that need to be pushed into AHB DMA TX FIFO. */ uint32_t outfifo_wdata_chn:9; /** outfifo_push_chn : WT; bitpos: [9]; default: 0; - * Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No - * effect\\1: Push\\ + * Configures whether to push data into AHB DMA TX FIFO. + * 0: Invalid. No effect + * 1: Push */ uint32_t outfifo_push_chn:1; uint32_t reserved_10:22; @@ -491,27 +548,32 @@ typedef union { } ahb_dma_out_push_chn_reg_t; /** Type of out_link_chn register - * Linked list descriptor configuration and control register of TX channel 0 + * Linked list descriptor configuration and control register of TX channel n */ typedef union { struct { /** outlink_stop_chn : WT; bitpos: [0]; default: 0; - * Configures whether or not to stop AHB_DMA's TX channel n from transmitting - * data.\\0: Invalid. No effect\\1: Stop\\ + * Configures whether to stop TX channel n from transmitting data. + * 0: Invalid. No effect + * 1: Stop */ uint32_t outlink_stop_chn:1; /** outlink_start_chn : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable AHB_DMA's TX channel n for data transfer.\\0: - * Disable\\1: Enable\\ + * Configures whether to enable TX channel n for data transfer. + * 0: Disable + * 1: Enable */ uint32_t outlink_start_chn:1; /** outlink_restart_chn : WT; bitpos: [2]; default: 0; - * Configures whether or not to restart TX channel n for AHB_DMA transfer.\\0: - * Invalid. No effect\\1: Restart\\ + * Configures whether to restart TX channel n for AHB DMA transfer. + * 0: Invalid. No effect + * 1: Restart */ uint32_t outlink_restart_chn:1; /** outlink_park_chn : RO; bitpos: [3]; default: 1; - * Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ + * Represents the status of the transmit descriptor's FSM. + * 0: Running + * 1: Idle */ uint32_t outlink_park_chn:1; uint32_t reserved_4:28; @@ -519,61 +581,14 @@ typedef union { uint32_t val; } ahb_dma_out_link_chn_reg_t; -/** Type of out_conf0_chn register - * Configuration register 0 of TX channel 1 - */ -typedef union { - struct { - /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ - */ - uint32_t out_rst_chn:1; - /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t out_loop_test_chn:1; - /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel n is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel n is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel n reading - * descriptors.\\0: Disable\\1: Enable\\ - */ - uint32_t outdscr_burst_en_chn:1; - uint32_t reserved_5:1; - /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel n.\\0: Disable\\1: - * Enable\\ - */ - uint32_t out_etm_en_chn:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: reserved\\ - */ - uint32_t out_data_burst_mode_sel_chn:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} ahb_dma_out_conf0_chn_reg_t; - /** Type of tx_ch_arb_weigh_chn register - * TX channel 0 arbitration weight configuration register + * TX channel n arbitration weight configuration register */ typedef union { struct { /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channeln + * Configures the weight (i.e the number of tokens) of TX channeln. + * Value range: 0 ~ 15. */ uint32_t tx_ch_arb_weigh_chn:4; uint32_t reserved_4:28; @@ -582,12 +597,14 @@ typedef union { } ahb_dma_tx_ch_arb_weigh_chn_reg_t; /** Type of tx_arb_weigh_opt_dir_chn register - * TX channel 0 weight arbitration optimization enable register + * TX channel n weight arbitration optimization enable register */ typedef union { struct { /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for TX channel n. + * 0: Disable + * 1: Enable */ uint32_t tx_arb_weigh_opt_dir_chn:1; uint32_t reserved_1:31; @@ -596,12 +613,13 @@ typedef union { } ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t; /** Type of rx_ch_arb_weigh_chn register - * RX channel 0 arbitration weight configuration register + * RX channel n arbitration weight configuration register */ typedef union { struct { /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channeln + * Configures the weight (i.e the number of tokens) of RX channeln. + * Value range: 0 ~ 15. */ uint32_t rx_ch_arb_weigh_chn:4; uint32_t reserved_4:28; @@ -610,12 +628,14 @@ typedef union { } ahb_dma_rx_ch_arb_weigh_chn_reg_t; /** Type of rx_arb_weigh_opt_dir_chn register - * RX channel 0 weight arbitration optimization enable register + * RX channel n weight arbitration optimization enable register */ typedef union { struct { /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for RX channel n. + * 0: Disable + * 1: Enable */ uint32_t rx_arb_weigh_opt_dir_chn:1; uint32_t reserved_1:31; @@ -624,12 +644,12 @@ typedef union { } ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; /** Type of in_link_addr_chn register - * Link list descriptor address configuration of RX channel 0 + * Linked list descriptor configuration register of RX channel n */ typedef union { struct { /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first receive descriptor's address. */ uint32_t inlink_addr_chn:32; }; @@ -637,12 +657,12 @@ typedef union { } ahb_dma_in_link_addr_chn_reg_t; /** Type of out_link_addr_chn register - * Link list descriptor address configuration of TX channel 0 + * Linked list descriptor configuration register of TX channel n */ typedef union { struct { /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first transmit descriptor's address. */ uint32_t outlink_addr_chn:32; }; @@ -709,7 +729,9 @@ typedef union { typedef union { struct { /** weight_en_tx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ + * Configures whether to enable weight arbitration for TX. + * 0: Disable + * 1: Enable */ uint32_t weight_en_tx:1; uint32_t reserved_1:31; @@ -723,7 +745,9 @@ typedef union { typedef union { struct { /** weight_en_rx : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ + * Configures whether to enable weight arbitration for RX. + * 0: Disable + * 1: Enable */ uint32_t weight_en_rx:1; uint32_t reserved_1:31; @@ -749,16 +773,20 @@ typedef union { /** Group: Status Registers */ /** Type of infifo_status_chn register - * Receive FIFO status of RX channel 0 + * RX channel n FIFO status */ typedef union { struct { /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full */ uint32_t infifo_full_chn:1; /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t infifo_empty_chn:1; uint32_t reserved_2:6; @@ -768,23 +796,23 @@ typedef union { uint32_t infifo_cnt_chn:7; uint32_t reserved_15:8; /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ uint32_t in_remain_under_1b_chn:1; /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ uint32_t in_remain_under_2b_chn:1; /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ uint32_t in_remain_under_3b_chn:1; /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ uint32_t in_remain_under_4b_chn:1; /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; - * reserved + * Reserved. */ uint32_t in_buf_hungry_chn:1; uint32_t reserved_28:4; @@ -793,21 +821,23 @@ typedef union { } ahb_dma_infifo_status_chn_reg_t; /** Type of in_state_chn register - * Receive status of RX channel 0 + * RX channel n status */ typedef union { struct { /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * Represents the lower 18 bits of the next receive descriptor address that is + * pre-read (but not processed yet). If the current receive descriptor is the last + * descriptor, then this field represents the address of the current receive + * descriptor. */ uint32_t inlink_dscr_addr_chn:18; /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ uint32_t in_dscr_state_chn:2; /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ uint32_t in_state_chn:3; uint32_t reserved_23:9; @@ -816,7 +846,7 @@ typedef union { } ahb_dma_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Receive descriptor address when EOF occurs on RX channel 0 + * Receive descriptor address when EOF occurs on RX channel n */ typedef union { struct { @@ -830,7 +860,7 @@ typedef union { } ahb_dma_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Receive descriptor address when errors occur of RX channel 0 + * Receive descriptor address when errors occur of RX channel n */ typedef union { struct { @@ -844,13 +874,14 @@ typedef union { } ahb_dma_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Current receive descriptor address of RX channel 0 + * Address of the next receive descriptor pointed by the current pre-read receive + * descriptor on RX channel n */ typedef union { struct { /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. + * receive descriptor that is pre-read. */ uint32_t inlink_dscr_chn:32; }; @@ -858,13 +889,12 @@ typedef union { } ahb_dma_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * The last receive descriptor address of RX channel 0 + * Address of the current pre-read receive descriptor on RX channel n */ typedef union { struct { /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. + * Represents the address of the current receive descriptor x that is pre-read. */ uint32_t inlink_dscr_bf0_chn:32; }; @@ -872,13 +902,12 @@ typedef union { } ahb_dma_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * The second-to-last receive descriptor address of RX channel 0 + * Address of the previous pre-read receive descriptor on RX channel n */ typedef union { struct { /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. + * Represents the address of the previous receive descriptor x-1 that is pre-read. */ uint32_t inlink_dscr_bf1_chn:32; }; @@ -886,12 +915,12 @@ typedef union { } ahb_dma_in_dscr_bf1_chn_reg_t; /** Type of in_done_des_addr_chn register - * RX_done Inlink descriptor address of RX channel 0 + * Address of the completed inlink descriptor on RX channel n */ typedef union { struct { /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . + * Represents the address of the inlink descriptor when this descriptor is completed. */ uint32_t in_done_des_addr_chn:32; }; @@ -899,16 +928,20 @@ typedef union { } ahb_dma_in_done_des_addr_chn_reg_t; /** Type of outfifo_status_chn register - * Transmit FIFO status of TX channel 0 + * TX channel n FIFO status */ typedef union { struct { /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full */ uint32_t outfifo_full_chn:1; /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty */ uint32_t outfifo_empty_chn:1; uint32_t reserved_2:6; @@ -939,21 +972,23 @@ typedef union { } ahb_dma_outfifo_status_chn_reg_t; /** Type of out_state_chn register - * Transmit status of TX channel 0 + * TX channel n status */ typedef union { struct { /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. + * Represents the lower 18 bits of the next transmit descriptor address that is + * pre-read (but not processed yet). If the current transmit descriptor is the last + * descriptor, then this field represents the address of the current transmit + * descriptor. */ uint32_t outlink_dscr_addr_chn:18; /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ uint32_t out_dscr_state_chn:2; /** out_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ uint32_t out_state_chn:3; uint32_t reserved_23:9; @@ -962,7 +997,7 @@ typedef union { } ahb_dma_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Transmit descriptor address when EOF occurs on TX channel 0 + * Transmit descriptor address when EOF occurs on TX channel n */ typedef union { struct { @@ -976,7 +1011,7 @@ typedef union { } ahb_dma_out_eof_des_addr_chn_reg_t; /** Type of out_eof_bfr_des_addr_chn register - * The last transmit descriptor address when EOF occurs on TX channel 0 + * The last transmit descriptor address when EOF occurs on TX channel n */ typedef union { struct { @@ -990,13 +1025,14 @@ typedef union { } ahb_dma_out_eof_bfr_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Current transmit descriptor address of TX channel 0 + * Address of the next transmit descriptor pointed by the current pre-read transmit + * descriptor on TX channel n */ typedef union { struct { /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. + * transmit descriptor that is pre-read. */ uint32_t outlink_dscr_chn:32; }; @@ -1004,13 +1040,12 @@ typedef union { } ahb_dma_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * The last transmit descriptor address of TX channel 0 + * Address of the current pre-read transmit descriptor on TX channel n */ typedef union { struct { /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. + * Represents the address of the current transmit descriptor y that is pre-read. */ uint32_t outlink_dscr_bf0_chn:32; }; @@ -1018,13 +1053,12 @@ typedef union { } ahb_dma_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * The second-to-last transmit descriptor address of TX channel 0 + * Address of the previous pre-read transmit descriptor on TX channel n */ typedef union { struct { /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. + * Represents the address of the previous transmit descriptor y-1 that is pre-read. */ uint32_t outlink_dscr_bf1_chn:32; }; @@ -1032,7 +1066,7 @@ typedef union { } ahb_dma_out_dscr_bf1_chn_reg_t; /** Type of out_done_des_addr_chn register - * TX done outlink descriptor address of TX channel 0 + * Address of the completed outlink descriptor on TX channel n */ typedef union { struct { @@ -1047,13 +1081,14 @@ typedef union { /** Group: Priority Registers */ /** Type of in_pri_chn register - * Priority register of RX channel 0 + * Priority register of RX channel n */ typedef union { struct { /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel n.The larger of the value, the higher of the + * Configures the priority of RX channel n. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ uint32_t rx_pri_chn:4; uint32_t reserved_4:28; @@ -1062,13 +1097,14 @@ typedef union { } ahb_dma_in_pri_chn_reg_t; /** Type of out_pri_chn register - * Priority register of TX channel 0 + * Priority register of TX channel n */ typedef union { struct { /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel n.The larger of the value, the higher of the + * Configures the priority of TX channel n. The larger the value, the higher the * priority. + * Value range: 0 ~ 5 */ uint32_t tx_pri_chn:4; uint32_t reserved_4:28; @@ -1077,16 +1113,23 @@ typedef union { } ahb_dma_out_pri_chn_reg_t; -/** Group: Peripheral Select Registers */ +/** Group: Peripheral Selection Registers */ /** Type of in_peri_sel_chn register - * Peripheral selection register of RX channel 0 + * Peripheral selection register of RX channel n */ typedef union { struct { /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to RX channel n. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ uint32_t peri_in_sel_chn:6; uint32_t reserved_6:26; @@ -1095,14 +1138,21 @@ typedef union { } ahb_dma_in_peri_sel_chn_reg_t; /** Type of out_peri_sel_chn register - * Peripheral selection register of TX channel 0 + * Peripheral selection register of TX channel n */ typedef union { struct { /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: - * UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ - * 10: Dummy\\ 11~15: Dummy\\ + * Configures the peripheral connected to TX channel n. + * 0: Dummy + * 1: GP-SPI + * 2: Dummy + * 3: I2S + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ uint32_t peri_out_sel_chn:6; uint32_t reserved_6:26; @@ -1184,8 +1234,7 @@ typedef struct { volatile ahb_dma_in_int_chn_reg_t in_intr[2]; uint32_t reserved_020[4]; volatile ahb_dma_out_int_chn_reg_t out_intr[2]; - uint32_t reserved_050[4]; - volatile ahb_dma_ahb_test_reg_t ahb_test; + uint32_t reserved_050[5]; volatile ahb_dma_misc_conf_reg_t misc_conf; volatile ahb_dma_date_reg_t date; uint32_t reserved_06c;