From 75cdc683fff1995e28896fbe99eaad39cdd5f068 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Thu, 4 Aug 2022 12:19:28 +0800 Subject: [PATCH] ulp: fix -Wformat errors in ULP tests --- components/ulp/test_apps/ulp_fsm/main/test_ulp.c | 6 +++--- components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c index 3fb527db6d..e3386e584f 100644 --- a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c +++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c @@ -342,7 +342,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") for (size_t i = 0; i < test_items_count; ++i) { const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low); const uint32_t not_mask = ~mask; - printf("#%2d: low: %2d width: %2d mask: %08x expected: %08x ", i, + printf("#%2d: low: %2d width: %2d mask: %08" PRIx32 " expected: %08" PRIx32 " ", i, test_items[i].low, test_items[i].width, mask, not_mask); @@ -377,7 +377,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") /* Verify the test results */ uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG); uint32_t set = REG_READ(RTC_CNTL_STORE1_REG); - printf("clear: %08x set: %08x\n", clear, set); + printf("clear: %08" PRIx32 " set: %08" PRIx32 "\n", clear, set); /* Restore initial calibration values */ REG_WRITE(RTC_CNTL_STORE0_REG, rtc_store0); @@ -548,7 +548,7 @@ TEST_CASE("ULP FSM timer setting", "[ulp]") uint32_t expected_counter = 1000000 / cycles_to_test[i]; uint32_t tolerance = (expected_counter * 15 / 100); tolerance = tolerance ? tolerance : 1; // Keep a tolerance of at least 1 count - printf("expected: %u\t tolerance: +/- %u\t actual: %u\n", expected_counter, tolerance, counter); + printf("expected: %" PRIu32 "\t tolerance: +/- %" PRIu32 "\t actual: %" PRIu32 "\n", expected_counter, tolerance, counter); // Should be within 15% TEST_ASSERT_INT_WITHIN(tolerance, expected_counter, counter); } diff --git a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c index bd304ce4fc..16c0211444 100644 --- a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c +++ b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c @@ -6,6 +6,7 @@ #include #include +#include #include "esp_sleep.h" #include "soc/rtc_cntl_reg.h" #include "soc/sens_reg.h" @@ -79,7 +80,7 @@ TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp]") /* Verify test data */ TEST_ASSERT(ulp_command_resp == RISCV_READ_WRITE_TEST); TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK); - printf("data out: 0x%X, expected: 0x%X \n", ulp_riscv_test_data_out, test_data); + printf("data out: 0x%" PRIx32 ", expected: 0x%" PRIx32 " \n", ulp_riscv_test_data_out, test_data); TEST_ASSERT(test_data == ulp_riscv_test_data_out); /* Clear test data */ @@ -139,7 +140,7 @@ static bool ulp_riscv_is_running(void) vTaskDelay((5 * ULP_WAKEUP_PERIOD / 1000) / portTICK_PERIOD_MS); uint32_t end_cnt = ulp_riscv_counter; - printf("start run count: %d, end run count %d\n", start_cnt, end_cnt); + printf("start run count: %" PRIu32 ", end run count %" PRIu32 "\n", start_cnt, end_cnt); /* If the ulp is running the counter should have been incremented */ return (start_cnt != end_cnt);