From ea6dd7344d012f93eafd87130af498671736610e Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Tue, 15 Oct 2024 13:04:05 +0800 Subject: [PATCH 1/2] fix(esp_hw_support): fix the issue of mmu table content loss due to default sd signal --- components/soc/esp32c5/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32c5/include/soc/soc_caps.h | 1 - 2 files changed, 5 deletions(-) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index f2cb4fe872..4cced7b65d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1379,10 +1379,6 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA bool default y -config SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD - bool - default y - config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index a6f586c172..4cef656a38 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -578,7 +578,6 @@ #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) -#define SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD (1) #define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1) #define SOC_PM_PAU_LINK_NUM (5) From 52bcb74b675c317784e2240917edd91aa7292f6e Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Tue, 15 Oct 2024 19:35:26 +0800 Subject: [PATCH 2/2] fix(esp_hw_support): fix the issue of wifi rx packet loss when switchng soc root clock source --- .../lowpower/port/esp32c5/sleep_clock.c | 18 +++++++++++++++++- .../esp_hw_support/port/esp32c5/rtc_clk.c | 3 ++- components/esp_system/port/soc/esp32c5/clk.c | 11 +++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c index d4a682ea3e..35a98164a7 100644 --- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c @@ -10,6 +10,8 @@ #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" #include "soc/i2c_ana_mst_reg.h" +#include "soc/chip_revision.h" +#include "hal/efuse_hal.h" static const char *TAG = "sleep_clock"; @@ -35,7 +37,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg) #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) { - /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master * command memory */ @@ -52,6 +53,21 @@ esp_err_t sleep_clock_system_retention_init(void *arg) } #endif +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP + /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's located + * in TOP domain) is used to fix the issue where the modem module fails + * to transmit and receive packets due to the loss of The modem root clock + * caused by automatic clock gating during soc root clock source switching. + * For detailed information, refer to IDF-11064 */ + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + const static sleep_retention_entries_config_t rootclk_workaround[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) } + }; + err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority"); + } +#endif + ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization"); return ESP_OK; } diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index 23a3941c9d..16bb71e007 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -268,7 +268,8 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - // ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M + /* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M + * For detailed information, refer to IDF-11064 */ source = SOC_CPU_CLK_SRC_PLL_F240M; source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; divider = 3; diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 6e62a960ed..4cec699c81 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -19,7 +19,9 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/i2s_reg.h" +#include "soc/chip_revision.h" #include "esp_cpu.h" +#include "hal/efuse_hal.h" #include "hal/wdt_hal.h" #if SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_lpcon_ll.h" @@ -215,6 +217,15 @@ __attribute__((weak)) void esp_perip_clk_init(void) modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); #endif + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix + * the issue where the modem module fails to transmit and receive packets + * due to the loss of the modem root clock caused by automatic clock gating + * during soc root clock source switching. For detailed information, refer + * to IDF-11064. */ + REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31)); + } + ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); #if 0 // TODO: [ESP32C5] IDF-8844 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;