mirror of
https://github.com/espressif/esp-idf
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Merge branch 'refactor/rng_ll_h2' into 'master'
rng: refactor to use hal/ll apis for esp32h2 Closes IDF-12462 See merge request espressif/esp-idf!36863
This commit is contained in:
Armando (Dou Yiwen)
commit
9184f62853
@ -1,94 +1,60 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/soc.h"
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#include "soc/pcr_reg.h"
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#include "soc/apb_saradc_reg.h"
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#include "soc/pmu_reg.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_saradc.h"
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#include "esp_log.h"
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static const uint32_t SAR2_CHANNEL = 9;
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static const uint32_t PATTERN_BIT_WIDTH = 6;
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static const uint32_t SAR1_ATTEN = 1;
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static const uint32_t SAR2_ATTEN = 1;
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#include "bootloader_random.h"
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#include "hal/regi2c_ctrl_ll.h"
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#include "hal/adc_ll.h"
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#include "hal/adc_types.h"
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void bootloader_random_enable(void)
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{
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REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
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REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
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REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
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REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
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// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
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REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
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REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
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adc_ll_reset_register();
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adc_ll_enable_bus_clock(true);
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adc_ll_enable_func_clock(true);
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adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
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adc_ll_digi_controller_clk_div(0, 0, 0);
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// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
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regi2c_ctrl_ll_i2c_periph_enable();
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// enable analog i2c master clock for RNG runtime
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ANALOG_CLOCK_ENABLE();
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
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adc_ll_set_dtest_param(0);
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adc_ll_set_ent_param(1);
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adc_ll_enable_tout_bus(ADC_UNIT_1, true);
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adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
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adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66);
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adc_digi_pattern_config_t pattern_config = {};
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pattern_config.atten = ADC_ATTEN_DB_2_5;
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adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
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pattern_config.unit = ADC_UNIT_2;
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pattern_config.atten = ADC_ATTEN_DB_2_5;
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pattern_config.channel = ADC_CHANNEL_1;
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adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
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// create patterns and set them in pattern table
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uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
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uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
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uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
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REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
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// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0);
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// Same as in C3
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
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// set timer expiry (timer is ADC_CTRL_CLK)
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REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
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// ENABLE_TIMER
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REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
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adc_ll_digi_set_clk_div(15);
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adc_ll_digi_set_trigger_interval(200);
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adc_ll_digi_trigger_enable();
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}
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void bootloader_random_disable(void)
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{
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// disable timer
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REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
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// Write reset value of this register
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REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
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// Revert ADC I2C configuration and initial voltage source setting
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
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adc_ll_digi_trigger_disable();
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adc_ll_digi_reset_pattern_table();
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adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
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adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
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adc_ll_set_dtest_param(0);
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adc_ll_set_ent_param(0);
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adc_ll_enable_tout_bus(ADC_UNIT_1, false);
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// disable analog i2c master clock
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ANALOG_CLOCK_DISABLE();
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// disable ADC_CTRL_CLK (SAR ADC function clock)
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REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
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// Set PCR_SARADC_CONF_REG to initial state
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REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
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adc_ll_digi_controller_clk_div(4, 0, 0);
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adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -224,6 +224,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
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}
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}
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/**
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* Rest pattern table to default value
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*/
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static inline void adc_ll_digi_reset_pattern_table(void)
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{
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APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = 0xffffff;
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APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = 0xffffff;
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}
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/**
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* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
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*
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@ -659,15 +668,57 @@ static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
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* @note Different ADC units and different attenuation options use different calibration data (initial data).
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*
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* @param adc_n ADC index number.
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* @param param calibration param
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*/
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__attribute__((always_inline))
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static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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uint8_t msb = param >> 8;
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uint8_t lsb = param & 0xFF;
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
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if (adc_n == ADC_UNIT_1) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
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} else {
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//H2 doesn't support ADC2, here is for backward compatibility for RNG
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
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}
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}
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/**
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* Set the SAR DTEST param
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*
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* @param param DTEST value
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*/
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__attribute__((always_inline))
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static inline void adc_ll_set_dtest_param(uint32_t param)
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{
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, param);
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}
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/**
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* Set the SAR ENT param
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*
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* @param param ENT value
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*/
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__attribute__((always_inline))
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static inline void adc_ll_set_ent_param(uint32_t param)
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{
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, param);
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}
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/**
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* Enable the SAR TOUT bus
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*
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* @param adc_n ADC index number.
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* @param en true for enable
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*/
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__attribute__((always_inline))
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static inline void adc_ll_enable_tout_bus(adc_unit_t adc_n, bool en)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, en);
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}
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/*---------------------------------------------------------------
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,6 +11,7 @@
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#include "soc/soc.h"
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#include "soc/regi2c_defs.h"
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#include "soc/i2c_ana_mst_reg.h"
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#include "soc/pmu_reg.h"
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#include "modem/modem_lpcon_struct.h"
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#ifdef __cplusplus
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@ -112,6 +113,22 @@ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
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SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
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}
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/**
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* @brief Enable regi2c controlled periph registers
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*/
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static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
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{
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
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}
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/**
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* @brief Disable regi2c controlled periph registers
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*/
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static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
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{
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CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -30,13 +30,21 @@
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#define ADC_SAR2_DREF_ADDR_MSB 0x6
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#define ADC_SAR2_DREF_ADDR_LSB 0x4
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define I2C_SARADC_TSENS_DAC 0x6
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#define I2C_SARADC_TSENS_DAC_MSB 3
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@ -54,22 +62,6 @@
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#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB 5
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#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB 5
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#define I2C_SARADC_SAR1_INIT_CODE_LSB 0
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#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB 7
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#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB 0
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#define I2C_SARADC_SAR1_INIT_CODE_MSB 1
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#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB 3
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#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB 0
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#define I2C_SARADC_SAR2_INIT_CODE_LSB 3
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#define I2C_SARADC_SAR2_INIT_CODE_LSB_MSB 7
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#define I2C_SARADC_SAR2_INIT_CODE_LSB_LSB 0
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#define I2C_SARADC_SAR2_INIT_CODE_MSB 4
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#define I2C_SARADC_SAR2_INIT_CODE_MSB_MSB 3
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#define I2C_SARADC_SAR2_INIT_CODE_MSB_LSB 0
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#define ADC_SAR1_ENCAL_GND_ADDR 0x8
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#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x1
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#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x1
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