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Merge branch 'ci/re_enable_i2s_pytest_exceptions_v5.4' into 'release/v5.4'

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ci(i2s): re-enable example pytest exceptions (v5.4)

See merge request espressif/esp-idf!36312
This commit is contained in:
morris 2025-01-11 22:13:32 +08:00
commit 93f91c4f0f
3 changed files with 50 additions and 54 deletions
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26
examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py
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@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0 # SPDX-License-Identifier: CC0-1.0
import pytest import pytest
from pytest_embedded import Dut from pytest_embedded import Dut
@ -21,14 +21,13 @@ from pytest_embedded import Dut
def test_i2s_pdm_tx_example(dut: Dut) -> None: def test_i2s_pdm_tx_example(dut: Dut) -> None:
dut.expect(r'I2S PDM TX example start', timeout=5) dut.expect(r'I2S PDM TX example start', timeout=5)
dut.expect(r'---------------------------', timeout=5) dut.expect(r'---------------------------', timeout=5)
# TODO: IDF-10007, reopen dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz '
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz ' r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5) dut.expect(r'i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5) dut.expect(r'i2s_common: i2s tx channel enabled', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', timeout=5)
dut.expect(r'Playing bass `twinkle twinkle little star`', timeout=5) dut.expect(r'Playing bass `twinkle twinkle little star`', timeout=5)
@ -44,11 +43,10 @@ def test_i2s_pdm_tx_example(dut: Dut) -> None:
def test_i2s_pdm_rx_example(dut: Dut) -> None: def test_i2s_pdm_rx_example(dut: Dut) -> None:
dut.expect(r'I2S PDM RX example start', timeout=5) dut.expect(r'I2S PDM RX example start', timeout=5)
dut.expect(r'---------------------------', timeout=5) dut.expect(r'---------------------------', timeout=5)
# TODO: IDF-10007, reopen dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_common: i2s rx channel enabled', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled', timeout=5)
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5) dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
dut.expect(r'-----------------------------------', timeout=5) dut.expect(r'-----------------------------------', timeout=5)
dut.expect(r'\[0\] ([-]?[0-9]+) \[1\] ([-]?[0-9]+) \[2\] ([-]?[0-9]+) \[3\] ([-]?[0-9]+)', timeout=5) dut.expect(r'\[0\] ([-]?[0-9]+) \[1\] ([-]?[0-9]+) \[2\] ([-]?[0-9]+) \[3\] ([-]?[0-9]+)', timeout=5)

39
examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py
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@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0 # SPDX-License-Identifier: CC0-1.0
import pytest import pytest
from pytest_embedded import Dut from pytest_embedded import Dut
@ -16,25 +16,24 @@ from pytest_embedded import Dut
@pytest.mark.generic @pytest.mark.generic
def test_i2s_basic_example(dut: Dut) -> None: def test_i2s_basic_example(dut: Dut) -> None:
# TODO: IDF-10007, reopen dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz ' r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5) dut.expect(r'i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz ' r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5) dut.expect(r'i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5) chan_enable_pattern = [
# chan_enable_pattern = [ r'i2s_common: i2s tx channel enabled',
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', r'i2s_common: i2s rx channel enabled'
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled' ]
# ] dut.expect(chan_enable_pattern, timeout=5)
# dut.expect(chan_enable_pattern, timeout=5) dut.expect(chan_enable_pattern, timeout=5)
# dut.expect(chan_enable_pattern, timeout=5)
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5) dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5) dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
dut.expect(r'-----------------------------------', timeout=5) dut.expect(r'-----------------------------------', timeout=5)

39
examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py
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@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD # SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0 # SPDX-License-Identifier: CC0-1.0
import pytest import pytest
from pytest_embedded import Dut from pytest_embedded import Dut
@ -14,25 +14,24 @@ from pytest_embedded import Dut
@pytest.mark.generic @pytest.mark.generic
def test_i2s_tdm_example(dut: Dut) -> None: def test_i2s_tdm_example(dut: Dut) -> None:
# TODO: IDF-10007, reopen dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz ' r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5) dut.expect(r'i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5) dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), ' r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5) dut.expect(r'i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz ' r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5) dut.expect(r'i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5) chan_enable_pattern = [
# chan_enable_pattern = [ r'i2s_common: i2s tx channel enabled',
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', r'i2s_common: i2s rx channel enabled'
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled' ]
# ] dut.expect(chan_enable_pattern, timeout=5)
# dut.expect(chan_enable_pattern, timeout=5) dut.expect(chan_enable_pattern, timeout=5)
# dut.expect(chan_enable_pattern, timeout=5)
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5) dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5) dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
dut.expect(r'-----------------------------------', timeout=5) dut.expect(r'-----------------------------------', timeout=5)