diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h index 69e625dc50..3cb3320a93 100644 --- a/components/esp_rom/include/esp32h2/rom/rtc.h +++ b/components/esp_rom/include/esp32h2/rom/rtc.h @@ -82,7 +82,6 @@ typedef enum { TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/ RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ - INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/ TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/ RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/ RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ @@ -90,11 +89,11 @@ typedef enum { RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ - GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ EFUSE_RESET = 20, /**<20, efuse reset digital core*/ USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */ USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */ POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/ + JTAG_CPU_RESET = 24, /**<24, jtag reset CPU*/ } RESET_REASON; // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h @@ -111,11 +110,11 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT"); ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1"); ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH"); ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC"); ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART"); ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG"); ESP_STATIC_ASSERT((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH"); +ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_CPU_RESET == RESET_REASON_CPU0_JTAG, "JTAG_CPU_RESET != RESET_REASON_CPU0_JTAG"); typedef enum { NO_SLEEP = 0, diff --git a/components/esp_system/include/esp_system.h b/components/esp_system/include/esp_system.h index 1354734875..ebf58972f8 100644 --- a/components/esp_system/include/esp_system.h +++ b/components/esp_system/include/esp_system.h @@ -35,6 +35,9 @@ typedef enum { ESP_RST_SDIO, //!< Reset over SDIO ESP_RST_USB, //!< Reset by USB peripheral ESP_RST_JTAG, //!< Reset by JTAG + ESP_RST_EFUSE, //!< Reset due to efuse error + ESP_RST_PWR_GLITCH, //!< Reset due to power glitch detected + ESP_RST_CPU_LOCKUP, //!< Reset due to CPU lock up } esp_reset_reason_t; /** diff --git a/components/esp_system/port/soc/esp32c6/reset_reason.c b/components/esp_system/port/soc/esp32c6/reset_reason.c index 6a5b4cedca..93c6812d16 100644 --- a/components/esp_system/port/soc/esp32c6/reset_reason.c +++ b/components/esp_system/port/soc/esp32c6/reset_reason.c @@ -54,6 +54,15 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, case RESET_REASON_CORE_USB_JTAG: return ESP_RST_USB; + case RESET_REASON_CORE_EFUSE_CRC: + return ESP_RST_EFUSE; + + case RESET_REASON_CPU0_JTAG: + return ESP_RST_JTAG; + + case RESET_REASON_CORE_SDIO: + return ESP_RST_SDIO; + default: return ESP_RST_UNKNOWN; } diff --git a/components/esp_system/port/soc/esp32h2/reset_reason.c b/components/esp_system/port/soc/esp32h2/reset_reason.c index e9f8f0b717..31b3976128 100644 --- a/components/esp_system/port/soc/esp32h2/reset_reason.c +++ b/components/esp_system/port/soc/esp32h2/reset_reason.c @@ -54,6 +54,15 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, case RESET_REASON_CORE_USB_JTAG: return ESP_RST_USB; + case RESET_REASON_CORE_EFUSE_CRC: + return ESP_RST_EFUSE; + + case RESET_REASON_CORE_PWR_GLITCH: + return ESP_RST_PWR_GLITCH; + + case RESET_REASON_CPU0_JTAG: + return ESP_RST_JTAG; + default: return ESP_RST_UNKNOWN; } diff --git a/components/soc/esp32c6/include/soc/reset_reasons.h b/components/soc/esp32c6/include/soc/reset_reasons.h index bd9831d5dd..b6b0e33ae3 100644 --- a/components/soc/esp32c6/include/soc/reset_reasons.h +++ b/components/soc/esp32c6/include/soc/reset_reasons.h @@ -23,7 +23,6 @@ extern "C" { #endif -// TODO: IDF-5719 /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter diff --git a/components/soc/esp32h2/include/soc/reset_reasons.h b/components/soc/esp32h2/include/soc/reset_reasons.h index dddfc94eef..24ce66c9a4 100644 --- a/components/soc/esp32h2/include/soc/reset_reasons.h +++ b/components/soc/esp32h2/include/soc/reset_reasons.h @@ -23,7 +23,6 @@ extern "C" { #endif -// ESP32H2-TODO: IDF-5719 Need update /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter @@ -31,7 +30,6 @@ extern "C" { typedef enum { RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip - RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core @@ -44,11 +42,11 @@ typedef enum { RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module - RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 } soc_reset_reason_t;