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https://github.com/espressif/esp-idf
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Merge branch 'fix/fix_modem_module_clock_missing_after_ota_v5.3' into 'release/v5.3'
fix(esp_system): deselect all modem modules lp clock source selection before clk initialization (v5.3) See merge request espressif/esp-idf!34924
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commit
a24dc94030
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -107,9 +107,15 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
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/**
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* @brief Disable lowpower clock source selection
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* @param module modem module
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*/
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void modem_clock_deselect_lp_clock_source(periph_module_t module);
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/**
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* @brief Disable all modem module's lowpower clock source selection
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*/
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void modem_clock_deselect_all_module_lp_clock_source(void);
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/**
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* @brief Reset wifi mac
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*/
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@ -346,6 +346,17 @@ void IRAM_ATTR modem_clock_module_disable(periph_module_t module)
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modem_clock_device_disable(MODEM_CLOCK_instance(), deps);
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}
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void modem_clock_deselect_all_module_lp_clock_source(void)
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{
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#if SOC_WIFI_SUPPORTED
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modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal);
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#endif
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#if SOC_BT_SUPPORTED
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modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal);
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#endif
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modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal);
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}
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void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpclk_src_t src, uint32_t divider)
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{
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assert(IS_MODEM_MODULE(module));
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@ -83,6 +83,7 @@ __attribute__((weak)) void esp_clk_init(void)
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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modem_clock_deselect_all_module_lp_clock_source();
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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@ -102,6 +102,7 @@ __attribute__((weak)) void esp_clk_init(void)
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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modem_clock_deselect_all_module_lp_clock_source();
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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@ -75,6 +75,7 @@ __attribute__((weak)) void esp_clk_init(void)
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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modem_clock_deselect_all_module_lp_clock_source();
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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@ -43,6 +43,7 @@
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#include "hal/temperature_sensor_ll.h"
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#include "hal/usb_serial_jtag_ll.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_modem_clock.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/esp_pmu.h"
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#include "esp_rom_uart.h"
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@ -101,6 +102,7 @@ __attribute__((weak)) void esp_clk_init(void)
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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modem_clock_deselect_all_module_lp_clock_source();
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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@ -1,6 +1,5 @@
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# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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# SPDX-License-Identifier: Apache-2.0
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import logging
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import pexpect
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@ -9,7 +8,7 @@ from common_test_methods import get_env_config_variable
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from pytest_embedded import Dut
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bad_event_str = [
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'bcn_timout',
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'bcn_timeout',
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'm f probe req l',
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'abort() was called',
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'Guru Meditation Error',
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@ -31,7 +30,7 @@ def _run_test(dut: Dut) -> None:
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pass
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try:
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dut.expect(r'got ip: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=20)
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dut.expect(r'got ip: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)
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log_after_got_ip = dut.expect(pexpect.TIMEOUT, timeout=10).decode()
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if any(s in log_after_got_ip for s in bad_event_str):
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logging.info('Abnormal connection log:')
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