diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index 2a837feb56..8240293bee 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -16,6 +16,12 @@ #include "hal/apm_hal.h" #endif +#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61! +#include "soc/hp_apm_reg.h" +#include "soc/lp_apm_reg.h" +#endif + + void bootloader_init_mem(void) { @@ -32,6 +38,13 @@ void bootloader_init_mem(void) #endif #endif +#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61! + // disable apm filter + REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); + REG_WRITE(HP_APM_FUNC_CTRL_REG, 0); +#endif + + #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE // protect memory region esp_cpu_configure_region_protection(); diff --git a/components/hal/esp32c5/include/hal/ahb_dma_ll.h b/components/hal/esp32c5/include/hal/ahb_dma_ll.h index 70ab227bcc..fc67d245bc 100644 --- a/components/hal/esp32c5/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c5/include/hal/ahb_dma_ll.h @@ -136,7 +136,7 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev) */ static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev) { - // AHB-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM + // AHB-DMA can access SRAM, ROM, MSPI Flash, MSPI PSRAM dev->intr_mem_start_addr.val = 0x40800000; dev->intr_mem_end_addr.val = 0x44000000; } diff --git a/components/hal/esp32c61/include/hal/ahb_dma_ll.h b/components/hal/esp32c61/include/hal/ahb_dma_ll.h new file mode 100644 index 0000000000..bd7a1c46a4 --- /dev/null +++ b/components/hal/esp32c61/include/hal/ahb_dma_ll.h @@ -0,0 +1,642 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "soc/soc_caps.h" +#include "hal/gdma_types.h" +#include "hal/assert.h" +#include "soc/ahb_dma_struct.h" +#include "soc/ahb_dma_reg.h" +#include "soc/soc_etm_source.h" +#include "soc/retention_periph_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id) + +#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL) + +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +// any "dummy" peripheral ID can be used for M2M mode +#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31) +#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0 +#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups +#define GDMA_LL_AHB_PAIRS_PER_GROUP 2 // Number of GDMA pairs in each AHB group + +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][2][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \ + }, \ + }}[group][chan][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][2][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \ + }, \ + }}[group][chan][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][2][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \ + }, \ + }}[group][chan][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][2][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \ + }, \ + }}[group][chan][task] + +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + +///////////////////////////////////// Common ///////////////////////////////////////// + +/** + * @brief Force enable register clock + */ +static inline void ahb_dma_ll_force_enable_reg_clock(ahb_dma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +/** + * @brief Disable priority arbitration + * + * @param dev DMA register base address + * @param dis True to disable, false to enable + */ +static inline void ahb_dma_ll_disable_prio_arb(ahb_dma_dev_t *dev, bool dis) +{ + dev->misc_conf.arb_pri_dis = dis; +} + +/** + * @brief Reset DMA FSM + * + * @param dev DMA register base address + */ +static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev) +{ + dev->misc_conf.ahbm_rst_inter = 1; + dev->misc_conf.ahbm_rst_inter = 0; +} + +/** + * @brief Preset valid memory range for AHB-DMA + * + * @param dev DMA register base address + */ +static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev) +{ + // AHB-DMA can access SRAM, ROM, MSPI Flash, MSPI PSRAM + dev->intr_mem_start_addr.val = 0x40800000; + dev->intr_mem_end_addr.val = 0x44000000; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= mask; + } else { + dev->in_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *ahb_dma_ll_rx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.in_check_owner_chn = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, always enabled + */ +static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable; +} + +/** + * @brief Set RX channel burst size + */ +static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = burst_mode; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.in_rst_chn = 1; + dev->channel[channel].in.in_conf0.in_rst_chn = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_rx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_rx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t ahb_dma_ll_rx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.infifo_cnt_chn; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.infifo_pop_chn = 1; + return dev->channel[channel].in.in_pop.infifo_rdata_chn; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->in_link_addr[channel].inlink_addr_chn = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_start(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_start_chn = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_stop(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_stop_chn = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_rx_restart(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_restart_chn = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void ahb_dma_ll_rx_enable_auto_return(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable; +} + +/** + * @brief Check if DMA RX descriptor FSM is in IDLE state + */ +static inline bool ahb_dma_ll_rx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.inlink_park_chn; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_error_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_rx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.rx_pri_chn = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id; + dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M); +} + +/** + * @brief Disconnect DMA RX channel from peripheral + */ +static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID; + dev->channel[channel].in.in_conf0.mem_trans_en_chn = false; +} + +/** + * @brief Whether to enable the ETM subsystem for RX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_etm_en_chn = enable; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void ahb_dma_ll_tx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= mask; + } else { + dev->out_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *ahb_dma_ll_tx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.out_check_owner_chn = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, always enabled + */ +static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable; +} + +/** + * @brief Set TX channel burst size + */ +static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz) +{ + uint8_t burst_mode = 0; + switch (sz) { + case 4: + burst_mode = 0; // single + break; + case 16: + burst_mode = 1; // incr4 + break; + case 32: + burst_mode = 2; // incr8 + break; + case 64: + burst_mode = 3; // incr16 + break; + default: + HAL_ASSERT(false); + break; + } + dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = burst_mode; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void ahb_dma_ll_tx_set_eof_mode(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.out_rst_chn = 1; + dev->channel[channel].out.out_conf0.out_rst_chn = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_tx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool ahb_dma_ll_tx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t ahb_dma_ll_tx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.outfifo_wdata_chn = data; + dev->channel[channel].out.out_push.outfifo_push_chn = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->out_link_addr[channel].outlink_addr_chn = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_start(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_start_chn = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_stop(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_stop_chn = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void ahb_dma_ll_tx_restart(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_restart_chn = 1; +} + +/** + * @brief Check if DMA TX descriptor FSM is in IDLE state + */ +static inline bool ahb_dma_ll_tx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.outlink_park_chn; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t ahb_dma_ll_tx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.tx_pri_chn = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + (void)periph; + dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id; +} + +/** + * @brief Disconnect DMA TX channel from peripheral + */ +static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = AHB_DMA_LL_INVALID_PERIPH_ID; +} + +/** + * @brief Whether to enable the ETM subsystem for TX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_etm_en_chn = enable; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c61/include/hal/gdma_ll.h b/components/hal/esp32c61/include/hal/gdma_ll.h new file mode 100644 index 0000000000..6f61062936 --- /dev/null +++ b/components/hal/esp32c61/include/hal/gdma_ll.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sdkconfig.h" +#include "soc/pcr_struct.h" +#include "hal/ahb_dma_ll.h" +#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the bus clock for the DMA module + */ +static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.gdma_conf.gdma_clk_en = enable; +} + +/** + * @brief Reset the DMA module + */ +static inline void gdma_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.gdma_conf.gdma_rst_en = 1; + PCR.gdma_conf.gdma_rst_en = 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/gdma_periph.c b/components/soc/esp32c61/gdma_periph.c new file mode 100644 index 0000000000..929f058a92 --- /dev/null +++ b/components/soc/esp32c61/gdma_periph.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" +#include "soc/ahb_dma_reg.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + } + } + } + } +}; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 05bad37ead..8381a1d1a4 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,14 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + config SOC_GPTIMER_SUPPORTED bool default y @@ -15,6 +23,10 @@ config SOC_USB_SERIAL_JTAG_SUPPORTED bool default y +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + config SOC_SUPPORTS_SECURE_DL_MODE bool default y @@ -163,6 +175,22 @@ config SOC_CPU_PMP_REGION_GRANULARITY int default 128 +config SOC_DMA_CAN_ACCESS_FLASH + bool + default y + +config SOC_AHB_GDMA_VERSION + int + default 2 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 2 + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32c61/include/soc/gdma_reg.h b/components/soc/esp32c61/include/soc/ahb_dma_reg.h similarity index 100% rename from components/soc/esp32c61/include/soc/gdma_reg.h rename to components/soc/esp32c61/include/soc/ahb_dma_reg.h diff --git a/components/soc/esp32c61/include/soc/gdma_struct.h b/components/soc/esp32c61/include/soc/ahb_dma_struct.h similarity index 83% rename from components/soc/esp32c61/include/soc/gdma_struct.h rename to components/soc/esp32c61/include/soc/ahb_dma_struct.h index a758496aef..d6cbfa3097 100644 --- a/components/soc/esp32c61/include/soc/gdma_struct.h +++ b/components/soc/esp32c61/include/soc/ahb_dma_struct.h @@ -455,53 +455,6 @@ typedef union { uint32_t val; } gdma_in_link_chn_reg_t; -/** Type of out_conf0_ch0 register - * Configuration register 0 of TX channel 0 - */ -typedef union { - struct { - /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0: - * Release reset\\1: Reset\\ - */ - uint32_t out_rst_ch0:1; - /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t out_loop_test_ch0:1; - /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable automatic outlink write-back when all the data - * in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\ - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; - * Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated - * when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for - * TX channel 0 is generated when data to be transmitted has been popped from FIFO in - * AHB_DMA.\\ - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable INCR burst transfer for TX channel 0 reading - * descriptors.\\0: Disable\\1: Enable\\ - */ - uint32_t outdscr_burst_en_ch0:1; - uint32_t reserved_5:1; - /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1: - * Enable\\ - */ - uint32_t out_etm_en_ch0:1; - uint32_t reserved_7:1; - /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: - * incr8\\ 2'b11: incr16\\ - */ - uint32_t out_data_burst_mode_sel_ch0:2; - uint32_t reserved_10:22; - }; - uint32_t val; -} gdma_out_conf0_ch0_reg_t; /** Type of out_conf1_chn register * Configuration register 1 of TX channel 0 @@ -627,7 +580,7 @@ typedef union { uint32_t reserved_4:28; }; uint32_t val; -} gdma_tx_ch_arb_weigh_chn_reg_t; +} ahb_dma_tx_ch_arb_weigh_chn_reg_t; /** Type of tx_arb_weigh_opt_dir_chn register * TX channel 0 weight arbitration optimization enable register @@ -641,7 +594,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} gdma_tx_arb_weigh_opt_dir_chn_reg_t; +} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t; /** Type of rx_ch_arb_weigh_chn register * RX channel 0 arbitration weight configuration register @@ -655,7 +608,7 @@ typedef union { uint32_t reserved_4:28; }; uint32_t val; -} gdma_rx_ch_arb_weigh_chn_reg_t; +} ahb_dma_rx_ch_arb_weigh_chn_reg_t; /** Type of rx_arb_weigh_opt_dir_chn register * RX channel 0 weight arbitration optimization enable register @@ -669,7 +622,7 @@ typedef union { uint32_t reserved_1:31; }; uint32_t val; -} gdma_rx_arb_weigh_opt_dir_chn_reg_t; +} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; /** Type of in_link_addr_chn register * Link list descriptor address configuration of RX channel 0 @@ -682,7 +635,7 @@ typedef union { uint32_t inlink_addr_chn:32; }; uint32_t val; -} gdma_in_link_addr_chn_reg_t; +} ahb_dma_in_link_addr_chn_reg_t; /** Type of out_link_addr_chn register * Link list descriptor address configuration of TX channel 0 @@ -695,7 +648,7 @@ typedef union { uint32_t outlink_addr_chn:32; }; uint32_t val; -} gdma_out_link_addr_chn_reg_t; +} ahb_dma_out_link_addr_chn_reg_t; /** Type of intr_mem_start_addr register * Accessible address space start address configuration register @@ -838,7 +791,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gdma_infifo_status_chn_reg_t; +} ahb_dma_infifo_status_chn_reg_t; /** Type of in_state_chn register * Receive status of RX channel 0 @@ -861,7 +814,7 @@ typedef union { uint32_t reserved_23:9; }; uint32_t val; -} gdma_in_state_chn_reg_t; +} ahb_dma_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register * Receive descriptor address when EOF occurs on RX channel 0 @@ -875,7 +828,7 @@ typedef union { uint32_t in_suc_eof_des_addr_chn:32; }; uint32_t val; -} gdma_in_suc_eof_des_addr_chn_reg_t; +} ahb_dma_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register * Receive descriptor address when errors occur of RX channel 0 @@ -889,7 +842,7 @@ typedef union { uint32_t in_err_eof_des_addr_chn:32; }; uint32_t val; -} gdma_in_err_eof_des_addr_chn_reg_t; +} ahb_dma_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register * Current receive descriptor address of RX channel 0 @@ -1158,109 +1111,97 @@ typedef union { uint32_t val; } gdma_out_peri_sel_chn_reg_t; +typedef struct { + volatile gdma_in_int_raw_chn_reg_t raw; + volatile gdma_in_int_st_chn_reg_t st; + volatile gdma_in_int_ena_chn_reg_t ena; + volatile gdma_in_int_clr_chn_reg_t clr; +} gdma_in_int_chn_reg_t; typedef struct { - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + volatile gdma_out_int_raw_chn_reg_t raw; + volatile gdma_out_int_st_chn_reg_t st; + volatile gdma_out_int_ena_chn_reg_t ena; + volatile gdma_out_int_clr_chn_reg_t clr; +} gdma_out_int_chn_reg_t; + + +typedef struct { + volatile gdma_in_conf0_chn_reg_t in_conf0; + volatile gdma_in_conf1_chn_reg_t in_conf1; + volatile ahb_dma_infifo_status_chn_reg_t infifo_status; + volatile gdma_in_pop_chn_reg_t in_pop; + volatile gdma_in_link_chn_reg_t in_link; + volatile ahb_dma_in_state_chn_reg_t in_state; + volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile gdma_in_dscr_chn_reg_t in_dscr; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile gdma_in_pri_chn_reg_t in_pri; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; +} gdma_in_chn_reg_t; + +typedef struct { + volatile gdma_out_conf0_chn_reg_t out_conf0; + volatile gdma_out_conf1_chn_reg_t out_conf1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status; + volatile gdma_out_push_chn_reg_t out_push; + volatile gdma_out_link_chn_reg_t out_link; + volatile gdma_out_state_chn_reg_t out_state; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile gdma_out_dscr_chn_reg_t out_dscr; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile gdma_out_pri_chn_reg_t out_pri; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; +} gdma_out_chn_reg_t; + +typedef struct { + volatile gdma_in_chn_reg_t in; + // uint32_t reserved_in[11]; // volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0; + uint32_t reserved_in1[3]; + volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_chn; + uint32_t reserved_in2[7]; + volatile gdma_out_chn_reg_t out; + // uint32_t reserved_out[11]; // volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0; + uint32_t reserved_out1[3]; + volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_chn; + uint32_t reserved_out2[7]; +} gdma_chn_reg_t; + + +typedef struct { + uint32_t reserved[8]; + ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh; + ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; +} ahb_dma_out_crc_arb_chn_reg_t; + +typedef struct { + uint32_t reserved[8]; + ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh; + ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; +} ahb_dma_in_crc_arb_chn_reg_t; + +typedef struct { + volatile gdma_in_int_chn_reg_t in_intr[2]; uint32_t reserved_020[4]; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + volatile gdma_out_int_chn_reg_t out_intr[2]; uint32_t reserved_050[4]; volatile gdma_ahb_test_reg_t ahb_test; volatile gdma_misc_conf_reg_t misc_conf; volatile gdma_date_reg_t date; uint32_t reserved_06c; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; - volatile gdma_in_pop_chn_reg_t in_pop_ch0; - volatile gdma_in_link_chn_reg_t in_link_ch0; - volatile gdma_in_state_chn_reg_t in_state_ch0; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile gdma_in_pri_chn_reg_t in_pri_ch0; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; - uint32_t reserved_0a4[3]; - volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0; - uint32_t reserved_0b4[7]; - volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile gdma_out_push_chn_reg_t out_push_ch0; - volatile gdma_out_link_chn_reg_t out_link_ch0; - volatile gdma_out_state_chn_reg_t out_state_ch0; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile gdma_out_pri_chn_reg_t out_pri_ch0; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; - uint32_t reserved_104[3]; - volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0; - uint32_t reserved_114[7]; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; - volatile gdma_in_pop_chn_reg_t in_pop_ch1; - volatile gdma_in_link_chn_reg_t in_link_ch1; - volatile gdma_in_state_chn_reg_t in_state_ch1; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile gdma_in_pri_chn_reg_t in_pri_ch1; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; - uint32_t reserved_164[3]; - volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch1; - uint32_t reserved_174[7]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile gdma_out_push_chn_reg_t out_push_ch1; - volatile gdma_out_link_chn_reg_t out_link_ch1; - volatile gdma_out_state_chn_reg_t out_state_ch1; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile gdma_out_pri_chn_reg_t out_pri_ch1; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; - uint32_t reserved_1c4[3]; - volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch1; - uint32_t reserved_1d4[66]; - volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch0; - volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch0; - uint32_t reserved_2e4[8]; - volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch1; - volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch1; - uint32_t reserved_30c[18]; - volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch0; - volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch0; - uint32_t reserved_35c[8]; - volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch1; - volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch1; + volatile gdma_chn_reg_t channel[2]; + uint32_t reserved_1d4[51]; + volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2]; + uint32_t reserved_30c[10]; + volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[2]; uint32_t reserved_384[10]; - volatile gdma_in_link_addr_chn_reg_t in_link_addr_chn[2]; + volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[2]; uint32_t reserved_3b4; - volatile gdma_out_link_addr_chn_reg_t out_link_addr_chn[2]; + volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[2]; uint32_t reserved_3c0; volatile gdma_intr_mem_start_addr_reg_t intr_mem_start_addr; volatile gdma_intr_mem_end_addr_reg_t intr_mem_end_addr; @@ -1268,12 +1209,12 @@ typedef struct { volatile gdma_arb_timeout_rx_reg_t arb_timeout_rx; volatile gdma_weight_en_tx_reg_t weight_en_tx; volatile gdma_weight_en_rx_reg_t weight_en_rx; -} gdma_dev_t; +} ahb_dma_dev_t; -extern gdma_dev_t GDMA; +extern ahb_dma_dev_t AHB_DMA; #ifndef __cplusplus -_Static_assert(sizeof(gdma_dev_t) == 0x3dc, "Invalid size of gdma_dev_t structure"); +_Static_assert(sizeof(ahb_dma_dev_t) == 0x3dc, "Invalid size of ahb_dma_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/soc/gdma_channel.h b/components/soc/esp32c61/include/soc/gdma_channel.h index dd3f635e54..e1e6e87bd0 100644 --- a/components/soc/esp32c61/include/soc/gdma_channel.h +++ b/components/soc/esp32c61/include/soc/gdma_channel.h @@ -5,3 +5,22 @@ */ #pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) + +// On which system bus is the DMA instance of the peripheral connection mounted +#define SOC_GDMA_BUS_ANY (-1) +#define SOC_GDMA_BUS_AHB (0) + +#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY +#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 097e03db2f..243c2a7771 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -36,7 +36,7 @@ #define DR_REG_HP_SYSTEM_BASE 0x60095000 #define DR_REG_PCR_BASE 0x60096000 #define DR_REG_TEE_REG_BASE 0x60098000 -#define DR_REG_HP_APM_REG_BASE 0x60099000 +#define DR_REG_HP_APM_BASE 0x60099000 #define DR_REG_MISC_BASE 0x6009F000 #define DR_REG_MODEM0_BASE 0x600A0000 #define DR_REG_MODEM1_BASE 0x600AC000 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 2b2e8e4747..14fc26394a 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -20,13 +20,13 @@ // \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 // \#define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321 #define SOC_UART_SUPPORTED 1 -// \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 -// \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 // \#define SOC_BT_SUPPORTED 1 // \#define SOC_IEEE802154_SUPPORTED 1 -// \#define SOC_ASYNC_MEMCPY_SUPPORTED 1 //TODO: [ESP32C61] IDF-9315 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 // \#define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322 // \#define SOC_WIFI_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 @@ -143,13 +143,15 @@ #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 #define SOC_CPU_PMP_REGION_GRANULARITY 128 // TODO IDF-9580 check when doing PMP bringup +/*-------------------------- DMA Common CAPS ----------------------------------------*/ +#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */ -//TODO: [ESP32C61] IDF-9310 /*-------------------------- GDMA CAPS -------------------------------------*/ -// \#define SOC_AHB_GDMA_VERSION 1U -// \#define SOC_GDMA_NUM_GROUPS_MAX 1U -// \#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +#define SOC_AHB_GDMA_VERSION 2U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 2 +// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9964 +// \#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-10380 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32c61/include/soc/soc_etm_source.h b/components/soc/esp32c61/include/soc/soc_etm_source.h index cd7bcec1a9..3d1ea6e397 100644 --- a/components/soc/esp32c61/include/soc/soc_etm_source.h +++ b/components/soc/esp32c61/include/soc/soc_etm_source.h @@ -92,33 +92,24 @@ #define RTC_EVT_TICK 84 #define RTC_EVT_OVF 85 #define RTC_EVT_CMP 86 -#define GDMA_AHB_EVT_IN_DONE_CH0 87 -#define GDMA_AHB_EVT_IN_DONE_CH1 88 -#define GDMA_AHB_EVT_IN_DONE_CH2 89 -#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 90 -#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 91 -#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 92 -#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 93 -#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 94 -#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 95 -#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 96 -#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 97 -#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 98 -#define GDMA_AHB_EVT_OUT_DONE_CH0 99 -#define GDMA_AHB_EVT_OUT_DONE_CH1 100 -#define GDMA_AHB_EVT_OUT_DONE_CH2 101 -#define GDMA_AHB_EVT_OUT_EOF_CH0 102 -#define GDMA_AHB_EVT_OUT_EOF_CH1 103 -#define GDMA_AHB_EVT_OUT_EOF_CH2 104 -#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 105 -#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 106 -#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 107 -#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 108 -#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 109 -#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 110 -#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 111 -#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 112 -#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 113 +#define GDMA_EVT_IN_DONE_CH0 87 +#define GDMA_EVT_IN_DONE_CH1 88 +#define GDMA_EVT_IN_SUC_EOF_CH0 90 +#define GDMA_EVT_IN_SUC_EOF_CH1 91 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 93 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 94 +#define GDMA_EVT_IN_FIFO_FULL_CH0 96 +#define GDMA_EVT_IN_FIFO_FULL_CH1 97 +#define GDMA_EVT_OUT_DONE_CH0 99 +#define GDMA_EVT_OUT_DONE_CH1 100 +#define GDMA_EVT_OUT_EOF_CH0 102 +#define GDMA_EVT_OUT_EOF_CH1 103 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 105 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 106 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 108 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 109 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 111 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 112 #define PMU_EVT_SLEEP_WEEKUP 114 #define GPIO_TASK_CH0_SET 1 #define GPIO_TASK_CH1_SET 2 @@ -244,10 +235,8 @@ #define RTC_TASK_STOP 122 #define RTC_TASK_CLR 123 #define RTC_TASK_TRIGGERFLW 124 -#define GDMA_AHB_TASK_IN_START_CH0 125 -#define GDMA_AHB_TASK_IN_START_CH1 126 -#define GDMA_AHB_TASK_IN_START_CH2 127 -#define GDMA_AHB_TASK_OUT_START_CH0 128 -#define GDMA_AHB_TASK_OUT_START_CH1 129 -#define GDMA_AHB_TASK_OUT_START_CH2 130 +#define GDMA_TASK_IN_START_CH0 125 +#define GDMA_TASK_IN_START_CH1 126 +#define GDMA_TASK_OUT_START_CH0 128 +#define GDMA_TASK_OUT_START_CH1 129 #define PMU_TASK_SLEEP_REQ 131 diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index e57aeaa7f7..289c95dd0e 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -21,7 +21,7 @@ PROVIDE ( INTMTX = 0x60010000 ); PROVIDE ( SOC_ETM = 0x60013000 ); PROVIDE ( PVT_MONITOR = 0x60019000 ); PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); -PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( AHB_DMA = 0x60080000 ); PROVIDE ( GPSPI2 = 0x60081000 ); PROVIDE ( SHA = 0x60089000 ); PROVIDE ( ECC = 0x6008B000 );