diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index 2a837feb56..2c428b7b0f 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,14 +12,12 @@ #include "bootloader_mem.h" #include "esp_cpu.h" -#if SOC_APM_SUPPORTED #include "hal/apm_hal.h" -#endif void bootloader_init_mem(void) { -#if !defined(BOOTLOADER_BUILD) && defined(SOC_APM_SUPPORTED) +#if !defined(BOOTLOADER_BUILD) /* By default, these access path filters are enable and allow the * access to masters only if they are in TEE mode. Since all masters * except HP CPU boots in REE mode, default setting of these filters diff --git a/components/hal/esp32h21/include/hal/gdma_ll.h b/components/hal/esp32h21/include/hal/gdma_ll.h new file mode 100644 index 0000000000..bf145e4778 --- /dev/null +++ b/components/hal/esp32h21/include/hal/gdma_ll.h @@ -0,0 +1,586 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "hal/gdma_types.h" +#include "soc/gdma_struct.h" +#include "soc/gdma_reg.h" +#include "soc/soc_etm_source.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) + +#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +// any "dummy" peripheral ID can be used for M2M mode +#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32) +#define GDMA_LL_INVALID_PERIPH_ID (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0 +#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups +#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group + +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 +#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1 + +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \ + }}}[group][chan][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \ + }}}[group][chan][task] + +///////////////////////////////////// Common ///////////////////////////////////////// + +/** + * @brief Enable the bus clock for the DMA module + */ +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.gdma_conf.gdma_clk_en = enable; +} + +#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the DMA module + */ +static inline void _gdma_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.gdma_conf.gdma_rst_en = 1; + PCR.gdma_conf.gdma_rst_en = 0; +} + +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + +/** + * @brief Force enable register clock + */ +static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->in_intr[channel].raw.val; + } else { + return dev->in_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= mask; + } else { + dev->in_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.in_check_owner_chn = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, disabled by default + */ +static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_data_burst_en_chn = enable; +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.in_rst_chn = 1; + dev->channel[channel].in.in_conf0.in_rst_chn = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.infifo_cnt_chn; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.infifo_pop_chn = 1; + return dev->channel[channel].in.in_pop.infifo_rdata_chn; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].in.in_link.inlink_addr_chn = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_start_chn = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_stop_chn = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_restart_chn = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable; +} + +/** + * @brief Check if DMA RX descriptor FSM is in IDLE state + */ +static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.inlink_park_chn; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.rx_pri_chn = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id; + dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M); +} + +/** + * @brief Disconnect DMA RX channel from peripheral + */ +static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID; + dev->channel[channel].in.in_conf0.mem_trans_en_chn = false; +} + +/** + * @brief Whether to enable the ETM subsystem for RX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_etm_en_chn = enable; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw) +{ + if (raw) { + return dev->out_intr[channel].raw.val; + } else { + return dev->out_intr[channel].st.val; + } +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= mask; + } else { + dev->out_intr[channel].ena.val &= ~mask; + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = mask; +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.out_check_owner_chn = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, disabled by default + */ +static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_data_burst_en_chn = enable; +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.out_rst_chn = 1; + dev->channel[channel].out.out_conf0.out_rst_chn = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.outfifo_wdata_chn = data; + dev->channel[channel].out.out_push.outfifo_push_chn = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].out.out_link.outlink_addr_chn = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_start_chn = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_stop_chn = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_restart_chn = 1; +} + +/** + * @brief Check if DMA TX descriptor FSM is in IDLE state + */ +static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.outlink_park_chn; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr.val; +} + +/** + * @brief Get the pre-fetched TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.tx_pri_chn = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) +{ + (void)periph; + dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id; +} + +/** + * @brief Disconnect DMA TX channel from peripheral + */ +static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID; +} + +/** + * @brief Whether to enable the ETM subsystem for TX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_etm_en_chn = enable; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/apm_hal.h b/components/hal/include/hal/apm_hal.h index 94898df37c..2e1c64178f 100644 --- a/components/hal/include/hal/apm_hal.h +++ b/components/hal/include/hal/apm_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -250,7 +250,17 @@ int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); #endif //CONFIG_IDF_TARGET_ESP32P4 -#endif //SOC_APM_SUPPORTED +#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED +#include "soc/hp_apm_reg.h" +#include "soc/lp_apm_reg.h" +#include "soc/lp_apm0_reg.h" + +#define apm_hal_apm_ctrl_filter_enable_all(en) \ + REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ + REG_WRITE(LP_APM0_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ + REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); + +#endif #ifdef __cplusplus } diff --git a/components/soc/esp32h21/gdma_periph.c b/components/soc/esp32h21/gdma_periph.c new file mode 100644 index 0000000000..720fa30370 --- /dev/null +++ b/components/soc/esp32h21/gdma_periph.c @@ -0,0 +1,123 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" +#include "soc/gdma_reg.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE, + } + } + } + } +}; + +#if SOC_PAU_SUPPORTED +/* GDMA Channel (Group0, Pair0) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG + GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG + GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +*/ +#define G0P0_RETENTION_REGS_CNT 13 +#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG +static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \ + G0P0_RETENTION_REGS_CNT, 0, 0, \ + g0p0_regs_map[0], g0p0_regs_map[1], \ + g0p0_regs_map[2], g0p0_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair1) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG + GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG + GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +*/ +#define G0P1_RETENTION_REGS_CNT 13 +#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG +static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \ + G0P1_RETENTION_REGS_CNT, 0, 0, \ + g0p1_regs_map[0], g0p1_regs_map[1], \ + g0p1_regs_map[2], g0p1_regs_map[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +/* GDMA Channel (Group0, Pair2) Registers Context + Include: GDMA_MISC_CONF_REG / + GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG + GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG + GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG +*/ +#define G0P2_RETENTION_REGS_CNT_0 6 +#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG +#define G0P2_RETENTION_REGS_CNT_1 7 +#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG +static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0}; +static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ + G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + g0p2_regs_map0[0], g0p2_regs_map0[1], \ + g0p2_regs_map0[2], g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ + G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + g0p2_regs_map1[0], g0p2_regs_map1[1], \ + g0p2_regs_map1[2], g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } + } +}; +#endif diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 8552d04128..057b6fe38d 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_AHB_GDMA_SUPPORTED + bool + default y + config SOC_GPTIMER_SUPPORTED bool default y +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -215,6 +227,10 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US int default 1100 +config SOC_AHB_GDMA_VERSION + int + default 1 + config SOC_GDMA_NUM_GROUPS_MAX int default 1 @@ -223,6 +239,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 3 +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32h21/include/soc/gdma_channel.h b/components/soc/esp32h21/include/soc/gdma_channel.h index ff0217ffe0..1d04e5f917 100644 --- a/components/soc/esp32h21/include/soc/gdma_channel.h +++ b/components/soc/esp32h21/include/soc/gdma_channel.h @@ -1,5 +1,30 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ + +#pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) +#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9) + +// On which system bus is the DMA instance of the peripheral connection mounted +#define SOC_GDMA_BUS_ANY (-1) +#define SOC_GDMA_BUS_AHB (0) + +#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY +#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 8fa9630b31..e0d6386421 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -21,13 +21,13 @@ // #define SOC_ANA_CMPR_SUPPORTED 1 // #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11621 #define SOC_UART_SUPPORTED 1 -// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 -// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 // #define SOC_BT_SUPPORTED 1 // #define SOC_IEEE802154_SUPPORTED 1 // #define SOC_IEEE802154_BLE_ONLY 1 -// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11616 // #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32H21] IDF-11624 // #define SOC_SUPPORTS_SECURE_DL_MODE 1 @@ -176,11 +176,11 @@ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ -// #define SOC_AHB_GDMA_VERSION 1U +#define SOC_AHB_GDMA_VERSION 1U #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-11604 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32h21/register/soc/gdma_struct.h b/components/soc/esp32h21/register/soc/gdma_struct.h index abb3738f67..b18bb6eb7e 100644 --- a/components/soc/esp32h21/register/soc/gdma_struct.h +++ b/components/soc/esp32h21/register/soc/gdma_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -472,48 +472,48 @@ typedef union { uint32_t val; } gdma_in_link_chn_reg_t; -/** Type of out_conf0_ch0 register - * Configure 0 register of Tx channel 0. +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel n. */ typedef union { struct { - /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. */ - uint32_t out_rst_ch0:1; - /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t out_loop_test_ch0:1; - /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; * Set this bit to enable automatic outlink-writeback when all the data in tx buffer * has been transmitted. */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is * generated when data need to transmit has been popped from FIFO in DMA */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link * descriptor when accessing internal SRAM. */ - uint32_t outdscr_burst_en_ch0:1; - /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data * when accessing internal SRAM. */ - uint32_t out_data_burst_en_ch0:1; - /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm * task. */ - uint32_t out_etm_en_ch0:1; + uint32_t out_etm_en_chn:1; uint32_t reserved_7:25; }; uint32_t val; -} gdma_out_conf0_ch0_reg_t; +} gdma_out_conf0_chn_reg_t; /** Type of out_conf1_chn register * Configure 1 register of Tx channel n. @@ -580,49 +580,6 @@ typedef union { uint32_t val; } gdma_out_link_chn_reg_t; -/** Type of out_conf0_chn register - * Configure 0 register of Tx channel n. - */ -typedef union { - struct { - /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. - */ - uint32_t out_rst_chn:1; - /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_chn:1; - /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in tx buffer - * has been transmitted. - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is - * generated when data need to transmit has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_chn:1; - /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_chn:1; - /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm - * task. - */ - uint32_t out_etm_en_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} gdma_out_conf0_chn_reg_t; - /** Group: Version Registers */ /** Type of date register @@ -966,123 +923,73 @@ typedef union { typedef struct { - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; - volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; - volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; - volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; - volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; - volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; - volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; - volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; - volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; + volatile gdma_in_int_raw_chn_reg_t raw; + volatile gdma_in_int_st_chn_reg_t st; + volatile gdma_in_int_ena_chn_reg_t ena; + volatile gdma_in_int_clr_chn_reg_t clr; +} gdma_in_int_chn_reg_t; + +typedef struct { + volatile gdma_out_int_raw_chn_reg_t raw; + volatile gdma_out_int_st_chn_reg_t st; + volatile gdma_out_int_ena_chn_reg_t ena; + volatile gdma_out_int_clr_chn_reg_t clr; +} gdma_out_int_chn_reg_t; + +typedef struct { + volatile gdma_in_conf0_chn_reg_t in_conf0; + volatile gdma_in_conf1_chn_reg_t in_conf1; + volatile gdma_infifo_status_chn_reg_t infifo_status; + volatile gdma_in_pop_chn_reg_t in_pop; + volatile gdma_in_link_chn_reg_t in_link; + volatile gdma_in_state_chn_reg_t in_state; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile gdma_in_dscr_chn_reg_t in_dscr; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile gdma_in_pri_chn_reg_t in_pri; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; +} gdma_in_chn_reg_t; + +typedef struct { + volatile gdma_out_conf0_chn_reg_t out_conf0; + volatile gdma_out_conf1_chn_reg_t out_conf1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status; + volatile gdma_out_push_chn_reg_t out_push; + volatile gdma_out_link_chn_reg_t out_link; + volatile gdma_out_state_chn_reg_t out_state; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile gdma_out_dscr_chn_reg_t out_dscr; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile gdma_out_pri_chn_reg_t out_pri; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; +} gdma_out_chn_reg_t; + +typedef struct { + volatile gdma_in_chn_reg_t in; + uint32_t reserved_in[11]; + volatile gdma_out_chn_reg_t out; + uint32_t reserved_out[11]; +} gdma_chn_reg_t; + + +typedef struct gdma_dev_s { + volatile gdma_in_int_chn_reg_t in_intr[3]; + volatile gdma_out_int_chn_reg_t out_intr[3]; volatile gdma_ahb_test_reg_t ahb_test; volatile gdma_misc_conf_reg_t misc_conf; volatile gdma_date_reg_t date; uint32_t reserved_06c; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; - volatile gdma_in_pop_chn_reg_t in_pop_ch0; - volatile gdma_in_link_chn_reg_t in_link_ch0; - volatile gdma_in_state_chn_reg_t in_state_ch0; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile gdma_in_pri_chn_reg_t in_pri_ch0; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; - uint32_t reserved_0a4[11]; - volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile gdma_out_push_chn_reg_t out_push_ch0; - volatile gdma_out_link_chn_reg_t out_link_ch0; - volatile gdma_out_state_chn_reg_t out_state_ch0; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile gdma_out_pri_chn_reg_t out_pri_ch0; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; - uint32_t reserved_104[11]; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; - volatile gdma_in_pop_chn_reg_t in_pop_ch1; - volatile gdma_in_link_chn_reg_t in_link_ch1; - volatile gdma_in_state_chn_reg_t in_state_ch1; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile gdma_in_pri_chn_reg_t in_pri_ch1; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; - uint32_t reserved_164[11]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile gdma_out_push_chn_reg_t out_push_ch1; - volatile gdma_out_link_chn_reg_t out_link_ch1; - volatile gdma_out_state_chn_reg_t out_state_ch1; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile gdma_out_pri_chn_reg_t out_pri_ch1; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; - uint32_t reserved_1c4[11]; - volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; - volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; - volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; - volatile gdma_in_pop_chn_reg_t in_pop_ch2; - volatile gdma_in_link_chn_reg_t in_link_ch2; - volatile gdma_in_state_chn_reg_t in_state_ch2; - volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; - volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; - volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; - volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; - volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; - volatile gdma_in_pri_chn_reg_t in_pri_ch2; - volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; - uint32_t reserved_224[11]; - volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; - volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; - volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; - volatile gdma_out_push_chn_reg_t out_push_ch2; - volatile gdma_out_link_chn_reg_t out_link_ch2; - volatile gdma_out_state_chn_reg_t out_state_ch2; - volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; - volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; - volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; - volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; - volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; - volatile gdma_out_pri_chn_reg_t out_pri_ch2; - volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; + volatile gdma_chn_reg_t channel[3]; } gdma_dev_t; extern gdma_dev_t GDMA; #ifndef __cplusplus -_Static_assert(sizeof(gdma_dev_t) == 0x284, "Invalid size of gdma_dev_t structure"); +_Static_assert(sizeof(gdma_dev_t) == 0x2B0, "Invalid size of gdma_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/hp_apm_reg.h b/components/soc/esp32h21/register/soc/hp_apm_reg.h index a01b49f9d7..e9fc59ad47 100644 --- a/components/soc/esp32h21/register/soc/hp_apm_reg.h +++ b/components/soc/esp32h21/register/soc/hp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** HP_APM_REGION_FILTER_EN_REG register * Region filter enable register */ -#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_BASE + 0x0) +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) /** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; * Region filter enable */ @@ -26,7 +26,7 @@ extern "C" { /** HP_APM_REGION0_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_BASE + 0x4) +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) /** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region0 */ @@ -38,7 +38,7 @@ extern "C" { /** HP_APM_REGION0_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_BASE + 0x8) +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) /** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region0 */ @@ -50,7 +50,7 @@ extern "C" { /** HP_APM_REGION0_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_BASE + 0xc) +#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) /** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -118,7 +118,7 @@ extern "C" { /** HP_APM_REGION1_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_BASE + 0x10) +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) /** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region1 */ @@ -130,7 +130,7 @@ extern "C" { /** HP_APM_REGION1_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_BASE + 0x14) +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) /** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region1 */ @@ -142,7 +142,7 @@ extern "C" { /** HP_APM_REGION1_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_BASE + 0x18) +#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) /** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -210,7 +210,7 @@ extern "C" { /** HP_APM_REGION2_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_BASE + 0x1c) +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) /** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region2 */ @@ -222,7 +222,7 @@ extern "C" { /** HP_APM_REGION2_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_BASE + 0x20) +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) /** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region2 */ @@ -234,7 +234,7 @@ extern "C" { /** HP_APM_REGION2_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_BASE + 0x24) +#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) /** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -302,7 +302,7 @@ extern "C" { /** HP_APM_REGION3_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_BASE + 0x28) +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) /** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region3 */ @@ -314,7 +314,7 @@ extern "C" { /** HP_APM_REGION3_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_BASE + 0x2c) +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) /** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region3 */ @@ -326,7 +326,7 @@ extern "C" { /** HP_APM_REGION3_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_BASE + 0x30) +#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) /** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -394,7 +394,7 @@ extern "C" { /** HP_APM_REGION4_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_BASE + 0x34) +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) /** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region4 */ @@ -406,7 +406,7 @@ extern "C" { /** HP_APM_REGION4_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_BASE + 0x38) +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) /** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region4 */ @@ -418,7 +418,7 @@ extern "C" { /** HP_APM_REGION4_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_BASE + 0x3c) +#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) /** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -486,7 +486,7 @@ extern "C" { /** HP_APM_REGION5_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_BASE + 0x40) +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) /** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region5 */ @@ -498,7 +498,7 @@ extern "C" { /** HP_APM_REGION5_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_BASE + 0x44) +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) /** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region5 */ @@ -510,7 +510,7 @@ extern "C" { /** HP_APM_REGION5_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_BASE + 0x48) +#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) /** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -578,7 +578,7 @@ extern "C" { /** HP_APM_REGION6_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_BASE + 0x4c) +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) /** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region6 */ @@ -590,7 +590,7 @@ extern "C" { /** HP_APM_REGION6_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_BASE + 0x50) +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) /** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region6 */ @@ -602,7 +602,7 @@ extern "C" { /** HP_APM_REGION6_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_BASE + 0x54) +#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) /** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -670,7 +670,7 @@ extern "C" { /** HP_APM_REGION7_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_BASE + 0x58) +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) /** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region7 */ @@ -682,7 +682,7 @@ extern "C" { /** HP_APM_REGION7_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_BASE + 0x5c) +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) /** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region7 */ @@ -694,7 +694,7 @@ extern "C" { /** HP_APM_REGION7_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_BASE + 0x60) +#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) /** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -762,7 +762,7 @@ extern "C" { /** HP_APM_REGION8_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_BASE + 0x64) +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) /** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region8 */ @@ -774,7 +774,7 @@ extern "C" { /** HP_APM_REGION8_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_BASE + 0x68) +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) /** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region8 */ @@ -786,7 +786,7 @@ extern "C" { /** HP_APM_REGION8_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_BASE + 0x6c) +#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) /** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -854,7 +854,7 @@ extern "C" { /** HP_APM_REGION9_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_BASE + 0x70) +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) /** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region9 */ @@ -866,7 +866,7 @@ extern "C" { /** HP_APM_REGION9_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_BASE + 0x74) +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) /** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region9 */ @@ -878,7 +878,7 @@ extern "C" { /** HP_APM_REGION9_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_BASE + 0x78) +#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) /** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -946,7 +946,7 @@ extern "C" { /** HP_APM_REGION10_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_BASE + 0x7c) +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) /** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region10 */ @@ -958,7 +958,7 @@ extern "C" { /** HP_APM_REGION10_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_BASE + 0x80) +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) /** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region10 */ @@ -970,7 +970,7 @@ extern "C" { /** HP_APM_REGION10_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_BASE + 0x84) +#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) /** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1038,7 +1038,7 @@ extern "C" { /** HP_APM_REGION11_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_BASE + 0x88) +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) /** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region11 */ @@ -1050,7 +1050,7 @@ extern "C" { /** HP_APM_REGION11_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_BASE + 0x8c) +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) /** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region11 */ @@ -1062,7 +1062,7 @@ extern "C" { /** HP_APM_REGION11_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_BASE + 0x90) +#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) /** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1130,7 +1130,7 @@ extern "C" { /** HP_APM_REGION12_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_BASE + 0x94) +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) /** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region12 */ @@ -1142,7 +1142,7 @@ extern "C" { /** HP_APM_REGION12_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_BASE + 0x98) +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) /** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region12 */ @@ -1154,7 +1154,7 @@ extern "C" { /** HP_APM_REGION12_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_BASE + 0x9c) +#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) /** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1222,7 +1222,7 @@ extern "C" { /** HP_APM_REGION13_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_BASE + 0xa0) +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) /** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region13 */ @@ -1234,7 +1234,7 @@ extern "C" { /** HP_APM_REGION13_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_BASE + 0xa4) +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) /** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region13 */ @@ -1246,7 +1246,7 @@ extern "C" { /** HP_APM_REGION13_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_BASE + 0xa8) +#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) /** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1314,7 +1314,7 @@ extern "C" { /** HP_APM_REGION14_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_BASE + 0xac) +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) /** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region14 */ @@ -1326,7 +1326,7 @@ extern "C" { /** HP_APM_REGION14_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_BASE + 0xb0) +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) /** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region14 */ @@ -1338,7 +1338,7 @@ extern "C" { /** HP_APM_REGION14_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_BASE + 0xb4) +#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) /** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1406,7 +1406,7 @@ extern "C" { /** HP_APM_REGION15_ADDR_START_REG register * Region address register */ -#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_BASE + 0xb8) +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) /** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region15 */ @@ -1418,7 +1418,7 @@ extern "C" { /** HP_APM_REGION15_ADDR_END_REG register * Region address register */ -#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_BASE + 0xbc) +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) /** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region15 */ @@ -1430,7 +1430,7 @@ extern "C" { /** HP_APM_REGION15_PMS_ATTR_REG register * Region access authority attribute register */ -#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_BASE + 0xc0) +#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) /** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -1498,7 +1498,7 @@ extern "C" { /** HP_APM_FUNC_CTRL_REG register * PMS function control register */ -#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_BASE + 0xc4) +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) /** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; * PMS M0 function enable */ @@ -1531,7 +1531,7 @@ extern "C" { /** HP_APM_M0_STATUS_REG register * M0 status register */ -#define HP_APM_M0_STATUS_REG (DR_REG_HP_BASE + 0xc8) +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) /** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -1543,7 +1543,7 @@ extern "C" { /** HP_APM_M0_STATUS_CLR_REG register * M0 status clear register */ -#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_BASE + 0xcc) +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) /** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -1555,7 +1555,7 @@ extern "C" { /** HP_APM_M0_EXCEPTION_INFO0_REG register * M0 exception_info0 register */ -#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xd0) +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) /** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Exception region */ @@ -1581,7 +1581,7 @@ extern "C" { /** HP_APM_M0_EXCEPTION_INFO1_REG register * M0 exception_info1 register */ -#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xd4) +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) /** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -1593,7 +1593,7 @@ extern "C" { /** HP_APM_M1_STATUS_REG register * M1 status register */ -#define HP_APM_M1_STATUS_REG (DR_REG_HP_BASE + 0xd8) +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) /** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -1605,7 +1605,7 @@ extern "C" { /** HP_APM_M1_STATUS_CLR_REG register * M1 status clear register */ -#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_BASE + 0xdc) +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) /** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -1617,7 +1617,7 @@ extern "C" { /** HP_APM_M1_EXCEPTION_INFO0_REG register * M1 exception_info0 register */ -#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xe0) +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) /** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Exception region */ @@ -1643,7 +1643,7 @@ extern "C" { /** HP_APM_M1_EXCEPTION_INFO1_REG register * M1 exception_info1 register */ -#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xe4) +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) /** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -1655,7 +1655,7 @@ extern "C" { /** HP_APM_M2_STATUS_REG register * M2 status register */ -#define HP_APM_M2_STATUS_REG (DR_REG_HP_BASE + 0xe8) +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) /** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -1667,7 +1667,7 @@ extern "C" { /** HP_APM_M2_STATUS_CLR_REG register * M2 status clear register */ -#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_BASE + 0xec) +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) /** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -1679,7 +1679,7 @@ extern "C" { /** HP_APM_M2_EXCEPTION_INFO0_REG register * M2 exception_info0 register */ -#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xf0) +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) /** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Exception region */ @@ -1705,7 +1705,7 @@ extern "C" { /** HP_APM_M2_EXCEPTION_INFO1_REG register * M2 exception_info1 register */ -#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xf4) +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) /** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -1717,7 +1717,7 @@ extern "C" { /** HP_APM_M3_STATUS_REG register * M3 status register */ -#define HP_APM_M3_STATUS_REG (DR_REG_HP_BASE + 0xf8) +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) /** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -1729,7 +1729,7 @@ extern "C" { /** HP_APM_M3_STATUS_CLR_REG register * M3 status clear register */ -#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_BASE + 0xfc) +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) /** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -1741,7 +1741,7 @@ extern "C" { /** HP_APM_M3_EXCEPTION_INFO0_REG register * M3 exception_info0 register */ -#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0x100) +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) /** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; * Exception region */ @@ -1767,7 +1767,7 @@ extern "C" { /** HP_APM_M3_EXCEPTION_INFO1_REG register * M3 exception_info1 register */ -#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0x104) +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) /** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -1779,7 +1779,7 @@ extern "C" { /** HP_APM_INT_EN_REG register * APM interrupt enable register */ -#define HP_APM_INT_EN_REG (DR_REG_HP_BASE + 0x108) +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) /** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; * APM M0 interrupt enable */ @@ -1812,7 +1812,7 @@ extern "C" { /** HP_APM_CLOCK_GATE_REG register * clock gating register */ -#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_BASE + 0x10c) +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) /** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * reg_clk_en */ @@ -1824,7 +1824,7 @@ extern "C" { /** HP_APM_DATE_REG register * Version register */ -#define HP_APM_DATE_REG (DR_REG_HP_BASE + 0x7fc) +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) /** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; * reg_date */ diff --git a/components/soc/esp32h21/register/soc/lp_apm0_reg.h b/components/soc/esp32h21/register/soc/lp_apm0_reg.h index 17220e50a9..bd164990ad 100644 --- a/components/soc/esp32h21/register/soc/lp_apm0_reg.h +++ b/components/soc/esp32h21/register/soc/lp_apm0_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** LP_APM0_REGION_FILTER_EN_REG register * Region filter enable register */ -#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) /** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; * Region filter enable */ @@ -26,7 +26,7 @@ extern "C" { /** LP_APM0_REGION0_ADDR_START_REG register * Region address register */ -#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) /** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region0 */ @@ -38,7 +38,7 @@ extern "C" { /** LP_APM0_REGION0_ADDR_END_REG register * Region address register */ -#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) /** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region0 */ @@ -50,7 +50,7 @@ extern "C" { /** LP_APM0_REGION0_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) /** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -118,7 +118,7 @@ extern "C" { /** LP_APM0_REGION1_ADDR_START_REG register * Region address register */ -#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) /** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region1 */ @@ -130,7 +130,7 @@ extern "C" { /** LP_APM0_REGION1_ADDR_END_REG register * Region address register */ -#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) /** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region1 */ @@ -142,7 +142,7 @@ extern "C" { /** LP_APM0_REGION1_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) /** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -210,7 +210,7 @@ extern "C" { /** LP_APM0_REGION2_ADDR_START_REG register * Region address register */ -#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_BASE + 0x1c) +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) /** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region2 */ @@ -222,7 +222,7 @@ extern "C" { /** LP_APM0_REGION2_ADDR_END_REG register * Region address register */ -#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_BASE + 0x20) +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) /** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region2 */ @@ -234,7 +234,7 @@ extern "C" { /** LP_APM0_REGION2_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_BASE + 0x24) +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) /** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -302,7 +302,7 @@ extern "C" { /** LP_APM0_REGION3_ADDR_START_REG register * Region address register */ -#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_BASE + 0x28) +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) /** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region3 */ @@ -314,7 +314,7 @@ extern "C" { /** LP_APM0_REGION3_ADDR_END_REG register * Region address register */ -#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_BASE + 0x2c) +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) /** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region3 */ @@ -326,7 +326,7 @@ extern "C" { /** LP_APM0_REGION3_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_BASE + 0x30) +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) /** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -394,7 +394,7 @@ extern "C" { /** LP_APM0_FUNC_CTRL_REG register * PMS function control register */ -#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) /** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; * PMS M0 function enable */ @@ -406,7 +406,7 @@ extern "C" { /** LP_APM0_M0_STATUS_REG register * M0 status register */ -#define LP_APM0_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) /** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -418,7 +418,7 @@ extern "C" { /** LP_APM0_M0_STATUS_CLR_REG register * M0 status clear register */ -#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) /** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -430,7 +430,7 @@ extern "C" { /** LP_APM0_M0_EXCEPTION_INFO0_REG register * M0 exception_info0 register */ -#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) /** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; * Exception region */ @@ -456,7 +456,7 @@ extern "C" { /** LP_APM0_M0_EXCEPTION_INFO1_REG register * M0 exception_info1 register */ -#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) /** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -468,7 +468,7 @@ extern "C" { /** LP_APM0_INT_EN_REG register * APM interrupt enable register */ -#define LP_APM0_INT_EN_REG (DR_REG_LP_BASE + 0xd8) +#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) /** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; * APM M0 interrupt enable */ @@ -480,7 +480,7 @@ extern "C" { /** LP_APM0_CLOCK_GATE_REG register * clock gating register */ -#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xdc) +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) /** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; * reg_clk_en */ @@ -492,7 +492,7 @@ extern "C" { /** LP_APM0_DATE_REG register * Version register */ -#define LP_APM0_DATE_REG (DR_REG_LP_BASE + 0x7fc) +#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) /** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; * reg_date */ diff --git a/components/soc/esp32h21/register/soc/lp_apm_reg.h b/components/soc/esp32h21/register/soc/lp_apm_reg.h index 6e433906e1..f223057773 100644 --- a/components/soc/esp32h21/register/soc/lp_apm_reg.h +++ b/components/soc/esp32h21/register/soc/lp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** LP_APM_REGION_FILTER_EN_REG register * Region filter enable register */ -#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) /** LP_APM_REGION_FILTER_EN : R/W; bitpos: [1:0]; default: 1; * Region filter enable */ @@ -26,7 +26,7 @@ extern "C" { /** LP_APM_REGION0_ADDR_START_REG register * Region address register */ -#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) /** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region0 */ @@ -38,7 +38,7 @@ extern "C" { /** LP_APM_REGION0_ADDR_END_REG register * Region address register */ -#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) /** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region0 */ @@ -50,7 +50,7 @@ extern "C" { /** LP_APM_REGION0_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) /** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -118,7 +118,7 @@ extern "C" { /** LP_APM_REGION1_ADDR_START_REG register * Region address register */ -#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) /** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; * Start address of region1 */ @@ -130,7 +130,7 @@ extern "C" { /** LP_APM_REGION1_ADDR_END_REG register * Region address register */ -#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) /** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; * End address of region1 */ @@ -142,7 +142,7 @@ extern "C" { /** LP_APM_REGION1_PMS_ATTR_REG register * Region access authority attribute register */ -#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) /** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; * Region execute authority in REE_MODE0 */ @@ -210,7 +210,7 @@ extern "C" { /** LP_APM_FUNC_CTRL_REG register * PMS function control register */ -#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) /** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; * PMS M0 function enable */ @@ -222,7 +222,7 @@ extern "C" { /** LP_APM_M0_STATUS_REG register * M0 status register */ -#define LP_APM_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) /** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Exception status */ @@ -234,7 +234,7 @@ extern "C" { /** LP_APM_M0_STATUS_CLR_REG register * M0 status clear register */ -#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) /** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; * Clear exception status */ @@ -246,7 +246,7 @@ extern "C" { /** LP_APM_M0_EXCEPTION_INFO0_REG register * M0 exception_info0 register */ -#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) /** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [1:0]; default: 0; * Exception region */ @@ -272,7 +272,7 @@ extern "C" { /** LP_APM_M0_EXCEPTION_INFO1_REG register * M0 exception_info1 register */ -#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) /** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; * Exception addr */ @@ -284,7 +284,7 @@ extern "C" { /** LP_APM_INT_EN_REG register * APM interrupt enable register */ -#define LP_APM_INT_EN_REG (DR_REG_LP_BASE + 0xe8) +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) /** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; * APM M0 interrupt enable */ @@ -296,7 +296,7 @@ extern "C" { /** LP_APM_CLOCK_GATE_REG register * clock gating register */ -#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xec) +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) /** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * reg_clk_en */ @@ -308,7 +308,7 @@ extern "C" { /** LP_APM_DATE_REG register * Version register */ -#define LP_APM_DATE_REG (DR_REG_LP_BASE + 0xfc) +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) /** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35680864; * reg_date */ diff --git a/docs/docs_not_updated/esp32h21.txt b/docs/docs_not_updated/esp32h21.txt index 0da5cb4a43..8d2168e493 100644 --- a/docs/docs_not_updated/esp32h21.txt +++ b/docs/docs_not_updated/esp32h21.txt @@ -253,7 +253,6 @@ api-reference/system/wdts.rst api-reference/system/sleep_modes.rst api-reference/system/system_time.rst api-reference/system/himem.rst -api-reference/system/async_memcpy.rst api-reference/system/console.rst api-reference/system/internal-unstable.rst api-reference/system/ulp_instruction_set.rst