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https://github.com/espressif/esp-idf
synced 2025-03-12 10:39:11 -04:00
Merge branch 'bugfix/fix_iram_handler_call_inline_func' into 'release/v4.1'
Bugfix/fix iram handler call inline function uart_ll_is_tx_idle in flash (v4.1) See merge request espressif/esp-idf!9951
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commit
a4c72cfa28
@ -19,6 +19,7 @@
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#pragma once
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#include "hal/uart_types.h"
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#include "soc/uart_periph.h"
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#include "esp_attr.h"
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// The default fifo depth
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#define UART_LL_FIFO_DEF_LEN (UART_FIFO_LEN)
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@ -96,7 +97,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val |= mask;
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}
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@ -109,7 +110,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return None
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*/
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static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val &= (~mask);
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}
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@ -121,7 +122,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return The UART interrupt status.
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*/
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static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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{
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return hw->int_st.val;
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}
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@ -134,7 +135,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_clr.val = mask;
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}
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@ -160,7 +161,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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{
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//Get the UART APB fifo addr. Read fifo, we use APB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
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@ -178,7 +179,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
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*
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* @return None
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*/
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static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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{
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//Get the UART AHB fifo addr, Write fifo, we use AHB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : (hw == &UART1) ? UART_FIFO_AHB_REG(1) : UART_FIFO_AHB_REG(2);
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@ -194,7 +195,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
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*
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* @return None
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*/
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static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
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{
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//Hardware issue: we can not use `rxfifo_rst` to reset the hw rxfifo.
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uint16_t fifo_cnt;
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@ -260,7 +261,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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*
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* @return The data length of txfifo can be written.
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*/
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static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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{
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return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
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}
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@ -424,7 +425,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint8_t tout_thr)
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*
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* @return None.
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*/
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static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
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FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
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{
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if(break_num > 0) {
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hw->idle_conf.tx_brk_num = break_num;
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@ -515,7 +516,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
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*
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* @return None.
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*/
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static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
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FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
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{
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hw->at_cmd_char.data = cmd_char->cmd_char;
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hw->at_cmd_char.char_num = cmd_char->char_num;
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@ -558,7 +559,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
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*
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* @return None.
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*/
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static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
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FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
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{
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hw->conf0.sw_rts = level & 0x1;
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}
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@ -740,7 +741,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
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*
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* @return The bit mode.
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*/
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static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
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FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
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{
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*data_bit = hw->conf0.bit_num;
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}
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@ -752,7 +753,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
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*
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* @return True if the state machine is in the IDLE state, otherwise false is returned.
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*/
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static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
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FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
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{
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typeof(hw->status) status = hw->status;
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return ((status.txfifo_cnt == 0) && (status.st_utx_out == 0));
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