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Merge branch 'bugfix/frc1_timer_clear' into 'master'

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newlib: fix register used for DPORT/RTC bug workaround

While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to
peripheral address space wraparound this write actually affected one of
FRC2 registers, which is used by WiFi stack to implement legacy
ets_timer APIs.
This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to
known value safely.

See merge request !449
This commit is contained in:
Ivan Grokhotkov 2017-01-19 10:17:36 +08:00
commit a6b163c954
1 changed files with 2 additions and 3 deletions
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components/newlib/time.c
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@ -85,9 +85,8 @@ static void IRAM_ATTR frc_timer_isr()
{
// Write to FRC_TIMER_INT_REG may not take effect in some cases (root cause TBD)
// This extra write works around this issue.
// There is no register at DR_REG_FRC_TIMER_BASE + 0x60 (in fact, any DPORT register address can be used).
WRITE_PERI_REG(DR_REG_FRC_TIMER_BASE + 0x60, 0xabababab);
// Clear interrupt status
// FRC_TIMER_LOAD_REG(0) is used here, but any other DPORT register address can also be used.
WRITE_PERI_REG(FRC_TIMER_LOAD_REG(0), FRC_TIMER_LOAD_VALUE(0));
WRITE_PERI_REG(FRC_TIMER_INT_REG(0), FRC_TIMER_INT_CLR);
s_microseconds += FRC1_ISR_PERIOD_US;
}