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Merge branch 'bugfix/flash_encryption_v4.2' into 'release/v4.2'

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ota: fix ota with flash encryption(backport v4.2)

See merge request espressif/esp-idf!12701
This commit is contained in:
Jiang Jiang Jian 2021-03-18 04:09:45 +00:00
commit aafcc2ca60
6 changed files with 88 additions and 0 deletions
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1
components/esp_rom/include/esp32/rom/spi_flash.h
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@ -124,6 +124,7 @@ extern "C" {
//Extra dummy for flash read
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2

2
components/spi_flash/esp32/flash_ops_esp32.c
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@ -32,6 +32,7 @@ static inline void IRAM_ATTR spi_flash_guard_end(void)
}
}
extern void IRAM_ATTR flash_rom_init(void);
esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
{
const uint8_t *ssrc = (const uint8_t *)src;
@ -73,6 +74,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
}
spi_flash_guard_start();
flash_rom_init();
rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32);
spi_flash_guard_end();
if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {

2
components/spi_flash/esp32s2/flash_ops_esp32s2.c
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@ -29,6 +29,7 @@ static const char *TAG = "spiflash_s2";
#define SPICACHE SPIMEM0
#define SPIFLASH SPIMEM1
extern void IRAM_ATTR flash_rom_init(void);
esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
{
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
@ -68,6 +69,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
if (ops && ops->start) {
ops->start();
}
flash_rom_init();
rc = SPI_Encrypt_Write(dest_addr, src, size);
if (ops && ops->end) {
ops->end();

61
components/spi_flash/flash_ops.c
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@ -462,6 +462,67 @@ out:
}
#endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL
#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
extern uint8_t g_rom_spiflash_dummy_len_plus[];
void IRAM_ATTR flash_rom_init(void)
{
uint32_t freqdiv = 0;
#if CONFIG_IDF_TARGET_ESP32
uint32_t dummy_bit = 0;
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
#endif
#endif//CONFIG_IDF_TARGET_ESP32
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
freqdiv = 1;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
freqdiv = 2;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
freqdiv = 3;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
freqdiv = 4;
#endif
#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
esp_rom_spiflash_read_mode_t read_mode;
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
read_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_DIO
read_mode = ESP_ROM_SPIFLASH_DIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#endif
#endif //!CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32
g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
#else
spi_dummy_len_fix(1, freqdiv);
#endif //CONFIG_IDF_TARGET_ESP32
#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
spi_common_set_dummy_output(read_mode);
#endif //!CONFIG_IDF_TARGET_ESP32S2
esp_rom_spiflash_config_clk(freqdiv, 1);
}
#else
void IRAM_ATTR flash_rom_init(void)
{
return;
}
#endif // !CONFIG_SPI_FLASH_USE_LEGACY_IMPL
esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
{

8
tools/ci/config/target-test.yml
View File

@ -484,6 +484,14 @@ UT_020:
- Example_SPI_Multi_device
- psram
UT_021:
extends: .unit_test_template
parallel: 2
tags:
- ESP32_IDF
- psram
- UT_T1_FlashEncryption
UT_022:
extends: .unit_test_template
tags:

14
tools/unit-test-app/configs/flash_encryption_psram Normal file
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@ -0,0 +1,14 @@
# This config is for ESP32 only (no ESP32-S2/S3 flash encryption support yet, ESP32-C3 has no psram)
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=spi_flash
TEST_GROUPS=flash_encryption
CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
CONFIG_SECURE_BOOT_ALLOW_JTAG=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y