From 49826c241bf5db59574dff118d0a6096bb767664 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 11 Dec 2024 16:24:36 +0800 Subject: [PATCH 1/3] fix(spi_flash): fixed no_os flash API not consider cache states issue on h2/p4/c6/c5/c61 --- components/spi_flash/spi_flash_os_func_noos.c | 91 ++----------------- 1 file changed, 8 insertions(+), 83 deletions(-) diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index 78bdc4bc85..6843269e15 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -8,76 +8,21 @@ #include "sdkconfig.h" #include "esp_flash.h" #include "esp_attr.h" - #include "esp_rom_sys.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/ets_sys.h" -#include "esp32s3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/ets_sys.h" -#include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C2 -#include "esp32c2/rom/ets_sys.h" -#include "esp32c2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C6 -#include "esp32c6/rom/ets_sys.h" -#include "esp32c6/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C61 //TODO: IDF-9526, refactor this -#include "esp32c61/rom/ets_sys.h" -#include "esp32c61/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C5 -#include "esp32c5/rom/ets_sys.h" -#include "esp32c5/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H2 -#include "esp32h2/rom/ets_sys.h" -#include "esp32h2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32P4 -#include "esp32p4/rom/ets_sys.h" -#include "esp32p4/rom/cache.h" -#endif - -#include "esp_attr.h" - -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 -typedef struct { - uint32_t icache_autoload; - uint32_t dcache_autoload; -} spi_noos_arg_t; - -static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 -typedef struct { - uint32_t icache_autoload; -} spi_noos_arg_t; - -static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#endif +#include "rom/cache.h" +#include "hal/cache_hal.h" +#include "hal/cache_ll.h" +#include "soc/soc_caps.h" static IRAM_ATTR esp_err_t start(void *arg) { #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Read_Disable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_ICache(); - spi_arg->dcache_autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_ICache(); -#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_Cache(); -#elif CONFIG_IDF_TARGET_ESP32P4 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_L2_Cache(); #else - abort(); + cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif + return ESP_OK; } @@ -86,26 +31,10 @@ static IRAM_ATTR esp_err_t end(void *arg) #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); Cache_Read_Enable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_ICache_All(); - Cache_Resume_ICache(spi_arg->icache_autoload); - Cache_Resume_DCache(spi_arg->dcache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_ICache_All(); - Cache_Resume_ICache(spi_arg->icache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_All(); - Cache_Resume_Cache(spi_arg->icache_autoload); -#elif CONFIG_IDF_TARGET_ESP32P4 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_All(CACHE_MAP_L2_CACHE); - Cache_Resume_L2_Cache(spi_arg->icache_autoload); #else - abort(); + cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif + return ESP_OK; } @@ -137,9 +66,5 @@ esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip) { chip->os_func = &esp_flash_noos_functions; -#if !CONFIG_IDF_TARGET_ESP32 - chip->os_func_data = &spi_arg; -#endif - return ESP_OK; } From 8c8f8836e5f5a2cff2abf104f7678cc83ca72128 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 11 Dec 2024 16:26:59 +0800 Subject: [PATCH 2/3] fix(spi_flash): fixed no_os flash API not consider branch predictor on c5/c61 --- components/spi_flash/spi_flash_os_func_noos.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index 6843269e15..a2f83f47cc 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -9,6 +9,7 @@ #include "esp_flash.h" #include "esp_attr.h" #include "esp_rom_sys.h" +#include "esp_cpu.h" #include "rom/cache.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" @@ -16,6 +17,11 @@ static IRAM_ATTR esp_err_t start(void *arg) { +#if SOC_BRANCH_PREDICTOR_SUPPORTED + //branch predictor will start cache request as well + esp_cpu_branch_prediction_disable(); +#endif + #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Read_Disable(1); @@ -35,6 +41,10 @@ static IRAM_ATTR esp_err_t end(void *arg) cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif +#if SOC_BRANCH_PREDICTOR_SUPPORTED + esp_cpu_branch_prediction_enable(); +#endif + return ESP_OK; } From 4a9fb951cf0e5fb17802d36ff38c18c8883d955e Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 16 Dec 2024 11:53:33 +0800 Subject: [PATCH 3/3] fix(cache): fixed cache hal ctx not initialised in app issue --- components/esp_system/port/cpu_start.c | 7 ++++++- components/hal/esp32/cache_hal_esp32.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 6e1a0ceda7..cad5d291ac 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -41,7 +41,6 @@ #include "soc/assist_debug_reg.h" #include "soc/system_reg.h" #include "esp32s3/rom/opi_flash.h" -#include "hal/cache_hal.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" #include "esp32c3/rom/cache.h" @@ -95,6 +94,7 @@ #include "esp_private/sleep_gpio.h" #include "hal/wdt_hal.h" #include "soc/rtc.h" +#include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "hal/efuse_ll.h" #include "soc/periph_defs.h" @@ -454,6 +454,11 @@ void IRAM_ATTR call_start_cpu0(void) do_multicore_settings(); #endif +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + //cache hal ctx needs to be initialised + cache_hal_init(); +#endif + // When the APP is loaded into ram for execution, some hardware initialization behaviors // in the bootloader are still necessary #if CONFIG_APP_BUILD_TYPE_RAM diff --git a/components/hal/esp32/cache_hal_esp32.c b/components/hal/esp32/cache_hal_esp32.c index 33a7b1fb26..b4f48fde26 100644 --- a/components/hal/esp32/cache_hal_esp32.c +++ b/components/hal/esp32/cache_hal_esp32.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,11 @@ static uint32_t s_cache_status[2]; +void cache_hal_init(void) +{ + //for compatibility +} + /** * On ESP32, The cache_hal_suspend()/cache_hal_resume() are replacements * for Cache_Read_Disable()/Cache_Read_Enable() in ROM.