From e58becec0ab5a230009308239c4eb59db9bb1eb2 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 30 Aug 2023 18:12:42 +0800 Subject: [PATCH] feat(esp-system): support reset reasons on P4 --- .../src/esp32p4/bootloader_esp32p4.c | 9 ++- components/esp_rom/include/esp32p4/rom/rtc.h | 70 +++++++++---------- components/esp_system/.build-test-rules.yml | 3 - components/esp_system/include/esp_system.h | 1 + .../port/soc/esp32p4/reset_reason.c | 28 ++++---- .../esp_system_unity_tests/README.md | 4 +- .../main/CMakeLists.txt | 6 +- .../main/test_reset_reason.c | 42 +++++++++-- .../esp_system_unity_tests/main/test_sleep.c | 4 ++ .../soc/esp32p4/include/soc/reset_reasons.h | 38 +++++----- 10 files changed, 121 insertions(+), 84 deletions(-) diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index ddab8547e1..085ab34559 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -64,14 +64,17 @@ static void bootloader_check_wdt_reset(void) { int wdt_rst = 0; soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 || - rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) { - ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); + if (rst_reason == RESET_REASON_SYS_HP_WDT || rst_reason == RESET_REASON_SYS_LP_WDT || rst_reason == RESET_REASON_CORE_HP_WDT || + rst_reason == RESET_REASON_CORE_LP_WDT || rst_reason == RESET_REASON_CHIP_LP_WDT) { + ESP_LOGW(TAG, "CPU has been reset by WDT."); wdt_rst = 1; } if (wdt_rst) { // if reset by WDT dump info from trace port wdt_reset_info_dump(0); +#if !CONFIG_FREERTOS_UNICORE + wdt_reset_info_dump(1); +#endif } wdt_reset_cpu0_info_enable(); } diff --git a/components/esp_rom/include/esp32p4/rom/rtc.h b/components/esp_rom/include/esp32p4/rom/rtc.h index f9c9f84942..626ae66ba9 100644 --- a/components/esp_rom/include/esp32p4/rom/rtc.h +++ b/components/esp_rom/include/esp32p4/rom/rtc.h @@ -71,46 +71,46 @@ typedef enum { } SLEEP_MODE; typedef enum { - NO_MEAN = 0, - POWERON_RESET = 1, /**<1, Vbat power on reset*/ - RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/ - DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/ - SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/ - TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/ - TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/ - RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/ - TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/ - RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/ - RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ - RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ - RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ - TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ - SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ - EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/ - USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/ - USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/ - JTAG_RESET = 24, /**<24, jtag reset CPU*/ + NO_MEAN = 0, + POWERON_RESET = 1, /**<1, Vbat power on reset*/ + SW_SYS_RESET = 3, /**<3, Software reset digital core*/ + PMU_SYS_PWR_DOWN_RESET = 5, /**<5, PMU HP system power down reset*/ + PMU_CPU_PWR_DOWN_RESET = 6, /**<6, PMU HP CPU power down reset*/ + HP_SYS_HP_WDT_RESET = 7, /**<7, HP system reset from HP watchdog*/ + HP_SYS_LP_WDT_RESET = 9, /**<9, HP system reset from LP watchdog*/ + HP_CORE_HP_WDT_RESET = 11, /**<11, HP core reset from HP watchdog*/ + HP_CORE_SYS_RESET = 12, /**<12, HP core software reset*/ + HP_CORE_LP_SYS_RESET = 13, /**<13, HP core reset from LP watchdog*/ + BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ + LP_WDT_CHIP_RESET = 16, /**<16, Reset chip when LP watchdog trigger*/ + SUPER_WDT_RESET = 18, /**<18, super watchdog reset*/ + GLITCH_RTC_RESET = 19, /**<19, glitch reset*/ + EFUSE_CRC_ERR_RESET = 20, /**<20, efuse ecc error reset*/ + HP_SDIO_RESET = 21, /**<21, hp sdio chip reset*/ + HP_USB_JTAG_RESET = 22, /**<22, hp usb jtag reset*/ + HP_USB_UART_RESET = 23, /**<23, hp usb uart reset*/ + JTAG_RESET = 24, /**<24, jtag reset*/ } RESET_REASON; // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW"); -ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP"); -ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0"); -ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1"); +ESP_STATIC_ASSERT((soc_reset_reason_t)SW_SYS_RESET == RESET_REASON_CORE_SW, "SW_SYS_RESET != RESET_REASON_CORE_SW"); +ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_SYS_PMU_PWR_DOWN, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_DEEP_SLEEP"); +ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_CPU_PWR_DOWN_RESET == RESET_REASON_CPU_PMU_PWR_DOWN, "PMU_CPU_PWR_DOWN_RESET != RESET_REASON_CORE_SDIO"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT_RESET == RESET_REASON_SYS_HP_WDT, "HP_SYS_HP_WDT_RESET != RESET_REASON_CORE_MWDT0"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_LP_WDT_RESET == RESET_REASON_SYS_LP_WDT, "HP_SYS_LP_WDT_RESET != RESET_REASON_SYS_LP_WDT"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_HP_WDT_RESET == RESET_REASON_CORE_HP_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_HP_WDT"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_SYS_RESET == RESET_REASON_CPU0_SW, "HP_CORE_SYS_RESET != RESET_REASON_CPU0_SW"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_LP_SYS_RESET == RESET_REASON_CORE_LP_WDT, "HP_CORE_LP_SYS_RESET != RESET_REASON_CORE_LP_WDT"); +ESP_STATIC_ASSERT((soc_reset_reason_t)BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT"); +ESP_STATIC_ASSERT((soc_reset_reason_t)LP_WDT_CHIP_RESET == RESET_REASON_CHIP_LP_WDT, "LP_WDT_CHIP_RESET != RESET_REASON_CHIP_LP_WDT"); +ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH"); +ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_CRC_ERR_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC"); ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT"); -ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC"); -// ESP32P4-TODO -//_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART"); -//_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG"); -//_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_USB_JTAG_RESET == RESET_REASON_CORE_USB_JTAG, "HP_USB_JTAG_RESET != RESET_REASON_CORE_USB_JTAG"); +ESP_STATIC_ASSERT((soc_reset_reason_t)HP_USB_UART_RESET == RESET_REASON_CORE_USB_UART, "HP_USB_UART_RESET != RESET_REASON_CORE_USB_UART"); +ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG"); + typedef enum { NO_SLEEP = 0, diff --git a/components/esp_system/.build-test-rules.yml b/components/esp_system/.build-test-rules.yml index 9c2dbf4754..1eebf6ca17 100644 --- a/components/esp_system/.build-test-rules.yml +++ b/components/esp_system/.build-test-rules.yml @@ -3,9 +3,6 @@ components/esp_system/test_apps/esp_system_unity_tests: disable: - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - - if: IDF_TARGET == "esp32p4" - temporary: true - reason: not supported on p4 yet # TODO: IDF-8072 components/esp_system/test_apps/linux_apis: enable: diff --git a/components/esp_system/include/esp_system.h b/components/esp_system/include/esp_system.h index 325770f9b9..1354734875 100644 --- a/components/esp_system/include/esp_system.h +++ b/components/esp_system/include/esp_system.h @@ -34,6 +34,7 @@ typedef enum { ESP_RST_BROWNOUT, //!< Brownout reset (software or hardware) ESP_RST_SDIO, //!< Reset over SDIO ESP_RST_USB, //!< Reset by USB peripheral + ESP_RST_JTAG, //!< Reset by JTAG } esp_reset_reason_t; /** diff --git a/components/esp_system/port/soc/esp32p4/reset_reason.c b/components/esp_system/port/soc/esp32p4/reset_reason.c index 4f29b512f3..0615ce2b52 100644 --- a/components/esp_system/port/soc/esp32p4/reset_reason.c +++ b/components/esp_system/port/soc/esp32p4/reset_reason.c @@ -30,26 +30,30 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, } return ESP_RST_SW; - case RESET_REASON_CORE_DEEP_SLEEP: + case RESET_REASON_SYS_PMU_PWR_DOWN: + case RESET_REASON_CPU_PMU_PWR_DOWN: + /* Check when doing sleep bringup TODO IDF-7529 */ return ESP_RST_DEEPSLEEP; - case RESET_REASON_CORE_MWDT0: - return ESP_RST_TASK_WDT; - - case RESET_REASON_CORE_MWDT1: - return ESP_RST_INT_WDT; - - case RESET_REASON_CORE_RTC_WDT: - case RESET_REASON_SYS_RTC_WDT: + case RESET_REASON_SYS_HP_WDT: + case RESET_REASON_SYS_LP_WDT: case RESET_REASON_SYS_SUPER_WDT: - case RESET_REASON_CPU0_RTC_WDT: - case RESET_REASON_CPU0_MWDT0: - case RESET_REASON_CPU0_MWDT1: + case RESET_REASON_CHIP_LP_WDT: + case RESET_REASON_CORE_HP_WDT: + case RESET_REASON_CORE_LP_WDT: + /* Code is the same for INT vs Task WDT */ return ESP_RST_WDT; case RESET_REASON_SYS_BROWN_OUT: return ESP_RST_BROWNOUT; + case RESET_REASON_CORE_USB_UART: + case RESET_REASON_CORE_USB_JTAG: + return ESP_RST_USB; + + case RESET_REASON_CPU_JTAG: + return ESP_RST_JTAG; + default: return ESP_RST_UNKNOWN; } diff --git a/components/esp_system/test_apps/esp_system_unity_tests/README.md b/components/esp_system/test_apps/esp_system_unity_tests/README.md index a8b7833fa3..bf47d80ec6 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/README.md +++ b/components/esp_system/test_apps/esp_system_unity_tests/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt index b2d828a516..46b79fa772 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt @@ -8,8 +8,6 @@ set(requires "unity" set(SRC "test_app_main.c" "test_backtrace.c" "test_delay.c" - "test_ipc_isr.c" - "test_ipc_isr.S" "test_ipc.c" "test_reset_reason.c" "test_sleep.c" @@ -17,6 +15,10 @@ set(SRC "test_app_main.c" "test_system_time.c" "test_task_wdt.c") +if(CONFIG_ESP_IPC_ISR_ENABLE) + list(APPEND SRC "test_ipc_isr.c" "test_ipc_isr.S") +endif() + idf_component_register(SRCS ${SRC} PRIV_INCLUDE_DIRS . PRIV_REQUIRES "${requires}" diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index d5d7ef1f23..860b9f8706 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -36,6 +36,7 @@ #define BROWNOUT "SW_CPU_RESET" #endif // CONFIG_ESP32_REV_MIN_FULL >= 300 #define STORE_ERROR "StoreProhibited" +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define DEEPSLEEP "DSLEEP" @@ -46,6 +47,7 @@ #define RTC_WDT "RTCWDT_RTC_RST" #define BROWNOUT "BROWN_OUT_RST" #define STORE_ERROR "StoreProhibited" +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #define DEEPSLEEP "DSLEEP" @@ -56,6 +58,7 @@ #define RTC_WDT "RTCWDT_RTC_RST" #define BROWNOUT "BROWNOUT_RST" #define STORE_ERROR LOAD_STORE_ERROR +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT #elif CONFIG_IDF_TARGET_ESP32C2 #define DEEPSLEEP "DSLEEP" #define LOAD_STORE_ERROR "Store access fault" @@ -65,6 +68,7 @@ #define RTC_WDT "RTCWDT_RTC_RST" #define BROWNOUT "BROWNOUT_RST" #define STORE_ERROR LOAD_STORE_ERROR +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT #elif CONFIG_IDF_TARGET_ESP32C6 #define DEEPSLEEP "DSLEEP" @@ -75,6 +79,18 @@ #define RTC_WDT "LP_WDT_SYS" #define BROWNOUT "LP_BOD_SYS" #define STORE_ERROR LOAD_STORE_ERROR +#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT + +#elif CONFIG_IDF_TARGET_ESP32P4 +#define DEEPSLEEP "DSLEEP" +#define LOAD_STORE_ERROR "Store access fault" +#define RESET "SW_CPU_RESET" +#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" +#define INT_WDT "HP_SYS_HP_WDT_RESET" +#define RTC_WDT "LP_WDT_SYS" +#define BROWNOUT "LP_BOD_SYS" +#define STORE_ERROR LOAD_STORE_ERROR +#define INT_WDT_HW_ESP_RST ESP_RST_WDT // On P4 there is only one reset reason for MWDT0/1 #endif // CONFIG_IDF_TARGET_ESP32 @@ -88,7 +104,6 @@ TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]") } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32H2) static __NOINIT_ATTR uint32_t s_noinit_val; #if CHECK_RTC_MEM @@ -118,6 +133,8 @@ static void setup_values(void) #endif //CHECK_RTC_MEM } +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529 + static void do_deep_sleep(void) { setup_values(); @@ -144,6 +161,8 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][rese do_deep_sleep, check_reset_reason_deep_sleep); +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...) + static void do_exception(void) { setup_values(); @@ -232,6 +251,7 @@ static void do_int_wdt(void) while(1); } + static void do_int_wdt_hw(void) { setup_values(); @@ -240,10 +260,10 @@ static void do_int_wdt_hw(void) #else XTOS_SET_INTLEVEL(XCHAL_NMILEVEL); #endif - while(1); + while(1) { } } -static void check_reset_reason_int_wdt(void) +static void check_reset_reason_int_wdt_sw(void) { TEST_ASSERT_EQUAL(ESP_RST_INT_WDT, esp_reset_reason()); #if CHECK_RTC_MEM @@ -251,15 +271,23 @@ static void check_reset_reason_int_wdt(void) #endif //CHECK_RTC_MEM } +static void check_reset_reason_int_wdt_hw(void) +{ + TEST_ASSERT_EQUAL(INT_WDT_HW_ESP_RST, esp_reset_reason()); +#if CHECK_RTC_MEM + TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); +#endif //CHECK_RTC_MEM +} + TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)", "[reset_reason][reset="INT_WDT_PANIC","RESET"]", do_int_wdt, - check_reset_reason_int_wdt); + check_reset_reason_int_wdt_sw); TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (hw)", "[reset_reason][reset="INT_WDT"]", do_int_wdt_hw, - check_reset_reason_int_wdt); + check_reset_reason_int_wdt_hw); #if CONFIG_ESP_TASK_WDT_EN static void do_task_wdt(void) @@ -350,11 +378,10 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event", do_brownout, check_reset_reason_brownout); -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...) - #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY #ifndef CONFIG_FREERTOS_UNICORE +#if CONFIG_IDF_TARGET_ARCH_XTENSA #include "xt_instr_macros.h" #include "xtensa/config/specreg.h" @@ -434,6 +461,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a ta init_task_do_exception, test2_finish); +#endif //CONFIG_IDF_TARGET_ARCH_XTENSA #endif // CONFIG_FREERTOS_UNICORE #endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c index 23c4e71ef6..5ad3f47dd5 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c @@ -30,6 +30,8 @@ #include "nvs_flash.h" #include "nvs.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529 + #if SOC_PMU_SUPPORTED #include "esp_private/esp_pmu.h" #else @@ -665,3 +667,5 @@ TEST_CASE("wake up using GPIO (2 or 4 low)", "[deepsleep][ignore]") esp_deep_sleep_start(); } #endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP + +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h index b7e3b101a2..ae17f2eae3 100644 --- a/components/soc/esp32p4/include/soc/reset_reasons.h +++ b/components/soc/esp32p4/include/soc/reset_reasons.h @@ -22,31 +22,29 @@ extern "C" { #endif - -// TODO: IDF-7791 /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter */ typedef enum { - RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset - RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip - RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip - RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST - RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core - RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core - RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core - RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core - RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 - RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST - RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 - RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core - RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module - RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 - RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module - RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module - RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core - RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529 + RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset + RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset + RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system + RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system + RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 + RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core + RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core + RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core } soc_reset_reason_t;