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Merge branch 'refactor/resolve_mmu_soc_dependency_to_sdkconfig_h' into 'master'

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g0: resolve MMU_PAGE_SIZE not defined in g0 build issue

Closes IDF-5219

See merge request espressif/esp-idf!22447
This commit is contained in:
Armando (Dou Yiwen) 2023-02-23 12:05:13 +08:00
commit aeaf119338
14 changed files with 105 additions and 87 deletions
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40
components/esp_hw_support/Kconfig
View File

@ -181,46 +181,6 @@ menu "Hardware Settings"
Note that, this option only controls the ETM related driver log, won't affect other drivers.
endmenu # ETM Configuration
menu "MMU Config"
# This Config is used for configure the MMU.
# Be configured based on flash size selection.
# Invisible to users.
config MMU_PAGE_SIZE_16KB
bool
default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB
default n
config MMU_PAGE_SIZE_32KB
bool
default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB
default n
config MMU_PAGE_SIZE_64KB
bool
default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB
default n
config MMU_PAGE_MODE
string
default "8KB" if MMU_PAGE_SIZE_8KB
default "16KB" if MMU_PAGE_SIZE_16KB
default "32KB" if MMU_PAGE_SIZE_32KB
default "64KB" if MMU_PAGE_SIZE_64KB
config MMU_PAGE_SIZE
# Some chips support different flash MMU page sizes: 64k, 32k, 16k.
# Since the number of MMU pages is limited, the maximum flash size supported
# for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best
# use of small flash sizes (reducing the wasted space due to alignment), we
# need to use the smallest possible MMU page size for the given flash size.
hex
default 0x2000 if MMU_PAGE_SIZE_8KB
default 0x4000 if MMU_PAGE_SIZE_16KB
default 0x8000 if MMU_PAGE_SIZE_32KB
default 0x10000 if MMU_PAGE_SIZE_64KB
endmenu
menu "GDMA Configuration"
depends on SOC_GDMA_SUPPORTED
config GDMA_CTRL_FUNC_IN_IRAM

5
components/soc/CMakeLists.txt
View File

@ -115,6 +115,11 @@ idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
LDFRAGMENTS "linker.lf")
# For an embedded system, the MMU page size should always be defined statically
# For IDF, we define it according to the Flash size that user selects
# Replace this value in an adaptive way, if Kconfig isn't available on your platform
target_compile_definitions(${COMPONENT_LIB} INTERFACE SOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE)
if(target STREQUAL "esp32")
# esp_dport_access_reg_read is added as an undefined symbol because otherwise
# the linker can ignore dport_access.c as it would no other files depending on any symbols in it.

45
components/soc/Kconfig Normal file
View File

@ -0,0 +1,45 @@
menu "SoC Settings"
# No visible menu/configs for now
visible if 0
menu "MMU Config"
# This Config is used for configure the MMU.
# Be configured based on flash size selection.
# Invisible to users.
config MMU_PAGE_SIZE_16KB
bool
default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB
default n
config MMU_PAGE_SIZE_32KB
bool
default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB
default n
config MMU_PAGE_SIZE_64KB
bool
default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB
default n
config MMU_PAGE_MODE
string
default "8KB" if MMU_PAGE_SIZE_8KB
default "16KB" if MMU_PAGE_SIZE_16KB
default "32KB" if MMU_PAGE_SIZE_32KB
default "64KB" if MMU_PAGE_SIZE_64KB
config MMU_PAGE_SIZE
# Some chips support different flash MMU page sizes: 64k, 32k, 16k.
# Since the number of MMU pages is limited, the maximum flash size supported
# for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best
# use of small flash sizes (reducing the wasted space due to alignment), we
# need to use the smallest possible MMU page size for the given flash size.
hex
default 0x2000 if MMU_PAGE_SIZE_8KB
default 0x4000 if MMU_PAGE_SIZE_16KB
default 0x8000 if MMU_PAGE_SIZE_32KB
default 0x10000 if MMU_PAGE_SIZE_64KB
endmenu
endmenu

2
components/soc/esp32/include/soc/ext_mem_defs.h
View File

@ -41,7 +41,7 @@ extern "C" {
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 256

24
components/soc/esp32c2/include/soc/ext_mem_defs.h
View File

@ -7,26 +7,32 @@
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define IRAM0_ADDRESS_LOW 0x4037C000
#define IRAM0_ADDRESS_HIGH 0x403C0000
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
/*DRAM0 is connected with Cache DBUS0*/
#define DRAM0_ADDRESS_LOW 0x3FCA0000
#define DRAM0_ADDRESS_HIGH 0x3FCE0000
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
@ -82,7 +88,7 @@ extern "C" {
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 64 * 64KB, means MMU can support 4MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 64
@ -90,7 +96,7 @@ extern "C" {
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * 64 - 1)
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * 64 - 1)
//MMU entry num
#define MMU_ENTRY_NUM 64
@ -109,7 +115,7 @@ extern "C" {
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
#if (CONFIG_MMU_PAGE_SIZE == 0x10000)
#if (SOC_MMU_PAGE_SIZE == 0x10000)
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 64 MMU entries, needs 0x3F to hold it.
@ -118,7 +124,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x8000)
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
/**
* - 32KB MMU page size: the last 0x7FFF, which is the offset
* - 64 MMU entries, needs 0x3F to hold it.
@ -127,7 +133,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x4000)
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
/**
* - 16KB MMU page size: the last 0x3FFF, which is the offset
* - 64 MMU entries, needs 0x3F to hold it.
@ -135,7 +141,7 @@ extern "C" {
* Therefore, 0xF,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFF
#endif //CONFIG_MMU_PAGE_SIZE
#endif //SOC_MMU_PAGE_SIZE
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses

2
components/soc/esp32c3/include/soc/ext_mem_defs.h
View File

@ -77,7 +77,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0xff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 256

28
components/soc/esp32c6/include/soc/ext_mem_defs.h
View File

@ -3,19 +3,25 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#pragma once
#include "esp_bit_defs.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
@ -74,7 +80,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0x1ff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 256
@ -85,7 +91,7 @@ extern "C" {
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define CACHE_MEMORY_IBANK0_ADDR 0x40800000
@ -96,7 +102,7 @@ extern "C" {
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
#if (CONFIG_MMU_PAGE_SIZE == 0x10000)
#if (SOC_MMU_PAGE_SIZE == 0x10000)
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -105,7 +111,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x8000)
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
/**
* - 32KB MMU page size: the last 0x7FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -114,7 +120,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x4000)
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
/**
* - 16KB MMU page size: the last 0x3FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -122,7 +128,7 @@ extern "C" {
* Therefore, 0x1F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF
#endif //CONFIG_MMU_PAGE_SIZE
#endif //SOC_MMU_PAGE_SIZE
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
@ -152,5 +158,3 @@ _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */

2
components/soc/esp32c6/include/soc/soc.h
View File

@ -155,7 +155,7 @@
*/
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_LOW 0x40000000

29
components/soc/esp32h2/include/soc/ext_mem_defs.h
View File

@ -3,18 +3,25 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#pragma once
#include "esp_bit_defs.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
@ -73,7 +80,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0x1ff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 256
@ -84,7 +91,7 @@ extern "C" {
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define CACHE_MEMORY_IBANK0_ADDR 0x40800000
@ -95,7 +102,7 @@ extern "C" {
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
#if (CONFIG_MMU_PAGE_SIZE == 0x10000)
#if (SOC_MMU_PAGE_SIZE == 0x10000)
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -104,7 +111,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x8000)
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
/**
* - 32KB MMU page size: the last 0x7FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -113,7 +120,7 @@ extern "C" {
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF
#elif (CONFIG_MMU_PAGE_SIZE == 0x4000)
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
/**
* - 16KB MMU page size: the last 0x3FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
@ -121,7 +128,7 @@ extern "C" {
* Therefore, 0x1F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF
#endif //CONFIG_MMU_PAGE_SIZE
#endif //SOC_MMU_PAGE_SIZE
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
@ -151,5 +158,3 @@ _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */

2
components/soc/esp32h2/include/soc/soc.h
View File

@ -152,7 +152,7 @@
*/
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_LOW 0x40000000

2
components/soc/esp32h4/include/soc/ext_mem_defs.h
View File

@ -77,7 +77,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0xff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 256

2
components/soc/esp32s2/include/soc/ext_mem_defs.h
View File

@ -106,7 +106,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0x3fff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can support 1GB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 16384

2
components/soc/esp32s3/include/soc/ext_mem_defs.h
View File

@ -77,7 +77,7 @@ extern "C" {
#define MMU_VALID_VAL_MASK 0x3fff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can support 1GB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 16384

7
tools/test_apps/system/g0_components/CMakeLists.txt
View File

@ -26,13 +26,6 @@ idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1)
project(g0_components)
# As a workaround, we need to define the MMU page size here, until MMU hal-driver
# is refactored.
# IDF-5219
if(CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE)
idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_MMU_PAGE_SIZE=0x10000" APPEND)
endif()
if(CONFIG_IDF_TARGET_ESP32C2)
# clk_tree hal-driver needs CONFIG_XTAL_FREQ
idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_XTAL_FREQ=26" APPEND)