Merge branch 'feature/driver_support_esp32c6_gptimer_etc' into 'master'

gptimer: support esp32h2

Closes IDF-6242

See merge request espressif/esp-idf!21925

components/driver/.build-test-rules.yml

@@ -8,6 +8,10 @@ components/driver/test_apps/dac_test_apps/legacy_dac_driver:
   disable:
     - if: SOC_DAC_SUPPORTED != 1
 
+components/driver/test_apps/gptimer:
+  disable:
+    - if: SOC_GPTIMER_SUPPORTED != 1
+
 components/driver/test_apps/i2s_test_apps:
   disable:
     - if: SOC_I2S_SUPPORTED != 1
@@ -52,6 +56,10 @@ components/driver/test_apps/legacy_rtc_temp_driver:
   disable:
     - if: SOC_TEMP_SENSOR_SUPPORTED != 1
 
+components/driver/test_apps/legacy_timer_driver:
+  disable:
+    - if: SOC_GPTIMER_SUPPORTED != 1
+
 components/driver/test_apps/mcpwm:
   disable:
     - if: SOC_MCPWM_SUPPORTED != 1

components/driver/CMakeLists.txt

@@ -4,13 +4,9 @@ set(srcs
     "gpio/gpio.c"
     "gpio/rtc_io.c"
     "gpio/gpio_glitch_filter_ops.c"
-    "gptimer/gptimer.c"
     "spi_bus_lock.c"
     "uart.c")
 
-# deprecated source files
-list(APPEND srcs "deprecated/timer_legacy.c")
-
 set(includes "include" "deprecated")
 if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include")
     list(APPEND includes "${target}/include")
@@ -20,6 +16,10 @@ if(CONFIG_SOC_LEDC_SUPPORTED)
     list(APPEND srcs "ledc.c")
 endif()
 
+if(CONFIG_SOC_GPTIMER_SUPPORTED)
+    list(APPEND srcs "gptimer/gptimer.c" "deprecated/timer_legacy.c")
+endif()
+
 if(CONFIG_SOC_TIMER_SUPPORT_ETM)
     list(APPEND srcs "gptimer/gptimer_etm.c")
 endif()
@@ -142,14 +142,6 @@ if(${target} STREQUAL "esp32")
     list(APPEND srcs "deprecated/adc_i2s_deprecated.c")
 endif()
 
-if(${target} STREQUAL "esp32h2")
-    # TODO: IDF-5310
-    list(REMOVE_ITEM srcs
-        "deprecated/timer_legacy.c"
-        "gptimer/gptimer.c"
-            )
-endif()
-
 if(BOOTLOADER_BUILD)
     # Bootloader shall NOT depend on the drivers
     idf_component_register()

components/driver/deprecated/timer_legacy.c

@@ -98,6 +98,11 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
         *time = (double)timer_val * div / (40 * 1000 * 1000);
         break;
 #endif
+#if SOC_TIMER_GROUP_SUPPORT_PLL_F48M
+    case TIMER_SRC_CLK_PLL_F48M:
+        *time = (double)timer_val * div / (48 * 1000 * 1000);
+        break;
+#endif
 #if SOC_TIMER_GROUP_SUPPORT_PLL_F80M
     case TIMER_SRC_CLK_PLL_F80M:
         *time = (double)timer_val * div / (80 * 1000 * 1000);

components/hal/CMakeLists.txt

@@ -32,8 +32,6 @@ endif()
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs
         "rtc_io_hal.c"
-        "timer_hal.c"
-        "timer_hal_iram.c"
         "gpio_hal.c"
         "uart_hal.c"
         "uart_hal_iram.c"
@@ -47,6 +45,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "systimer_hal.c")
     endif()
 
+    if(CONFIG_SOC_GPTIMER_SUPPORTED)
+        list(APPEND srcs "timer_hal.c" "timer_hal_iram.c")
+    endif()
+
     if(CONFIG_SOC_LEDC_SUPPORTED)
         list(APPEND srcs "ledc_hal.c" "ledc_hal_iram.c")
     endif()
@@ -207,8 +209,6 @@ if(NOT BOOTLOADER_BUILD)
                 "adc_oneshot_hal.c" # TODO: IDF-6214
                 "adc_hal_common.c" # TODO: IDF-6215
                 "esp32h2/rtc_cntl_hal.c"
-                "timer_hal.c"
-                "timer_hal_iram.c"
                 )
     endif()
 endif()

components/hal/esp32h2/include/hal/timer_ll.h

@@ -0,0 +1,334 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "hal/timer_types.h"
+#include "soc/timer_group_struct.h"
+#include "soc/pcr_struct.h"
+#include "soc/soc_etm_source.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get timer group register base address with giving group number
+#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
+
+#define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                        \
+    (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                             \
+                            [GPTIMER_ETM_TASK_START_COUNT] = TIMER0_TASK_CNT_START_TIMER0, \
+                            [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER0_TASK_CNT_STOP_TIMER0,   \
+                            [GPTIMER_ETM_TASK_EN_ALARM] = TIMER0_TASK_ALARM_START_TIMER0,  \
+                            [GPTIMER_ETM_TASK_RELOAD] = TIMER0_TASK_CNT_RELOAD_TIMER0,     \
+                            [GPTIMER_ETM_TASK_CAPTURE] = TIMER0_TASK_CNT_CAP_TIMER0,       \
+                        }},                                                                \
+                        {{                                                                 \
+                            [GPTIMER_ETM_TASK_START_COUNT] = TIMER1_TASK_CNT_START_TIMER0, \
+                            [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER1_TASK_CNT_STOP_TIMER0,   \
+                            [GPTIMER_ETM_TASK_EN_ALARM] = TIMER1_TASK_ALARM_START_TIMER0,  \
+                            [GPTIMER_ETM_TASK_RELOAD] = TIMER1_TASK_CNT_RELOAD_TIMER0,     \
+                            [GPTIMER_ETM_TASK_CAPTURE] = TIMER1_TASK_CNT_CAP_TIMER0,       \
+                        }},                                                                \
+    }[group][timer][task]
+
+#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event)                                      \
+    (uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{                                            \
+                            [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER0_EVT_CNT_CMP_TIMER0,   \
+                        }},                                                                \
+                        {{                                                                 \
+                            [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER1_EVT_CNT_CMP_TIMER0,   \
+                        }},                                                                \
+    }[group][timer][event]
+
+/**
+ * @brief Set clock source for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param clk_src Clock source
+ */
+static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
+{
+    (void)timer_num; // only one timer in each group
+    uint8_t clk_id = 0;
+    switch (clk_src) {
+    case GPTIMER_CLK_SRC_XTAL:
+        clk_id = 0;
+        break;
+    case GPTIMER_CLK_SRC_RC_FAST:
+        clk_id = 1;
+        break;
+    case GPTIMER_CLK_SRC_PLL_F48M:
+        clk_id = 2;
+        break;
+    default:
+        HAL_ASSERT(false);
+        break;
+    }
+    if (hw == &TIMERG0) {
+        PCR.timergroup0_timer_clk_conf.tg0_timer_clk_sel = clk_id;
+    } else {
+        PCR.timergroup1_timer_clk_conf.tg1_timer_clk_sel = clk_id;
+    }
+}
+
+/**
+ * @brief Enable Timer Group (GPTimer) module clock
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer index in the group
+ * @param en true to enable, false to disable
+ */
+static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    (void)timer_num; // only one timer in each group
+    if (hw == &TIMERG0) {
+        PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = en;
+    } else {
+        PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = en;
+    }
+}
+
+/**
+ * @brief Enable alarm event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable alarm
+ *           False: disable alarm
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_alarm_en = en;
+}
+
+/**
+ * @brief Set clock prescale for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param divider Prescale value (0 and 1 are not valid)
+ */
+static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
+{
+    HAL_ASSERT(divider >= 2 && divider <= 65536);
+    if (divider >= 65536) {
+        divider = 0;
+    }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
+    hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
+}
+
+/**
+ * @brief Enable auto-reload mode
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable auto reload mode
+ *           False: disable auto reload mode
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_autoreload = en;
+}
+
+/**
+ * @brief Set count direction
+ *
+ * @param hw Timer peripheral register base address
+ * @param timer_num Timer number in the group
+ * @param direction Count direction
+ */
+static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
+{
+    hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
+}
+
+/**
+ * @brief Enable timer, start couting
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable the counter
+ *           False: disable the counter
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_en = en;
+}
+
+/**
+ * @brief Trigger software capture event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+__attribute__((always_inline))
+static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].update.tx_update = 1;
+    // Timer register is in a different clock domain from Timer hardware logic
+    // We need to wait for the update to take effect before fetching the count value
+    while (hw->hw_timer[timer_num].update.tx_update) {
+    }
+}
+
+/**
+ * @brief Get counter value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ *
+ * @return counter value
+ */
+__attribute__((always_inline))
+static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
+}
+
+/**
+ * @brief Set alarm value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param alarm_value When counter reaches alarm value, alarm event will be triggered
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
+{
+    hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
+    hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
+}
+
+/**
+ * @brief Set reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param reload_val Reload counter value
+ */
+__attribute__((always_inline))
+static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
+{
+    hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
+    hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
+}
+
+/**
+ * @brief Get reload value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @return reload count value
+ */
+static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
+}
+
+/**
+ * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ */
+static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].load.tx_load = 1;
+}
+
+/**
+ * @brief Enable ETM module
+ *
+ * @param hw Timer Group register base address
+ * @param en True: enable ETM module, False: disable ETM module
+ */
+static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en)
+{
+    hw->regclk.etm_en = en;
+}
+
+/**
+ * @brief Enable timer interrupt by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Mask of interrupt events
+ * @param en True: enable interrupt
+ *           False: disable interrupt
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
+{
+    if (en) {
+        hw->int_ena_timers.val |= mask;
+    } else {
+        hw->int_ena_timers.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Get interrupt status
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status
+ */
+__attribute__((always_inline))
+static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
+{
+    return hw->int_st_timers.val & 0x01;
+}
+
+/**
+ * @brief Clear interrupt status by mask
+ *
+ * @param hw Timer Group register base address
+ * @param mask Interrupt events mask
+ */
+__attribute__((always_inline))
+static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
+{
+    hw->int_clr_timers.val = mask;
+}
+
+/**
+ * @brief Enable the register clock forever
+ *
+ * @param hw Timer Group register base address
+ * @param en True: Enable the register clock forever
+ *           False: Register clock is enabled only when register operation happens
+ */
+static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
+{
+    hw->regclk.clk_en = en;
+}
+
+/**
+ * @brief Get interrupt status register address
+ *
+ * @param hw Timer Group register base address
+ *
+ * @return Interrupt status register address
+ */
+static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
+{
+    return &hw->int_st_timers;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -31,6 +31,10 @@ config SOC_MCPWM_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_SDMMC_HOST_SUPPORTED
     bool
     default y

components/soc/esp32/include/soc/soc_caps.h

@@ -67,6 +67,7 @@
 #define SOC_ADC_SUPPORTED           1
 #define SOC_DAC_SUPPORTED           1
 #define SOC_MCPWM_SUPPORTED         1
+#define SOC_GPTIMER_SUPPORTED       1
 #define SOC_SDMMC_HOST_SUPPORTED    1
 #define SOC_BT_SUPPORTED            1
 #define SOC_PCNT_SUPPORTED          1

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -15,6 +15,10 @@ config SOC_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_BT_SUPPORTED
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -28,6 +28,7 @@
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_GDMA_SUPPORTED              1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_BT_SUPPORTED                1
 #define SOC_WIFI_SUPPORTED              1
 #define SOC_ASYNC_MEMCPY_SUPPORTED      1

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -15,6 +15,10 @@ config SOC_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_TWAI_SUPPORTED
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -28,6 +28,7 @@
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_GDMA_SUPPORTED              1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_BT_SUPPORTED                1
 #define SOC_ASYNC_MEMCPY_SUPPORTED      1

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -15,6 +15,10 @@ config SOC_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_PCNT_SUPPORTED
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -28,6 +28,7 @@
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_GDMA_SUPPORTED              1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_PCNT_SUPPORTED              1
 #define SOC_MCPWM_SUPPORTED             1
 #define SOC_TWAI_SUPPORTED              1

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -11,6 +11,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_IEEE802154_BLE_ONLY
     bool
     default y
@@ -651,7 +655,7 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
-config SOC_TIMER_GROUP_SUPPORT_APB
+config SOC_TIMER_GROUP_SUPPORT_PLL_F48M
     bool
     default y
 
@@ -659,6 +663,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 2
 
+config SOC_TIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_TWAI_CONTROLLER_NUM
     bool
     default y

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -177,7 +177,11 @@ typedef enum {
 typedef enum {
     TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M,     /*!< Timer group clock source is PLL_F48M */
     TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
+#if CONFIG_IDF_ENV_FPGA
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL,          /*!< Timer group clock source default choice is XTAL */
+#else
     TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M,      /*!< Timer group clock source default choice is PLL_F48M */
+#endif
 } soc_periph_tg_clk_src_legacy_t;
 
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////

components/soc/esp32h2/include/soc/soc_caps.h

@@ -34,6 +34,7 @@
 // #define SOC_TWAI_SUPPORTED              1 // TODO: IDF-6217
 // #define SOC_BT_SUPPORTED                1 // TODO: IDF-6416
 // #define SOC_IEEE802154_SUPPORTED        1 // TODO: IDF-6577
+#define SOC_GPTIMER_SUPPORTED              1
 #define SOC_IEEE802154_BLE_ONLY            1
 // #define SOC_USB_SERIAL_JTAG_SUPPORTED   1 // TODO: IDF-6239
 // #define SOC_TEMP_SENSOR_SUPPORTED       1 // TODO: IDF-6229
@@ -342,15 +343,15 @@
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
 
-// TODO: IDF-6242 (Copy from esp32c6, need check)
 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
 #define SOC_TIMER_GROUPS                  (2)
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
+#define SOC_TIMER_GROUP_SUPPORT_PLL_F48M  (1)
+// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1) // TODO: IDF-6265
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-// #define SOC_TIMER_SUPPORT_ETM             (1)
+#define SOC_TIMER_SUPPORT_ETM             (1)
 
 // TODO: IDF-6217 (Copy from esp32c6, need check)
 /*-------------------------- TWAI CAPS ---------------------------------------*/

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -15,6 +15,10 @@ config SOC_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_TWAI_SUPPORTED
     bool
     default y

components/soc/esp32h4/include/soc/soc_caps.h

@@ -36,6 +36,7 @@
 #define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_GDMA_SUPPORTED              1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_BT_SUPPORTED                1
 #define SOC_IEEE802154_SUPPORTED        1

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -23,6 +23,10 @@ config SOC_DEDICATED_GPIO_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_SUPPORTS_SECURE_DL_MODE
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -44,6 +44,7 @@
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_CP_DMA_SUPPORTED            1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_SUPPORTS_SECURE_DL_MODE     1
 #define SOC_RISCV_COPROC_SUPPORTED      1
 #define SOC_USB_OTG_SUPPORTED           1

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -43,6 +43,10 @@ config SOC_GDMA_SUPPORTED
     bool
     default y
 
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
 config SOC_LCDCAM_SUPPORTED
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -30,6 +30,7 @@
 #define SOC_WIFI_SUPPORTED              1
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
+#define SOC_GPTIMER_SUPPORTED           1
 #define SOC_LCDCAM_SUPPORTED            1
 #define SOC_MCPWM_SUPPORTED             1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1

examples/peripherals/.build-test-rules.yml

@@ -171,6 +171,10 @@ examples/peripherals/temp_sensor:
   disable:
     - if: SOC_TEMP_SENSOR_SUPPORTED != 1
 
+examples/peripherals/timer_group:
+  disable:
+    - if: SOC_GPTIMER_SUPPORTED != 1
+
 examples/peripherals/timer_group/gptimer_capture_hc_sr04:
   disable:
     - if: SOC_TIMER_SUPPORT_ETM != 1

examples/peripherals/timer_group/legacy_driver/README.md

@@ -3,7 +3,7 @@
 
 # Example: General Purpose Timer
 
-This example uses the timer group driver to generate timer interrupts at two specified alarm intervals.
+This example uses the **legacy timer group driver** to generate timer interrupts with and without auto-reload. But we highly recommend you to use the new [GPTimer Driver](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/gptimer.html) in your new projects.
 
 ## How to Use Example
 
@@ -19,9 +19,10 @@ Run `idf.py -p PORT flash monitor` to build, flash and monitor the project.
 (To exit the serial monitor, type ``Ctrl-]``.)
 
 See the [ESP-IDF Getting Started Guide](https://idf.espressif.com/) for all the steps to configure and use the ESP-IDF to build projects.
+
 ## Example Output
 
-```
+```text
 I (0) cpu_start: Starting scheduler on APP CPU.
 I (325) example: Init timer with auto-reload
 I (835) example: Timer auto reloaded, count value in ISR: 3