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fix(gdma): burst size should be configurable on esp32c5

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This commit is contained in:
morris 2024-12-02 13:42:17 +08:00
parent daf465c038
commit b5c5c046d6
9 changed files with 17 additions and 123 deletions
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2
components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c
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@ -288,7 +288,7 @@ static void memcpy_performance_test(uint32_t buffer_size)
async_memcpy_config_t config = ASYNC_MEMCPY_DEFAULT_CONFIG();
config.backlog = (buffer_size / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1) * TEST_ASYNC_MEMCPY_BENCH_COUNTS;
config.dma_burst_size = 64; // set a big burst size for performance
config.dma_burst_size = 32; // set a big burst size for performance
async_memcpy_handle_t driver = NULL;
int64_t elapse_us = 0;
float throughput = 0.0;

6
components/hal/esp32c5/include/hal/ahb_dma_ll.h
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@ -220,9 +220,6 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
@ -473,9 +470,6 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;

6
components/hal/esp32c61/include/hal/ahb_dma_ll.h
View File

@ -212,9 +212,6 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
@ -465,9 +462,6 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;

1
components/hal/gdma_hal_ahb_v2.c
View File

@ -8,6 +8,7 @@
#include "hal/assert.h"
#include "hal/gdma_hal_ahb.h"
#include "hal/ahb_dma_ll.h"
#include "hal/gdma_ll.h"
static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
.m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,

1
components/hal/gdma_hal_axi.c
View File

@ -8,6 +8,7 @@
#include "hal/assert.h"
#include "hal/gdma_hal_axi.h"
#include "hal/axi_dma_ll.h"
#include "hal/gdma_ll.h"
static gdma_hal_priv_data_t gdma_axi_hal_priv_data = {
.m2m_free_periph_mask = AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK,

12
components/soc/esp32c5/register/soc/ahb_dma_reg.h
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@ -1326,7 +1326,7 @@ extern "C" {
#define AHB_DMA_IN_ETM_EN_CH0_S 5
/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S)
@ -1645,7 +1645,7 @@ extern "C" {
#define AHB_DMA_OUT_ETM_EN_CH0_S 6
/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S)
@ -1938,7 +1938,7 @@ extern "C" {
#define AHB_DMA_IN_ETM_EN_CH1_S 5
/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S)
@ -2257,7 +2257,7 @@ extern "C" {
#define AHB_DMA_OUT_ETM_EN_CH1_S 6
/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S)
@ -2550,7 +2550,7 @@ extern "C" {
#define AHB_DMA_IN_ETM_EN_CH2_S 5
/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channel2.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 0x00000003U
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S)
@ -2869,7 +2869,7 @@ extern "C" {
#define AHB_DMA_OUT_ETM_EN_CH2_S 6
/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel2.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 0x00000003U
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S)

52
components/soc/esp32c5/register/soc/ahb_dma_struct.h
View File

@ -378,7 +378,7 @@ typedef union {
uint32_t in_etm_en_chn:1;
/** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
uint32_t in_data_burst_mode_sel_chn:2;
uint32_t reserved_8:24;
@ -455,54 +455,6 @@ typedef union {
uint32_t val;
} ahb_dma_in_link_chn_reg_t;
/** Type of out_conf0_ch0 register
* Configuration register 0 of TX channel 0
*/
typedef union {
struct {
/** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
* Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0:
* Release reset\\1: Reset\\
*/
uint32_t out_rst_ch0:1;
/** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
* Reserved.
*/
uint32_t out_loop_test_ch0:1;
/** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable automatic outlink write-back when all the data
* in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\
*/
uint32_t out_auto_wrback_ch0:1;
/** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
* Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated
* when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for
* TX channel 0 is generated when data to be transmitted has been popped from FIFO in
* AHB_DMA.\\
*/
uint32_t out_eof_mode_ch0:1;
/** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable INCR burst transfer for TX channel 0 reading
* descriptors.\\0: Disable\\1: Enable\\
*/
uint32_t outdscr_burst_en_ch0:1;
uint32_t reserved_5:1;
/** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
* Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1:
* Enable\\
*/
uint32_t out_etm_en_ch0:1;
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
*/
uint32_t out_data_burst_mode_sel_ch0:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_ch0_reg_t;
/** Type of out_conf1_chn register
* Configuration register 1 of TX channel 0
*/
@ -607,7 +559,7 @@ typedef union {
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
uint32_t out_data_burst_mode_sel_chn:2;
uint32_t reserved_10:22;

8
components/soc/esp32c61/register/soc/ahb_dma_reg.h
View File

@ -922,7 +922,7 @@ extern "C" {
#define AHB_DMA_IN_ETM_EN_CH0_S 5
/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S)
@ -1253,7 +1253,7 @@ extern "C" {
#define AHB_DMA_OUT_ETM_EN_CH0_S 6
/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S)
@ -1558,7 +1558,7 @@ extern "C" {
#define AHB_DMA_IN_ETM_EN_CH1_S 5
/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U
#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S)
@ -1889,7 +1889,7 @@ extern "C" {
#define AHB_DMA_OUT_ETM_EN_CH1_S 6
/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel1.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U
#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S)

52
components/soc/esp32c61/register/soc/ahb_dma_struct.h
View File

@ -378,7 +378,7 @@ typedef union {
uint32_t in_etm_en_chn:1;
/** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
uint32_t in_data_burst_mode_sel_chn:2;
uint32_t reserved_8:24;
@ -455,54 +455,6 @@ typedef union {
uint32_t val;
} ahb_dma_in_link_chn_reg_t;
/** Type of out_conf0_ch0 register
* Configuration register 0 of TX channel 0
*/
typedef union {
struct {
/** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
* Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.\\0:
* Release reset\\1: Reset\\
*/
uint32_t out_rst_ch0:1;
/** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
* Reserved.
*/
uint32_t out_loop_test_ch0:1;
/** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable automatic outlink write-back when all the data
* in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\
*/
uint32_t out_auto_wrback_ch0:1;
/** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
* Configures when to generate EOF flag.\\0: EOF flag for TX channel 0 is generated
* when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for
* TX channel 0 is generated when data to be transmitted has been popped from FIFO in
* AHB_DMA.\\
*/
uint32_t out_eof_mode_ch0:1;
/** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable INCR burst transfer for TX channel 0 reading
* descriptors.\\0: Disable\\1: Enable\\
*/
uint32_t outdscr_burst_en_ch0:1;
uint32_t reserved_5:1;
/** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
* Configures whether or not to enable ETM control for TX channel 0.\\0: Disable\\1:
* Enable\\
*/
uint32_t out_etm_en_ch0:1;
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channel0.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
*/
uint32_t out_data_burst_mode_sel_ch0:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_ch0_reg_t;
/** Type of out_conf1_chn register
* Configuration register 1 of TX channel 0
*/
@ -607,7 +559,7 @@ typedef union {
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: incr16\\
* incr8\\ 2'b11: reserved\\
*/
uint32_t out_data_burst_mode_sel_chn:2;
uint32_t reserved_10:22;