diff --git a/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c index 1592c44341..9fc85e809b 100644 --- a/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c @@ -83,7 +83,7 @@ static void s_sar_adc_power_acquire(void) portENTER_CRITICAL_SAFE(&rtc_spinlock); s_saradc_power_on_cnt++; if (s_saradc_power_on_cnt == 1) { - adc_ll_digi_set_power_manage(ADC_POWER_SW_ON); + adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); } @@ -97,7 +97,7 @@ static void s_sar_adc_power_release(void) ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__); abort(); } else if (s_saradc_power_on_cnt == 0) { - adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM); + adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); } diff --git a/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c index f0624593f4..5c9c47cd11 100644 --- a/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c @@ -83,7 +83,7 @@ static void s_sar_adc_power_acquire(void) portENTER_CRITICAL_SAFE(&rtc_spinlock); s_saradc_power_on_cnt++; if (s_saradc_power_on_cnt == 1) { - adc_ll_digi_set_power_manage(ADC_POWER_SW_ON); + adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); } @@ -97,7 +97,7 @@ static void s_sar_adc_power_release(void) ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__); abort(); } else if (s_saradc_power_on_cnt == 0) { - adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM); + adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); } diff --git a/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c index 33ae356d0d..e23af13e43 100644 --- a/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c @@ -88,10 +88,10 @@ void sar_periph_ctrl_adc_oneshot_power_release(void) void sar_periph_ctrl_adc_continuous_power_acquire(void) { - adc_ll_digi_set_power_manage(ADC_POWER_SW_ON); + adc_ll_digi_set_power_manage(ADC_LL_POWER_SW_ON); } void sar_periph_ctrl_adc_continuous_power_release(void) { - adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM); + adc_ll_digi_set_power_manage(ADC_LL_POWER_BY_FSM); } diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h index 2e363c08ba..02ce51b213 100644 --- a/components/hal/esp32/include/hal/adc_ll.h +++ b/components/hal/esp32/include/hal/adc_ll.h @@ -29,10 +29,6 @@ extern "C" { #define ADC_LL_DEFAULT_CONV_LIMIT_EN 1 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 -typedef enum { - ADC_RTC_DATA_OK = 0, -} adc_ll_rtc_raw_data_t; - typedef enum { ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller. ADC_LL_CTRL_ULP = 1, ///< For ADC1 and ADC2. Select ULP controller. diff --git a/components/hal/esp32c2/include/hal/adc_ll.h b/components/hal/esp32c2/include/hal/adc_ll.h index a1d51689d7..ed2ba5020e 100644 --- a/components/hal/esp32c2/include/hal/adc_ll.h +++ b/components/hal/esp32c2/include/hal/adc_ll.h @@ -34,19 +34,11 @@ extern "C" { #define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; -typedef enum { - ADC_RTC_DATA_OK = 0, - ADC_RTC_CTRL_UNSELECTED = 1, - ADC_RTC_CTRL_BREAK = 2, - ADC_RTC_DATA_FAIL = -1, -} adc_ll_rtc_raw_data_t; - typedef enum { ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller. } adc_ll_controller_t; @@ -318,13 +310,13 @@ static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage) { /* Bit1 0:Fsm 1: SW mode Bit0 0:SW mode power down 1: SW mode power on */ - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; } diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index c102b72abd..691e93e72f 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -41,19 +41,11 @@ extern "C" { #define ADC_LL_EVENT_THRES1_LOW BIT(26) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; -typedef enum { - ADC_RTC_DATA_OK = 0, - ADC_RTC_CTRL_UNSELECTED = 1, - ADC_RTC_CTRL_BREAK = 2, - ADC_RTC_DATA_FAIL = -1, -} adc_ll_rtc_raw_data_t; - typedef enum { ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller. ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter. @@ -488,13 +480,13 @@ static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage) { /* Bit1 0:Fsm 1: SW mode Bit0 0:SW mode power down 1: SW mode power on */ - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.ctrl.sar_clk_gated = 0; APB_SARADC.ctrl.xpd_sar_force = 2; } diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h index 5ed2db486a..adf131672c 100644 --- a/components/hal/esp32c6/include/hal/adc_ll.h +++ b/components/hal/esp32c6/include/hal/adc_ll.h @@ -42,10 +42,9 @@ extern "C" { #define ADC_LL_EVENT_THRES1_LOW BIT(26) typedef enum { - ADC_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; typedef enum { @@ -495,13 +494,13 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) { /* Bit1 0:Fsm 1: SW mode Bit0 0:SW mode power down 1: SW mode power on */ - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; } diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h index a2e41bb94a..17847f4748 100644 --- a/components/hal/esp32h2/include/hal/adc_ll.h +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -42,10 +42,9 @@ extern "C" { #define ADC_LL_EVENT_THRES1_LOW BIT(26) typedef enum { - ADC_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; typedef enum { @@ -495,13 +494,13 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) { /* Bit1 0:Fsm 1: SW mode Bit0 0:SW mode power down 1: SW mode power on */ - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; } diff --git a/components/hal/esp32h4/include/hal/adc_ll.h b/components/hal/esp32h4/include/hal/adc_ll.h index aa23ec8bb2..7612384932 100644 --- a/components/hal/esp32h4/include/hal/adc_ll.h +++ b/components/hal/esp32h4/include/hal/adc_ll.h @@ -37,17 +37,16 @@ extern "C" { #define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; typedef enum { - ADC_RTC_DATA_OK = 0, - ADC_RTC_CTRL_UNSELECTED = 1, - ADC_RTC_CTRL_BREAK = 2, - ADC_RTC_DATA_FAIL = -1, + ADC_LL_RTC_DATA_OK = 0, + ADC_LL_RTC_CTRL_UNSELECTED = 1, + ADC_LL_RTC_CTRL_BREAK = 2, + ADC_LL_RTC_DATA_FAIL = -1, } adc_ll_rtc_raw_data_t; typedef enum { @@ -483,30 +482,6 @@ static inline uint32_t adc_ll_pwdet_get_cct(void) abort(); } -/** - * Analyze whether the obtained raw data is correct. - * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. - * - * @param adc_n ADC unit. - * @param raw_data ADC raw data input (convert value). - * @return - * - 0: The data is correct to use. - * - -1: The data is invalid. - */ -static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, int raw_data) -{ - if (adc_n == ADC_UNIT_1) { - return ADC_RTC_DATA_OK; - } - - //The raw data API returns value without channel information. Read value directly from the register - if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { - return ADC_RTC_DATA_FAIL; - } - - return ADC_RTC_DATA_OK; -} - /*--------------------------------------------------------------- Common setting ---------------------------------------------------------------*/ diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index e09a07f54c..0713d79748 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -37,17 +37,16 @@ extern "C" { #define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; typedef enum { - ADC_RTC_DATA_OK = 0, - ADC_RTC_CTRL_UNSELECTED = 1, - ADC_RTC_CTRL_BREAK = 2, - ADC_RTC_DATA_FAIL = -1, + ADC_LL_RTC_DATA_OK = 0, + ADC_LL_RTC_CTRL_UNSELECTED = 1, + ADC_LL_RTC_CTRL_BREAK = 2, + ADC_LL_RTC_DATA_FAIL = -1, } adc_ll_rtc_raw_data_t; typedef enum { @@ -859,13 +858,13 @@ static inline void adc_oneshot_ll_disable_all_unit(void) */ static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage) { - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 0x3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 0x0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.ctrl.sar_clk_gated = 0; APB_SARADC.ctrl.xpd_sar_force = 0x2; } diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h index 19a5c9aea3..93f5f8373a 100644 --- a/components/hal/esp32s3/include/hal/adc_ll.h +++ b/components/hal/esp32s3/include/hal/adc_ll.h @@ -37,10 +37,9 @@ extern "C" { #define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1) typedef enum { - ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ - ADC_POWER_MAX, /*!< For parameter check. */ + ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ } adc_ll_power_t; typedef enum { @@ -544,13 +543,13 @@ static inline uint32_t adc_ll_pwdet_get_cct(void) */ static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage) { - if (manage == ADC_POWER_SW_ON) { + if (manage == ADC_LL_POWER_SW_ON) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 0x3; - } else if (manage == ADC_POWER_BY_FSM) { + } else if (manage == ADC_LL_POWER_BY_FSM) { APB_SARADC.ctrl.sar_clk_gated = 1; APB_SARADC.ctrl.xpd_sar_force = 0x0; - } else if (manage == ADC_POWER_SW_OFF) { + } else if (manage == ADC_LL_POWER_SW_OFF) { APB_SARADC.ctrl.sar_clk_gated = 0; APB_SARADC.ctrl.xpd_sar_force = 0x2; }