diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/include/soc/reg_base.h index 9beea9fde3..ad1b7d143a 100644 --- a/components/soc/esp32s3/include/soc/reg_base.h +++ b/components/soc/esp32s3/include/soc/reg_base.h @@ -61,4 +61,4 @@ #define DR_REG_INTERRUPT_BASE 0x600C2000 #define DR_REG_EXTMEM_BASE 0x600C4000 #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 -#define DR_REG_WORLD_CNTL_BASE 0x600D0000 +#define DR_REG_WCL_BASE 0x600D0000 diff --git a/components/soc/esp32s3/include/soc/world_controller_reg.h b/components/soc/esp32s3/include/soc/world_controller_reg.h index 610e66089d..1ba5333cf2 100644 --- a/components/soc/esp32s3/include/soc/world_controller_reg.h +++ b/components/soc/esp32s3/include/soc/world_controller_reg.h @@ -1,1084 +1,1504 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_WORLD_CONTROLLER_REG_H_ -#define _SOC_WORLD_CONTROLLER_REG_H_ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x0) -/* WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 1 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4) -/* WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 2 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8) -/* WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 3 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xC) -/* WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 4 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x10) -/* WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 5 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14) -/* WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 6 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18) -/* WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 7 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x1C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 8 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x20) -/* WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 9 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x24) -/* WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 10 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x28) -/* WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 11 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x2C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 12 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x30) -/* WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 13 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x7C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ -/*description: This filed is used to enable entry address check .*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK 0x00001FFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V 0x1FFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x100) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to set address that need to write when enter WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x104) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: This filed is used to set the max value of clear write_buffer.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX 0x0000000F -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V 0xF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x80) -/* WORLD_CONTROLLER_CORE_0_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 1 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_1 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 1.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 1 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x84) -/* WORLD_CONTROLLER_CORE_0_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 2 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_2 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 2.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 2 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x88) -/* WORLD_CONTROLLER_CORE_0_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 3 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_3 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 3.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 3 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8C) -/* WORLD_CONTROLLER_CORE_0_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 4 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_4 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 4.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 4 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x90) -/* WORLD_CONTROLLER_CORE_0_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 5 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_5 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 5.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 5 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x94) -/* WORLD_CONTROLLER_CORE_0_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 6 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_6 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 6.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 6 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x98) -/* WORLD_CONTROLLER_CORE_0_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 7 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_7 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 7.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 7 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x9C) -/* WORLD_CONTROLLER_CORE_0_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 8 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_8 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 8.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 8 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA0) -/* WORLD_CONTROLLER_CORE_0_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 9 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_9 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 9.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 9 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA4) -/* WORLD_CONTROLLER_CORE_0_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 10 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_10 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 10.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 10 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA8) -/* WORLD_CONTROLLER_CORE_0_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 11 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_11 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 11.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 11 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xAC) -/* WORLD_CONTROLLER_CORE_0_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 12 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_12 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 12.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 12 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xB0) -/* WORLD_CONTROLLER_CORE_0_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 13 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_13 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 13.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 13 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xFC) -/* WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ -/*description: This field is used to quickly read and rewrite the current field of all STATUSTA -BLE registers.For example.*/ -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT 0x00001FFF -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S)) -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V 0x1FFF -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x108) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_M (BIT(6)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_S 6 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_S 5 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: This field indicates the data to be written next time.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT 0x0000000F -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V 0xF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S 1 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether the check is successful.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x140) -/* WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x144) -/* WORLD_CONTROLLER_CORE_0_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This field to used to set world to enter.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x148) -/* WORLD_CONTROLLER_CORE_0_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to update configuration completed.*/ -#define WORLD_CONTROLLER_CORE_0_UPDATE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_UPDATE_M ((WORLD_CONTROLLER_CORE_0_UPDATE_V)<<(WORLD_CONTROLLER_CORE_0_UPDATE_S)) -#define WORLD_CONTROLLER_CORE_0_UPDATE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_UPDATE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14C) -/* WORLD_CONTROLLER_CORE_0_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to cancel switch world configuration.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x150) -/* WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Iram0 bus.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x154) -/* WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x158) -/* WORLD_CONTROLLER_CORE_0_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether is preparing to switch to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x180) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to set NMI mask.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x184) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field to used to set trigger address.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x188) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to disable NMI mask.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18C) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to cancel NMI mask disable function..*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x190) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to mask NMI interrupt.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_V 0x1 -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x194) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x400) -/* WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 1 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x404) -/* WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 2 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x408) -/* WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 3 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x40C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 4 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x410) -/* WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 5 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x414) -/* WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 6 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x418) -/* WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 7 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x41C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 8 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x420) -/* WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 9 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x424) -/* WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 10 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x428) -/* WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 11 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x42C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 12 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x430) -/* WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 13 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x47C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ -/*description: This filed is used to enable entry address check .*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK 0x00001FFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V 0x1FFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x500) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to set address that need to write when enter WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x504) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: This filed is used to set the max value of clear write_buffer.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX 0x0000000F -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V 0xF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x480) -/* WORLD_CONTROLLER_CORE_1_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 1 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_1 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 1.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 1 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x484) -/* WORLD_CONTROLLER_CORE_1_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 2 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_2 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 2.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 2 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x488) -/* WORLD_CONTROLLER_CORE_1_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 3 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_3 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 3.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 3 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x48C) -/* WORLD_CONTROLLER_CORE_1_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 4 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_4 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 4.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 4 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x490) -/* WORLD_CONTROLLER_CORE_1_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 5 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_5 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 5.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 5 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x494) -/* WORLD_CONTROLLER_CORE_1_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 6 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_6 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 6.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 6 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x498) -/* WORLD_CONTROLLER_CORE_1_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 7 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_7 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 7.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 7 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x49C) -/* WORLD_CONTROLLER_CORE_1_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 8 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_8 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 8.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 8 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A0) -/* WORLD_CONTROLLER_CORE_1_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 9 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_9 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 9.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 9 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A4) -/* WORLD_CONTROLLER_CORE_1_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 10 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_10 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 10.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 10 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A8) -/* WORLD_CONTROLLER_CORE_1_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 11 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_11 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 11.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 11 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4AC) -/* WORLD_CONTROLLER_CORE_1_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 12 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_12 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 12.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 12 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4B0) -/* WORLD_CONTROLLER_CORE_1_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 13 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_13 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 13.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 13 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4FC) -/* WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ -/*description: This field is used to quickly read and rewrite the current field of all STATUSTA -BLE registers.For example.*/ -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT 0x00001FFF -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S)) -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V 0x1FFF -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x508) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_M (BIT(6)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_S 6 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_S 5 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: This field indicates the data to be written next time.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT 0x0000000F -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V 0xF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S 1 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether the check is successful.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x540) -/* WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x544) -/* WORLD_CONTROLLER_CORE_1_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This field to used to set world to enter.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x548) -/* WORLD_CONTROLLER_CORE_1_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to update configuration completed.*/ -#define WORLD_CONTROLLER_CORE_1_UPDATE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_UPDATE_M ((WORLD_CONTROLLER_CORE_1_UPDATE_V)<<(WORLD_CONTROLLER_CORE_1_UPDATE_S)) -#define WORLD_CONTROLLER_CORE_1_UPDATE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_UPDATE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x54C) -/* WORLD_CONTROLLER_CORE_1_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to cancel switch world configuration.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x550) -/* WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Iram0 bus.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x554) -/* WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x558) -/* WORLD_CONTROLLER_CORE_1_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether is preparing to switch to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x580) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to set NMI mask.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x584) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field to used to set trigger address.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x588) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to disable NMI mask.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x58C) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to cancel NMI mask disable function..*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x590) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to mask NMI interrupt.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_V 0x1 -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x594) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_S 0 - +/** WCL_Core_0_ENTRY_1_ADDR_REG register + * Core_0 Entry 1 address configuration Register + */ +#define WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WCL_BASE + 0x0) +/** WCL_CORE_0_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 1 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_1_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_1_ADDR_M (WCL_CORE_0_ENTRY_1_ADDR_V << WCL_CORE_0_ENTRY_1_ADDR_S) +#define WCL_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_1_ADDR_S 0 + +/** WCL_Core_0_ENTRY_2_ADDR_REG register + * Core_0 Entry 2 address configuration Register + */ +#define WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WCL_BASE + 0x4) +/** WCL_CORE_0_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 2 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_2_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_2_ADDR_M (WCL_CORE_0_ENTRY_2_ADDR_V << WCL_CORE_0_ENTRY_2_ADDR_S) +#define WCL_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_2_ADDR_S 0 + +/** WCL_Core_0_ENTRY_3_ADDR_REG register + * Core_0 Entry 3 address configuration Register + */ +#define WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WCL_BASE + 0x8) +/** WCL_CORE_0_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 3 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_3_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_3_ADDR_M (WCL_CORE_0_ENTRY_3_ADDR_V << WCL_CORE_0_ENTRY_3_ADDR_S) +#define WCL_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_3_ADDR_S 0 + +/** WCL_Core_0_ENTRY_4_ADDR_REG register + * Core_0 Entry 4 address configuration Register + */ +#define WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WCL_BASE + 0xc) +/** WCL_CORE_0_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 4 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_4_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_4_ADDR_M (WCL_CORE_0_ENTRY_4_ADDR_V << WCL_CORE_0_ENTRY_4_ADDR_S) +#define WCL_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_4_ADDR_S 0 + +/** WCL_Core_0_ENTRY_5_ADDR_REG register + * Core_0 Entry 5 address configuration Register + */ +#define WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WCL_BASE + 0x10) +/** WCL_CORE_0_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 5 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_5_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_5_ADDR_M (WCL_CORE_0_ENTRY_5_ADDR_V << WCL_CORE_0_ENTRY_5_ADDR_S) +#define WCL_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_5_ADDR_S 0 + +/** WCL_Core_0_ENTRY_6_ADDR_REG register + * Core_0 Entry 6 address configuration Register + */ +#define WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WCL_BASE + 0x14) +/** WCL_CORE_0_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 6 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_6_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_6_ADDR_M (WCL_CORE_0_ENTRY_6_ADDR_V << WCL_CORE_0_ENTRY_6_ADDR_S) +#define WCL_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_6_ADDR_S 0 + +/** WCL_Core_0_ENTRY_7_ADDR_REG register + * Core_0 Entry 7 address configuration Register + */ +#define WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WCL_BASE + 0x18) +/** WCL_CORE_0_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 7 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_7_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_7_ADDR_M (WCL_CORE_0_ENTRY_7_ADDR_V << WCL_CORE_0_ENTRY_7_ADDR_S) +#define WCL_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_7_ADDR_S 0 + +/** WCL_Core_0_ENTRY_8_ADDR_REG register + * Core_0 Entry 8 address configuration Register + */ +#define WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WCL_BASE + 0x1c) +/** WCL_CORE_0_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 8 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_8_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_8_ADDR_M (WCL_CORE_0_ENTRY_8_ADDR_V << WCL_CORE_0_ENTRY_8_ADDR_S) +#define WCL_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_8_ADDR_S 0 + +/** WCL_Core_0_ENTRY_9_ADDR_REG register + * Core_0 Entry 9 address configuration Register + */ +#define WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WCL_BASE + 0x20) +/** WCL_CORE_0_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 9 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_9_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_9_ADDR_M (WCL_CORE_0_ENTRY_9_ADDR_V << WCL_CORE_0_ENTRY_9_ADDR_S) +#define WCL_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_9_ADDR_S 0 + +/** WCL_Core_0_ENTRY_10_ADDR_REG register + * Core_0 Entry 10 address configuration Register + */ +#define WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WCL_BASE + 0x24) +/** WCL_CORE_0_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 10 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_10_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_10_ADDR_M (WCL_CORE_0_ENTRY_10_ADDR_V << WCL_CORE_0_ENTRY_10_ADDR_S) +#define WCL_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_10_ADDR_S 0 + +/** WCL_Core_0_ENTRY_11_ADDR_REG register + * Core_0 Entry 11 address configuration Register + */ +#define WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WCL_BASE + 0x28) +/** WCL_CORE_0_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 11 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_11_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_11_ADDR_M (WCL_CORE_0_ENTRY_11_ADDR_V << WCL_CORE_0_ENTRY_11_ADDR_S) +#define WCL_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_11_ADDR_S 0 + +/** WCL_Core_0_ENTRY_12_ADDR_REG register + * Core_0 Entry 12 address configuration Register + */ +#define WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WCL_BASE + 0x2c) +/** WCL_CORE_0_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 12 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_12_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_12_ADDR_M (WCL_CORE_0_ENTRY_12_ADDR_V << WCL_CORE_0_ENTRY_12_ADDR_S) +#define WCL_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_12_ADDR_S 0 + +/** WCL_Core_0_ENTRY_13_ADDR_REG register + * Core_0 Entry 13 address configuration Register + */ +#define WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WCL_BASE + 0x30) +/** WCL_CORE_0_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 13 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_13_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_13_ADDR_M (WCL_CORE_0_ENTRY_13_ADDR_V << WCL_CORE_0_ENTRY_13_ADDR_S) +#define WCL_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_13_ADDR_S 0 + +/** WCL_Core_0_ENTRY_CHECK_REG register + * Core_0 Entry check configuration Register + */ +#define WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WCL_BASE + 0x7c) +/** WCL_CORE_0_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ +#define WCL_CORE_0_ENTRY_CHECK 0x00001FFFU +#define WCL_CORE_0_ENTRY_CHECK_M (WCL_CORE_0_ENTRY_CHECK_V << WCL_CORE_0_ENTRY_CHECK_S) +#define WCL_CORE_0_ENTRY_CHECK_V 0x00001FFFU +#define WCL_CORE_0_ENTRY_CHECK_S 1 + +/** WCL_Core_0_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ +#define WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WCL_BASE + 0x80) +/** WCL_CORE_0_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ +#define WCL_CORE_0_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_1_M (WCL_CORE_0_FROM_WORLD_1_V << WCL_CORE_0_FROM_WORLD_1_S) +#define WCL_CORE_0_FROM_WORLD_1_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_1_S 0 +/** WCL_CORE_0_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ +#define WCL_CORE_0_FROM_ENTRY_1 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_1_M (WCL_CORE_0_FROM_ENTRY_1_V << WCL_CORE_0_FROM_ENTRY_1_S) +#define WCL_CORE_0_FROM_ENTRY_1_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_1_S 1 +/** WCL_CORE_0_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ +#define WCL_CORE_0_CURRENT_1 (BIT(5)) +#define WCL_CORE_0_CURRENT_1_M (WCL_CORE_0_CURRENT_1_V << WCL_CORE_0_CURRENT_1_S) +#define WCL_CORE_0_CURRENT_1_V 0x00000001U +#define WCL_CORE_0_CURRENT_1_S 5 + +/** WCL_Core_0_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ +#define WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WCL_BASE + 0x84) +/** WCL_CORE_0_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ +#define WCL_CORE_0_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_2_M (WCL_CORE_0_FROM_WORLD_2_V << WCL_CORE_0_FROM_WORLD_2_S) +#define WCL_CORE_0_FROM_WORLD_2_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_2_S 0 +/** WCL_CORE_0_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ +#define WCL_CORE_0_FROM_ENTRY_2 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_2_M (WCL_CORE_0_FROM_ENTRY_2_V << WCL_CORE_0_FROM_ENTRY_2_S) +#define WCL_CORE_0_FROM_ENTRY_2_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_2_S 1 +/** WCL_CORE_0_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ +#define WCL_CORE_0_CURRENT_2 (BIT(5)) +#define WCL_CORE_0_CURRENT_2_M (WCL_CORE_0_CURRENT_2_V << WCL_CORE_0_CURRENT_2_S) +#define WCL_CORE_0_CURRENT_2_V 0x00000001U +#define WCL_CORE_0_CURRENT_2_S 5 + +/** WCL_Core_0_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ +#define WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WCL_BASE + 0x88) +/** WCL_CORE_0_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ +#define WCL_CORE_0_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_3_M (WCL_CORE_0_FROM_WORLD_3_V << WCL_CORE_0_FROM_WORLD_3_S) +#define WCL_CORE_0_FROM_WORLD_3_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_3_S 0 +/** WCL_CORE_0_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ +#define WCL_CORE_0_FROM_ENTRY_3 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_3_M (WCL_CORE_0_FROM_ENTRY_3_V << WCL_CORE_0_FROM_ENTRY_3_S) +#define WCL_CORE_0_FROM_ENTRY_3_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_3_S 1 +/** WCL_CORE_0_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ +#define WCL_CORE_0_CURRENT_3 (BIT(5)) +#define WCL_CORE_0_CURRENT_3_M (WCL_CORE_0_CURRENT_3_V << WCL_CORE_0_CURRENT_3_S) +#define WCL_CORE_0_CURRENT_3_V 0x00000001U +#define WCL_CORE_0_CURRENT_3_S 5 + +/** WCL_Core_0_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ +#define WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WCL_BASE + 0x8c) +/** WCL_CORE_0_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ +#define WCL_CORE_0_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_4_M (WCL_CORE_0_FROM_WORLD_4_V << WCL_CORE_0_FROM_WORLD_4_S) +#define WCL_CORE_0_FROM_WORLD_4_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_4_S 0 +/** WCL_CORE_0_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ +#define WCL_CORE_0_FROM_ENTRY_4 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_4_M (WCL_CORE_0_FROM_ENTRY_4_V << WCL_CORE_0_FROM_ENTRY_4_S) +#define WCL_CORE_0_FROM_ENTRY_4_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_4_S 1 +/** WCL_CORE_0_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ +#define WCL_CORE_0_CURRENT_4 (BIT(5)) +#define WCL_CORE_0_CURRENT_4_M (WCL_CORE_0_CURRENT_4_V << WCL_CORE_0_CURRENT_4_S) +#define WCL_CORE_0_CURRENT_4_V 0x00000001U +#define WCL_CORE_0_CURRENT_4_S 5 + +/** WCL_Core_0_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ +#define WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WCL_BASE + 0x90) +/** WCL_CORE_0_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ +#define WCL_CORE_0_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_5_M (WCL_CORE_0_FROM_WORLD_5_V << WCL_CORE_0_FROM_WORLD_5_S) +#define WCL_CORE_0_FROM_WORLD_5_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_5_S 0 +/** WCL_CORE_0_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ +#define WCL_CORE_0_FROM_ENTRY_5 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_5_M (WCL_CORE_0_FROM_ENTRY_5_V << WCL_CORE_0_FROM_ENTRY_5_S) +#define WCL_CORE_0_FROM_ENTRY_5_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_5_S 1 +/** WCL_CORE_0_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ +#define WCL_CORE_0_CURRENT_5 (BIT(5)) +#define WCL_CORE_0_CURRENT_5_M (WCL_CORE_0_CURRENT_5_V << WCL_CORE_0_CURRENT_5_S) +#define WCL_CORE_0_CURRENT_5_V 0x00000001U +#define WCL_CORE_0_CURRENT_5_S 5 + +/** WCL_Core_0_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ +#define WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WCL_BASE + 0x94) +/** WCL_CORE_0_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ +#define WCL_CORE_0_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_6_M (WCL_CORE_0_FROM_WORLD_6_V << WCL_CORE_0_FROM_WORLD_6_S) +#define WCL_CORE_0_FROM_WORLD_6_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_6_S 0 +/** WCL_CORE_0_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ +#define WCL_CORE_0_FROM_ENTRY_6 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_6_M (WCL_CORE_0_FROM_ENTRY_6_V << WCL_CORE_0_FROM_ENTRY_6_S) +#define WCL_CORE_0_FROM_ENTRY_6_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_6_S 1 +/** WCL_CORE_0_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ +#define WCL_CORE_0_CURRENT_6 (BIT(5)) +#define WCL_CORE_0_CURRENT_6_M (WCL_CORE_0_CURRENT_6_V << WCL_CORE_0_CURRENT_6_S) +#define WCL_CORE_0_CURRENT_6_V 0x00000001U +#define WCL_CORE_0_CURRENT_6_S 5 + +/** WCL_Core_0_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ +#define WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WCL_BASE + 0x98) +/** WCL_CORE_0_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ +#define WCL_CORE_0_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_7_M (WCL_CORE_0_FROM_WORLD_7_V << WCL_CORE_0_FROM_WORLD_7_S) +#define WCL_CORE_0_FROM_WORLD_7_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_7_S 0 +/** WCL_CORE_0_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ +#define WCL_CORE_0_FROM_ENTRY_7 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_7_M (WCL_CORE_0_FROM_ENTRY_7_V << WCL_CORE_0_FROM_ENTRY_7_S) +#define WCL_CORE_0_FROM_ENTRY_7_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_7_S 1 +/** WCL_CORE_0_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ +#define WCL_CORE_0_CURRENT_7 (BIT(5)) +#define WCL_CORE_0_CURRENT_7_M (WCL_CORE_0_CURRENT_7_V << WCL_CORE_0_CURRENT_7_S) +#define WCL_CORE_0_CURRENT_7_V 0x00000001U +#define WCL_CORE_0_CURRENT_7_S 5 + +/** WCL_Core_0_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ +#define WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WCL_BASE + 0x9c) +/** WCL_CORE_0_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ +#define WCL_CORE_0_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_8_M (WCL_CORE_0_FROM_WORLD_8_V << WCL_CORE_0_FROM_WORLD_8_S) +#define WCL_CORE_0_FROM_WORLD_8_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_8_S 0 +/** WCL_CORE_0_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ +#define WCL_CORE_0_FROM_ENTRY_8 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_8_M (WCL_CORE_0_FROM_ENTRY_8_V << WCL_CORE_0_FROM_ENTRY_8_S) +#define WCL_CORE_0_FROM_ENTRY_8_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_8_S 1 +/** WCL_CORE_0_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ +#define WCL_CORE_0_CURRENT_8 (BIT(5)) +#define WCL_CORE_0_CURRENT_8_M (WCL_CORE_0_CURRENT_8_V << WCL_CORE_0_CURRENT_8_S) +#define WCL_CORE_0_CURRENT_8_V 0x00000001U +#define WCL_CORE_0_CURRENT_8_S 5 + +/** WCL_Core_0_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ +#define WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WCL_BASE + 0xa0) +/** WCL_CORE_0_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ +#define WCL_CORE_0_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_9_M (WCL_CORE_0_FROM_WORLD_9_V << WCL_CORE_0_FROM_WORLD_9_S) +#define WCL_CORE_0_FROM_WORLD_9_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_9_S 0 +/** WCL_CORE_0_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ +#define WCL_CORE_0_FROM_ENTRY_9 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_9_M (WCL_CORE_0_FROM_ENTRY_9_V << WCL_CORE_0_FROM_ENTRY_9_S) +#define WCL_CORE_0_FROM_ENTRY_9_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_9_S 1 +/** WCL_CORE_0_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ +#define WCL_CORE_0_CURRENT_9 (BIT(5)) +#define WCL_CORE_0_CURRENT_9_M (WCL_CORE_0_CURRENT_9_V << WCL_CORE_0_CURRENT_9_S) +#define WCL_CORE_0_CURRENT_9_V 0x00000001U +#define WCL_CORE_0_CURRENT_9_S 5 + +/** WCL_Core_0_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ +#define WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WCL_BASE + 0xa4) +/** WCL_CORE_0_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ +#define WCL_CORE_0_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_10_M (WCL_CORE_0_FROM_WORLD_10_V << WCL_CORE_0_FROM_WORLD_10_S) +#define WCL_CORE_0_FROM_WORLD_10_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_10_S 0 +/** WCL_CORE_0_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ +#define WCL_CORE_0_FROM_ENTRY_10 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_10_M (WCL_CORE_0_FROM_ENTRY_10_V << WCL_CORE_0_FROM_ENTRY_10_S) +#define WCL_CORE_0_FROM_ENTRY_10_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_10_S 1 +/** WCL_CORE_0_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ +#define WCL_CORE_0_CURRENT_10 (BIT(5)) +#define WCL_CORE_0_CURRENT_10_M (WCL_CORE_0_CURRENT_10_V << WCL_CORE_0_CURRENT_10_S) +#define WCL_CORE_0_CURRENT_10_V 0x00000001U +#define WCL_CORE_0_CURRENT_10_S 5 + +/** WCL_Core_0_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ +#define WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WCL_BASE + 0xa8) +/** WCL_CORE_0_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ +#define WCL_CORE_0_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_11_M (WCL_CORE_0_FROM_WORLD_11_V << WCL_CORE_0_FROM_WORLD_11_S) +#define WCL_CORE_0_FROM_WORLD_11_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_11_S 0 +/** WCL_CORE_0_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ +#define WCL_CORE_0_FROM_ENTRY_11 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_11_M (WCL_CORE_0_FROM_ENTRY_11_V << WCL_CORE_0_FROM_ENTRY_11_S) +#define WCL_CORE_0_FROM_ENTRY_11_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_11_S 1 +/** WCL_CORE_0_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ +#define WCL_CORE_0_CURRENT_11 (BIT(5)) +#define WCL_CORE_0_CURRENT_11_M (WCL_CORE_0_CURRENT_11_V << WCL_CORE_0_CURRENT_11_S) +#define WCL_CORE_0_CURRENT_11_V 0x00000001U +#define WCL_CORE_0_CURRENT_11_S 5 + +/** WCL_Core_0_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ +#define WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WCL_BASE + 0xac) +/** WCL_CORE_0_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ +#define WCL_CORE_0_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_12_M (WCL_CORE_0_FROM_WORLD_12_V << WCL_CORE_0_FROM_WORLD_12_S) +#define WCL_CORE_0_FROM_WORLD_12_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_12_S 0 +/** WCL_CORE_0_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ +#define WCL_CORE_0_FROM_ENTRY_12 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_12_M (WCL_CORE_0_FROM_ENTRY_12_V << WCL_CORE_0_FROM_ENTRY_12_S) +#define WCL_CORE_0_FROM_ENTRY_12_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_12_S 1 +/** WCL_CORE_0_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ +#define WCL_CORE_0_CURRENT_12 (BIT(5)) +#define WCL_CORE_0_CURRENT_12_M (WCL_CORE_0_CURRENT_12_V << WCL_CORE_0_CURRENT_12_S) +#define WCL_CORE_0_CURRENT_12_V 0x00000001U +#define WCL_CORE_0_CURRENT_12_S 5 + +/** WCL_Core_0_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ +#define WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WCL_BASE + 0xb0) +/** WCL_CORE_0_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ +#define WCL_CORE_0_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_13_M (WCL_CORE_0_FROM_WORLD_13_V << WCL_CORE_0_FROM_WORLD_13_S) +#define WCL_CORE_0_FROM_WORLD_13_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_13_S 0 +/** WCL_CORE_0_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ +#define WCL_CORE_0_FROM_ENTRY_13 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_13_M (WCL_CORE_0_FROM_ENTRY_13_V << WCL_CORE_0_FROM_ENTRY_13_S) +#define WCL_CORE_0_FROM_ENTRY_13_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_13_S 1 +/** WCL_CORE_0_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ +#define WCL_CORE_0_CURRENT_13 (BIT(5)) +#define WCL_CORE_0_CURRENT_13_M (WCL_CORE_0_CURRENT_13_V << WCL_CORE_0_CURRENT_13_S) +#define WCL_CORE_0_CURRENT_13_V 0x00000001U +#define WCL_CORE_0_CURRENT_13_S 5 + +/** WCL_Core_0_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ +#define WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WCL_BASE + 0xfc) +/** WCL_CORE_0_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 + * represents the current field of STATUSTABLE2 + */ +#define WCL_CORE_0_STATUSTABLE_CURRENT 0x00001FFFU +#define WCL_CORE_0_STATUSTABLE_CURRENT_M (WCL_CORE_0_STATUSTABLE_CURRENT_V << WCL_CORE_0_STATUSTABLE_CURRENT_S) +#define WCL_CORE_0_STATUSTABLE_CURRENT_V 0x00001FFFU +#define WCL_CORE_0_STATUSTABLE_CURRENT_S 1 + +/** WCL_Core_0_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ +#define WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WCL_BASE + 0x100) +/** WCL_CORE_0_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ +#define WCL_CORE_0_MESSAGE_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_MESSAGE_ADDR_M (WCL_CORE_0_MESSAGE_ADDR_V << WCL_CORE_0_MESSAGE_ADDR_S) +#define WCL_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_MESSAGE_ADDR_S 0 + +/** WCL_Core_0_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ +#define WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WCL_BASE + 0x104) +/** WCL_CORE_0_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ +#define WCL_CORE_0_MESSAGE_MAX 0x0000000FU +#define WCL_CORE_0_MESSAGE_MAX_M (WCL_CORE_0_MESSAGE_MAX_V << WCL_CORE_0_MESSAGE_MAX_S) +#define WCL_CORE_0_MESSAGE_MAX_V 0x0000000FU +#define WCL_CORE_0_MESSAGE_MAX_S 0 + +/** WCL_Core_0_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ +#define WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WCL_BASE + 0x108) +/** WCL_CORE_0_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ +#define WCL_CORE_0_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_0_MESSAGE_MATCH_M (WCL_CORE_0_MESSAGE_MATCH_V << WCL_CORE_0_MESSAGE_MATCH_S) +#define WCL_CORE_0_MESSAGE_MATCH_V 0x00000001U +#define WCL_CORE_0_MESSAGE_MATCH_S 0 +/** WCL_CORE_0_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ +#define WCL_CORE_0_MESSAGE_EXPECT 0x0000000FU +#define WCL_CORE_0_MESSAGE_EXPECT_M (WCL_CORE_0_MESSAGE_EXPECT_V << WCL_CORE_0_MESSAGE_EXPECT_S) +#define WCL_CORE_0_MESSAGE_EXPECT_V 0x0000000FU +#define WCL_CORE_0_MESSAGE_EXPECT_S 1 +/** WCL_CORE_0_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking data + */ +#define WCL_CORE_0_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_0_MESSAGE_DATAPHASE_M (WCL_CORE_0_MESSAGE_DATAPHASE_V << WCL_CORE_0_MESSAGE_DATAPHASE_S) +#define WCL_CORE_0_MESSAGE_DATAPHASE_V 0x00000001U +#define WCL_CORE_0_MESSAGE_DATAPHASE_S 5 +/** WCL_CORE_0_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking address. + */ +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_M (WCL_CORE_0_MESSAGE_ADDRESSPHASE_V << WCL_CORE_0_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_V 0x00000001U +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_S 6 + +/** WCL_Core_0_World_TRIGGER_ADDR_REG register + * Core_0 trigger address configuration Register + */ +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x140) +/** WCL_CORE_0_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ +#define WCL_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_M (WCL_CORE_0_WORLD_TRIGGER_ADDR_V << WCL_CORE_0_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_S 0 + +/** WCL_Core_0_World_PREPARE_REG register + * Core_0 prepare world configuration Register + */ +#define WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WCL_BASE + 0x144) +/** WCL_CORE_0_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + */ +#define WCL_CORE_0_WORLD_PREPARE 0x00000003U +#define WCL_CORE_0_WORLD_PREPARE_M (WCL_CORE_0_WORLD_PREPARE_V << WCL_CORE_0_WORLD_PREPARE_S) +#define WCL_CORE_0_WORLD_PREPARE_V 0x00000003U +#define WCL_CORE_0_WORLD_PREPARE_S 0 + +/** WCL_Core_0_World_UPDATE_REG register + * Core_0 configuration update register + */ +#define WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WCL_BASE + 0x148) +/** WCL_CORE_0_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ +#define WCL_CORE_0_UPDATE 0xFFFFFFFFU +#define WCL_CORE_0_UPDATE_M (WCL_CORE_0_UPDATE_V << WCL_CORE_0_UPDATE_S) +#define WCL_CORE_0_UPDATE_V 0xFFFFFFFFU +#define WCL_CORE_0_UPDATE_S 0 + +/** WCL_Core_0_World_Cancel_REG register + * Core_0 configuration cancel register + */ +#define WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WCL_BASE + 0x14c) +/** WCL_CORE_0_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,use this register to cancel world switch, jujst need + * write any value,the hardware only checks the write operation of this register and + * does not case about its value + */ +#define WCL_CORE_0_WORLD_CANCEL 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_CANCEL_M (WCL_CORE_0_WORLD_CANCEL_V << WCL_CORE_0_WORLD_CANCEL_S) +#define WCL_CORE_0_WORLD_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_CANCEL_S 0 + +/** WCL_Core_0_World_IRam0_REG register + * Core_0 Iram0 world register + */ +#define WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WCL_BASE + 0x150) +/** WCL_CORE_0_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ +#define WCL_CORE_0_WORLD_IRAM0 0x00000003U +#define WCL_CORE_0_WORLD_IRAM0_M (WCL_CORE_0_WORLD_IRAM0_V << WCL_CORE_0_WORLD_IRAM0_S) +#define WCL_CORE_0_WORLD_IRAM0_V 0x00000003U +#define WCL_CORE_0_WORLD_IRAM0_S 0 + +/** WCL_Core_0_World_DRam0_PIF_REG register + * Core_0 dram0 and PIF world register + */ +#define WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WCL_BASE + 0x154) +/** WCL_CORE_0_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ +#define WCL_CORE_0_WORLD_DRAM0_PIF 0x00000003U +#define WCL_CORE_0_WORLD_DRAM0_PIF_M (WCL_CORE_0_WORLD_DRAM0_PIF_V << WCL_CORE_0_WORLD_DRAM0_PIF_S) +#define WCL_CORE_0_WORLD_DRAM0_PIF_V 0x00000003U +#define WCL_CORE_0_WORLD_DRAM0_PIF_S 0 + +/** WCL_Core_0_World_Phase_REG register + * Core_0 world status register + */ +#define WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WCL_BASE + 0x158) +/** WCL_CORE_0_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1, 1 means value. + */ +#define WCL_CORE_0_WORLD_PHASE (BIT(0)) +#define WCL_CORE_0_WORLD_PHASE_M (WCL_CORE_0_WORLD_PHASE_V << WCL_CORE_0_WORLD_PHASE_S) +#define WCL_CORE_0_WORLD_PHASE_V 0x00000001U +#define WCL_CORE_0_WORLD_PHASE_S 0 + +/** WCL_Core_0_NMI_MASK_ENABLE_REG register + * Core_0 NMI mask enable register + */ +#define WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WCL_BASE + 0x180) +/** WCL_CORE_0_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask,it can write any value,when write this + * register,the hardware start masking NMI interrupt + */ +#define WCL_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_ENABLE_M (WCL_CORE_0_NMI_MASK_ENABLE_V << WCL_CORE_0_NMI_MASK_ENABLE_S) +#define WCL_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_ENABLE_S 0 + +/** WCL_Core_0_NMI_MASK_TRIGGER_ADDR_REG register + * Core_0 NMI mask trigger address register + */ +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x184) +/** WCL_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address, when CPU executes to this address,NMI + * mask automatically fails + */ +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 + +/** WCL_Core_0_NMI_MASK_DISABLE_REG register + * Core_0 NMI mask disable register + */ +#define WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WCL_BASE + 0x188) +/** WCL_CORE_0_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask,it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ +#define WCL_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_DISABLE_M (WCL_CORE_0_NMI_MASK_DISABLE_V << WCL_CORE_0_NMI_MASK_DISABLE_S) +#define WCL_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_DISABLE_S 0 + +/** WCL_Core_0_NMI_MASK_CANCLE_REG register + * Core_0 NMI mask disable register + */ +#define WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WCL_BASE + 0x18c) +/** WCL_CORE_0_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ +#define WCL_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_CANCEL_M (WCL_CORE_0_NMI_MASK_CANCEL_V << WCL_CORE_0_NMI_MASK_CANCEL_S) +#define WCL_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_CANCEL_S 0 + +/** WCL_Core_0_NMI_MASK_REG register + * Core_0 NMI mask register + */ +#define WCL_CORE_0_NMI_MASK_REG (DR_REG_WCL_BASE + 0x190) +/** WCL_CORE_0_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ +#define WCL_CORE_0_NMI_MASK (BIT(0)) +#define WCL_CORE_0_NMI_MASK_M (WCL_CORE_0_NMI_MASK_V << WCL_CORE_0_NMI_MASK_S) +#define WCL_CORE_0_NMI_MASK_V 0x00000001U +#define WCL_CORE_0_NMI_MASK_S 0 + +/** WCL_Core_0_NMI_MASK_PHASE_REG register + * Core_0 NMI mask phase register + */ +#define WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WCL_BASE + 0x194) +/** WCL_CORE_0_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ +#define WCL_CORE_0_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_0_NMI_MASK_PHASE_M (WCL_CORE_0_NMI_MASK_PHASE_V << WCL_CORE_0_NMI_MASK_PHASE_S) +#define WCL_CORE_0_NMI_MASK_PHASE_V 0x00000001U +#define WCL_CORE_0_NMI_MASK_PHASE_S 0 + +/** WCL_Core_1_ENTRY_1_ADDR_REG register + * Core_1 Entry 1 address configuration Register + */ +#define WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WCL_BASE + 0x400) +/** WCL_CORE_1_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 1 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_1_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_1_ADDR_M (WCL_CORE_1_ENTRY_1_ADDR_V << WCL_CORE_1_ENTRY_1_ADDR_S) +#define WCL_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_1_ADDR_S 0 + +/** WCL_Core_1_ENTRY_2_ADDR_REG register + * Core_1 Entry 2 address configuration Register + */ +#define WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WCL_BASE + 0x404) +/** WCL_CORE_1_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 2 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_2_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_2_ADDR_M (WCL_CORE_1_ENTRY_2_ADDR_V << WCL_CORE_1_ENTRY_2_ADDR_S) +#define WCL_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_2_ADDR_S 0 + +/** WCL_Core_1_ENTRY_3_ADDR_REG register + * Core_1 Entry 3 address configuration Register + */ +#define WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WCL_BASE + 0x408) +/** WCL_CORE_1_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 3 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_3_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_3_ADDR_M (WCL_CORE_1_ENTRY_3_ADDR_V << WCL_CORE_1_ENTRY_3_ADDR_S) +#define WCL_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_3_ADDR_S 0 + +/** WCL_Core_1_ENTRY_4_ADDR_REG register + * Core_1 Entry 4 address configuration Register + */ +#define WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WCL_BASE + 0x40c) +/** WCL_CORE_1_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 4 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_4_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_4_ADDR_M (WCL_CORE_1_ENTRY_4_ADDR_V << WCL_CORE_1_ENTRY_4_ADDR_S) +#define WCL_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_4_ADDR_S 0 + +/** WCL_Core_1_ENTRY_5_ADDR_REG register + * Core_1 Entry 5 address configuration Register + */ +#define WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WCL_BASE + 0x410) +/** WCL_CORE_1_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 5 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_5_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_5_ADDR_M (WCL_CORE_1_ENTRY_5_ADDR_V << WCL_CORE_1_ENTRY_5_ADDR_S) +#define WCL_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_5_ADDR_S 0 + +/** WCL_Core_1_ENTRY_6_ADDR_REG register + * Core_1 Entry 6 address configuration Register + */ +#define WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WCL_BASE + 0x414) +/** WCL_CORE_1_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 6 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_6_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_6_ADDR_M (WCL_CORE_1_ENTRY_6_ADDR_V << WCL_CORE_1_ENTRY_6_ADDR_S) +#define WCL_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_6_ADDR_S 0 + +/** WCL_Core_1_ENTRY_7_ADDR_REG register + * Core_1 Entry 7 address configuration Register + */ +#define WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WCL_BASE + 0x418) +/** WCL_CORE_1_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 7 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_7_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_7_ADDR_M (WCL_CORE_1_ENTRY_7_ADDR_V << WCL_CORE_1_ENTRY_7_ADDR_S) +#define WCL_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_7_ADDR_S 0 + +/** WCL_Core_1_ENTRY_8_ADDR_REG register + * Core_1 Entry 8 address configuration Register + */ +#define WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WCL_BASE + 0x41c) +/** WCL_CORE_1_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 8 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_8_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_8_ADDR_M (WCL_CORE_1_ENTRY_8_ADDR_V << WCL_CORE_1_ENTRY_8_ADDR_S) +#define WCL_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_8_ADDR_S 0 + +/** WCL_Core_1_ENTRY_9_ADDR_REG register + * Core_1 Entry 9 address configuration Register + */ +#define WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WCL_BASE + 0x420) +/** WCL_CORE_1_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 9 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_9_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_9_ADDR_M (WCL_CORE_1_ENTRY_9_ADDR_V << WCL_CORE_1_ENTRY_9_ADDR_S) +#define WCL_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_9_ADDR_S 0 + +/** WCL_Core_1_ENTRY_10_ADDR_REG register + * Core_1 Entry 10 address configuration Register + */ +#define WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WCL_BASE + 0x424) +/** WCL_CORE_1_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 10 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_10_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_10_ADDR_M (WCL_CORE_1_ENTRY_10_ADDR_V << WCL_CORE_1_ENTRY_10_ADDR_S) +#define WCL_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_10_ADDR_S 0 + +/** WCL_Core_1_ENTRY_11_ADDR_REG register + * Core_1 Entry 11 address configuration Register + */ +#define WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WCL_BASE + 0x428) +/** WCL_CORE_1_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 11 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_11_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_11_ADDR_M (WCL_CORE_1_ENTRY_11_ADDR_V << WCL_CORE_1_ENTRY_11_ADDR_S) +#define WCL_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_11_ADDR_S 0 + +/** WCL_Core_1_ENTRY_12_ADDR_REG register + * Core_1 Entry 12 address configuration Register + */ +#define WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WCL_BASE + 0x42c) +/** WCL_CORE_1_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 12 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_12_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_12_ADDR_M (WCL_CORE_1_ENTRY_12_ADDR_V << WCL_CORE_1_ENTRY_12_ADDR_S) +#define WCL_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_12_ADDR_S 0 + +/** WCL_Core_1_ENTRY_13_ADDR_REG register + * Core_1 Entry 13 address configuration Register + */ +#define WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WCL_BASE + 0x430) +/** WCL_CORE_1_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 13 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_13_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_13_ADDR_M (WCL_CORE_1_ENTRY_13_ADDR_V << WCL_CORE_1_ENTRY_13_ADDR_S) +#define WCL_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_13_ADDR_S 0 + +/** WCL_Core_1_ENTRY_CHECK_REG register + * Core_1 Entry check configuration Register + */ +#define WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WCL_BASE + 0x47c) +/** WCL_CORE_1_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ +#define WCL_CORE_1_ENTRY_CHECK 0x00001FFFU +#define WCL_CORE_1_ENTRY_CHECK_M (WCL_CORE_1_ENTRY_CHECK_V << WCL_CORE_1_ENTRY_CHECK_S) +#define WCL_CORE_1_ENTRY_CHECK_V 0x00001FFFU +#define WCL_CORE_1_ENTRY_CHECK_S 1 + +/** WCL_Core_1_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ +#define WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WCL_BASE + 0x480) +/** WCL_CORE_1_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ +#define WCL_CORE_1_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_1_M (WCL_CORE_1_FROM_WORLD_1_V << WCL_CORE_1_FROM_WORLD_1_S) +#define WCL_CORE_1_FROM_WORLD_1_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_1_S 0 +/** WCL_CORE_1_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ +#define WCL_CORE_1_FROM_ENTRY_1 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_1_M (WCL_CORE_1_FROM_ENTRY_1_V << WCL_CORE_1_FROM_ENTRY_1_S) +#define WCL_CORE_1_FROM_ENTRY_1_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_1_S 1 +/** WCL_CORE_1_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ +#define WCL_CORE_1_CURRENT_1 (BIT(5)) +#define WCL_CORE_1_CURRENT_1_M (WCL_CORE_1_CURRENT_1_V << WCL_CORE_1_CURRENT_1_S) +#define WCL_CORE_1_CURRENT_1_V 0x00000001U +#define WCL_CORE_1_CURRENT_1_S 5 + +/** WCL_Core_1_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ +#define WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WCL_BASE + 0x484) +/** WCL_CORE_1_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ +#define WCL_CORE_1_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_2_M (WCL_CORE_1_FROM_WORLD_2_V << WCL_CORE_1_FROM_WORLD_2_S) +#define WCL_CORE_1_FROM_WORLD_2_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_2_S 0 +/** WCL_CORE_1_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ +#define WCL_CORE_1_FROM_ENTRY_2 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_2_M (WCL_CORE_1_FROM_ENTRY_2_V << WCL_CORE_1_FROM_ENTRY_2_S) +#define WCL_CORE_1_FROM_ENTRY_2_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_2_S 1 +/** WCL_CORE_1_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ +#define WCL_CORE_1_CURRENT_2 (BIT(5)) +#define WCL_CORE_1_CURRENT_2_M (WCL_CORE_1_CURRENT_2_V << WCL_CORE_1_CURRENT_2_S) +#define WCL_CORE_1_CURRENT_2_V 0x00000001U +#define WCL_CORE_1_CURRENT_2_S 5 + +/** WCL_Core_1_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ +#define WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WCL_BASE + 0x488) +/** WCL_CORE_1_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ +#define WCL_CORE_1_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_3_M (WCL_CORE_1_FROM_WORLD_3_V << WCL_CORE_1_FROM_WORLD_3_S) +#define WCL_CORE_1_FROM_WORLD_3_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_3_S 0 +/** WCL_CORE_1_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ +#define WCL_CORE_1_FROM_ENTRY_3 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_3_M (WCL_CORE_1_FROM_ENTRY_3_V << WCL_CORE_1_FROM_ENTRY_3_S) +#define WCL_CORE_1_FROM_ENTRY_3_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_3_S 1 +/** WCL_CORE_1_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ +#define WCL_CORE_1_CURRENT_3 (BIT(5)) +#define WCL_CORE_1_CURRENT_3_M (WCL_CORE_1_CURRENT_3_V << WCL_CORE_1_CURRENT_3_S) +#define WCL_CORE_1_CURRENT_3_V 0x00000001U +#define WCL_CORE_1_CURRENT_3_S 5 + +/** WCL_Core_1_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ +#define WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WCL_BASE + 0x48c) +/** WCL_CORE_1_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ +#define WCL_CORE_1_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_4_M (WCL_CORE_1_FROM_WORLD_4_V << WCL_CORE_1_FROM_WORLD_4_S) +#define WCL_CORE_1_FROM_WORLD_4_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_4_S 0 +/** WCL_CORE_1_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ +#define WCL_CORE_1_FROM_ENTRY_4 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_4_M (WCL_CORE_1_FROM_ENTRY_4_V << WCL_CORE_1_FROM_ENTRY_4_S) +#define WCL_CORE_1_FROM_ENTRY_4_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_4_S 1 +/** WCL_CORE_1_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ +#define WCL_CORE_1_CURRENT_4 (BIT(5)) +#define WCL_CORE_1_CURRENT_4_M (WCL_CORE_1_CURRENT_4_V << WCL_CORE_1_CURRENT_4_S) +#define WCL_CORE_1_CURRENT_4_V 0x00000001U +#define WCL_CORE_1_CURRENT_4_S 5 + +/** WCL_Core_1_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ +#define WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WCL_BASE + 0x490) +/** WCL_CORE_1_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ +#define WCL_CORE_1_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_5_M (WCL_CORE_1_FROM_WORLD_5_V << WCL_CORE_1_FROM_WORLD_5_S) +#define WCL_CORE_1_FROM_WORLD_5_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_5_S 0 +/** WCL_CORE_1_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ +#define WCL_CORE_1_FROM_ENTRY_5 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_5_M (WCL_CORE_1_FROM_ENTRY_5_V << WCL_CORE_1_FROM_ENTRY_5_S) +#define WCL_CORE_1_FROM_ENTRY_5_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_5_S 1 +/** WCL_CORE_1_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ +#define WCL_CORE_1_CURRENT_5 (BIT(5)) +#define WCL_CORE_1_CURRENT_5_M (WCL_CORE_1_CURRENT_5_V << WCL_CORE_1_CURRENT_5_S) +#define WCL_CORE_1_CURRENT_5_V 0x00000001U +#define WCL_CORE_1_CURRENT_5_S 5 + +/** WCL_Core_1_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ +#define WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WCL_BASE + 0x494) +/** WCL_CORE_1_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ +#define WCL_CORE_1_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_6_M (WCL_CORE_1_FROM_WORLD_6_V << WCL_CORE_1_FROM_WORLD_6_S) +#define WCL_CORE_1_FROM_WORLD_6_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_6_S 0 +/** WCL_CORE_1_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ +#define WCL_CORE_1_FROM_ENTRY_6 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_6_M (WCL_CORE_1_FROM_ENTRY_6_V << WCL_CORE_1_FROM_ENTRY_6_S) +#define WCL_CORE_1_FROM_ENTRY_6_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_6_S 1 +/** WCL_CORE_1_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ +#define WCL_CORE_1_CURRENT_6 (BIT(5)) +#define WCL_CORE_1_CURRENT_6_M (WCL_CORE_1_CURRENT_6_V << WCL_CORE_1_CURRENT_6_S) +#define WCL_CORE_1_CURRENT_6_V 0x00000001U +#define WCL_CORE_1_CURRENT_6_S 5 + +/** WCL_Core_1_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ +#define WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WCL_BASE + 0x498) +/** WCL_CORE_1_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ +#define WCL_CORE_1_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_7_M (WCL_CORE_1_FROM_WORLD_7_V << WCL_CORE_1_FROM_WORLD_7_S) +#define WCL_CORE_1_FROM_WORLD_7_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_7_S 0 +/** WCL_CORE_1_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ +#define WCL_CORE_1_FROM_ENTRY_7 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_7_M (WCL_CORE_1_FROM_ENTRY_7_V << WCL_CORE_1_FROM_ENTRY_7_S) +#define WCL_CORE_1_FROM_ENTRY_7_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_7_S 1 +/** WCL_CORE_1_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ +#define WCL_CORE_1_CURRENT_7 (BIT(5)) +#define WCL_CORE_1_CURRENT_7_M (WCL_CORE_1_CURRENT_7_V << WCL_CORE_1_CURRENT_7_S) +#define WCL_CORE_1_CURRENT_7_V 0x00000001U +#define WCL_CORE_1_CURRENT_7_S 5 + +/** WCL_Core_1_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ +#define WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WCL_BASE + 0x49c) +/** WCL_CORE_1_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ +#define WCL_CORE_1_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_8_M (WCL_CORE_1_FROM_WORLD_8_V << WCL_CORE_1_FROM_WORLD_8_S) +#define WCL_CORE_1_FROM_WORLD_8_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_8_S 0 +/** WCL_CORE_1_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ +#define WCL_CORE_1_FROM_ENTRY_8 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_8_M (WCL_CORE_1_FROM_ENTRY_8_V << WCL_CORE_1_FROM_ENTRY_8_S) +#define WCL_CORE_1_FROM_ENTRY_8_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_8_S 1 +/** WCL_CORE_1_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ +#define WCL_CORE_1_CURRENT_8 (BIT(5)) +#define WCL_CORE_1_CURRENT_8_M (WCL_CORE_1_CURRENT_8_V << WCL_CORE_1_CURRENT_8_S) +#define WCL_CORE_1_CURRENT_8_V 0x00000001U +#define WCL_CORE_1_CURRENT_8_S 5 + +/** WCL_Core_1_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ +#define WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WCL_BASE + 0x4a0) +/** WCL_CORE_1_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ +#define WCL_CORE_1_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_9_M (WCL_CORE_1_FROM_WORLD_9_V << WCL_CORE_1_FROM_WORLD_9_S) +#define WCL_CORE_1_FROM_WORLD_9_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_9_S 0 +/** WCL_CORE_1_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ +#define WCL_CORE_1_FROM_ENTRY_9 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_9_M (WCL_CORE_1_FROM_ENTRY_9_V << WCL_CORE_1_FROM_ENTRY_9_S) +#define WCL_CORE_1_FROM_ENTRY_9_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_9_S 1 +/** WCL_CORE_1_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ +#define WCL_CORE_1_CURRENT_9 (BIT(5)) +#define WCL_CORE_1_CURRENT_9_M (WCL_CORE_1_CURRENT_9_V << WCL_CORE_1_CURRENT_9_S) +#define WCL_CORE_1_CURRENT_9_V 0x00000001U +#define WCL_CORE_1_CURRENT_9_S 5 + +/** WCL_Core_1_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ +#define WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WCL_BASE + 0x4a4) +/** WCL_CORE_1_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ +#define WCL_CORE_1_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_10_M (WCL_CORE_1_FROM_WORLD_10_V << WCL_CORE_1_FROM_WORLD_10_S) +#define WCL_CORE_1_FROM_WORLD_10_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_10_S 0 +/** WCL_CORE_1_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ +#define WCL_CORE_1_FROM_ENTRY_10 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_10_M (WCL_CORE_1_FROM_ENTRY_10_V << WCL_CORE_1_FROM_ENTRY_10_S) +#define WCL_CORE_1_FROM_ENTRY_10_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_10_S 1 +/** WCL_CORE_1_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ +#define WCL_CORE_1_CURRENT_10 (BIT(5)) +#define WCL_CORE_1_CURRENT_10_M (WCL_CORE_1_CURRENT_10_V << WCL_CORE_1_CURRENT_10_S) +#define WCL_CORE_1_CURRENT_10_V 0x00000001U +#define WCL_CORE_1_CURRENT_10_S 5 + +/** WCL_Core_1_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ +#define WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WCL_BASE + 0x4a8) +/** WCL_CORE_1_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ +#define WCL_CORE_1_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_11_M (WCL_CORE_1_FROM_WORLD_11_V << WCL_CORE_1_FROM_WORLD_11_S) +#define WCL_CORE_1_FROM_WORLD_11_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_11_S 0 +/** WCL_CORE_1_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ +#define WCL_CORE_1_FROM_ENTRY_11 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_11_M (WCL_CORE_1_FROM_ENTRY_11_V << WCL_CORE_1_FROM_ENTRY_11_S) +#define WCL_CORE_1_FROM_ENTRY_11_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_11_S 1 +/** WCL_CORE_1_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ +#define WCL_CORE_1_CURRENT_11 (BIT(5)) +#define WCL_CORE_1_CURRENT_11_M (WCL_CORE_1_CURRENT_11_V << WCL_CORE_1_CURRENT_11_S) +#define WCL_CORE_1_CURRENT_11_V 0x00000001U +#define WCL_CORE_1_CURRENT_11_S 5 + +/** WCL_Core_1_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ +#define WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WCL_BASE + 0x4ac) +/** WCL_CORE_1_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ +#define WCL_CORE_1_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_12_M (WCL_CORE_1_FROM_WORLD_12_V << WCL_CORE_1_FROM_WORLD_12_S) +#define WCL_CORE_1_FROM_WORLD_12_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_12_S 0 +/** WCL_CORE_1_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ +#define WCL_CORE_1_FROM_ENTRY_12 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_12_M (WCL_CORE_1_FROM_ENTRY_12_V << WCL_CORE_1_FROM_ENTRY_12_S) +#define WCL_CORE_1_FROM_ENTRY_12_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_12_S 1 +/** WCL_CORE_1_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ +#define WCL_CORE_1_CURRENT_12 (BIT(5)) +#define WCL_CORE_1_CURRENT_12_M (WCL_CORE_1_CURRENT_12_V << WCL_CORE_1_CURRENT_12_S) +#define WCL_CORE_1_CURRENT_12_V 0x00000001U +#define WCL_CORE_1_CURRENT_12_S 5 + +/** WCL_Core_1_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ +#define WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WCL_BASE + 0x4b0) +/** WCL_CORE_1_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ +#define WCL_CORE_1_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_13_M (WCL_CORE_1_FROM_WORLD_13_V << WCL_CORE_1_FROM_WORLD_13_S) +#define WCL_CORE_1_FROM_WORLD_13_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_13_S 0 +/** WCL_CORE_1_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ +#define WCL_CORE_1_FROM_ENTRY_13 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_13_M (WCL_CORE_1_FROM_ENTRY_13_V << WCL_CORE_1_FROM_ENTRY_13_S) +#define WCL_CORE_1_FROM_ENTRY_13_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_13_S 1 +/** WCL_CORE_1_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ +#define WCL_CORE_1_CURRENT_13 (BIT(5)) +#define WCL_CORE_1_CURRENT_13_M (WCL_CORE_1_CURRENT_13_V << WCL_CORE_1_CURRENT_13_S) +#define WCL_CORE_1_CURRENT_13_V 0x00000001U +#define WCL_CORE_1_CURRENT_13_S 5 + +/** WCL_Core_1_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ +#define WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WCL_BASE + 0x4fc) +/** WCL_CORE_1_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1 + */ +#define WCL_CORE_1_STATUSTABLE_CURRENT 0x00001FFFU +#define WCL_CORE_1_STATUSTABLE_CURRENT_M (WCL_CORE_1_STATUSTABLE_CURRENT_V << WCL_CORE_1_STATUSTABLE_CURRENT_S) +#define WCL_CORE_1_STATUSTABLE_CURRENT_V 0x00001FFFU +#define WCL_CORE_1_STATUSTABLE_CURRENT_S 1 + +/** WCL_Core_1_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ +#define WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WCL_BASE + 0x500) +/** WCL_CORE_1_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ +#define WCL_CORE_1_MESSAGE_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_MESSAGE_ADDR_M (WCL_CORE_1_MESSAGE_ADDR_V << WCL_CORE_1_MESSAGE_ADDR_S) +#define WCL_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_MESSAGE_ADDR_S 0 + +/** WCL_Core_1_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ +#define WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WCL_BASE + 0x504) +/** WCL_CORE_1_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ +#define WCL_CORE_1_MESSAGE_MAX 0x0000000FU +#define WCL_CORE_1_MESSAGE_MAX_M (WCL_CORE_1_MESSAGE_MAX_V << WCL_CORE_1_MESSAGE_MAX_S) +#define WCL_CORE_1_MESSAGE_MAX_V 0x0000000FU +#define WCL_CORE_1_MESSAGE_MAX_S 0 + +/** WCL_Core_1_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ +#define WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WCL_BASE + 0x508) +/** WCL_CORE_1_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ +#define WCL_CORE_1_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_1_MESSAGE_MATCH_M (WCL_CORE_1_MESSAGE_MATCH_V << WCL_CORE_1_MESSAGE_MATCH_S) +#define WCL_CORE_1_MESSAGE_MATCH_V 0x00000001U +#define WCL_CORE_1_MESSAGE_MATCH_S 0 +/** WCL_CORE_1_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ +#define WCL_CORE_1_MESSAGE_EXPECT 0x0000000FU +#define WCL_CORE_1_MESSAGE_EXPECT_M (WCL_CORE_1_MESSAGE_EXPECT_V << WCL_CORE_1_MESSAGE_EXPECT_S) +#define WCL_CORE_1_MESSAGE_EXPECT_V 0x0000000FU +#define WCL_CORE_1_MESSAGE_EXPECT_S 1 +/** WCL_CORE_1_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking data + */ +#define WCL_CORE_1_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_1_MESSAGE_DATAPHASE_M (WCL_CORE_1_MESSAGE_DATAPHASE_V << WCL_CORE_1_MESSAGE_DATAPHASE_S) +#define WCL_CORE_1_MESSAGE_DATAPHASE_V 0x00000001U +#define WCL_CORE_1_MESSAGE_DATAPHASE_S 5 +/** WCL_CORE_1_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking address. + */ +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_M (WCL_CORE_1_MESSAGE_ADDRESSPHASE_V << WCL_CORE_1_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_V 0x00000001U +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_S 6 + +/** WCL_Core_1_World_TRIGGER_ADDR_REG register + * Core_1 trigger address configuration Register + */ +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x540) +/** WCL_CORE_1_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ +#define WCL_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_M (WCL_CORE_1_WORLD_TRIGGER_ADDR_V << WCL_CORE_1_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_S 0 + +/** WCL_Core_1_World_PREPARE_REG register + * Core_1 prepare world configuration Register + */ +#define WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WCL_BASE + 0x544) +/** WCL_CORE_1_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + */ +#define WCL_CORE_1_WORLD_PREPARE 0x00000003U +#define WCL_CORE_1_WORLD_PREPARE_M (WCL_CORE_1_WORLD_PREPARE_V << WCL_CORE_1_WORLD_PREPARE_S) +#define WCL_CORE_1_WORLD_PREPARE_V 0x00000003U +#define WCL_CORE_1_WORLD_PREPARE_S 0 + +/** WCL_Core_1_World_UPDATE_REG register + * Core_1 configuration update register + */ +#define WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WCL_BASE + 0x548) +/** WCL_CORE_1_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ +#define WCL_CORE_1_UPDATE 0xFFFFFFFFU +#define WCL_CORE_1_UPDATE_M (WCL_CORE_1_UPDATE_V << WCL_CORE_1_UPDATE_S) +#define WCL_CORE_1_UPDATE_V 0xFFFFFFFFU +#define WCL_CORE_1_UPDATE_S 0 + +/** WCL_Core_1_World_Cancel_REG register + * Core_1 configuration cancel register + */ +#define WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WCL_BASE + 0x54c) +/** WCL_CORE_1_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,can use this register to cancel world switch. can + * write any value, the hardware only checks the write operation of this register and + * does not case about its value + */ +#define WCL_CORE_1_WORLD_CANCEL 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_CANCEL_M (WCL_CORE_1_WORLD_CANCEL_V << WCL_CORE_1_WORLD_CANCEL_S) +#define WCL_CORE_1_WORLD_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_CANCEL_S 0 + +/** WCL_Core_1_World_IRam0_REG register + * Core_1 Iram0 world register + */ +#define WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WCL_BASE + 0x550) +/** WCL_CORE_1_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ +#define WCL_CORE_1_WORLD_IRAM0 0x00000003U +#define WCL_CORE_1_WORLD_IRAM0_M (WCL_CORE_1_WORLD_IRAM0_V << WCL_CORE_1_WORLD_IRAM0_S) +#define WCL_CORE_1_WORLD_IRAM0_V 0x00000003U +#define WCL_CORE_1_WORLD_IRAM0_S 0 + +/** WCL_Core_1_World_DRam0_PIF_REG register + * Core_1 dram0 and PIF world register + */ +#define WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WCL_BASE + 0x554) +/** WCL_CORE_1_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ +#define WCL_CORE_1_WORLD_DRAM0_PIF 0x00000003U +#define WCL_CORE_1_WORLD_DRAM0_PIF_M (WCL_CORE_1_WORLD_DRAM0_PIF_V << WCL_CORE_1_WORLD_DRAM0_PIF_S) +#define WCL_CORE_1_WORLD_DRAM0_PIF_V 0x00000003U +#define WCL_CORE_1_WORLD_DRAM0_PIF_S 0 + +/** WCL_Core_1_World_Phase_REG register + * Core_0 world status register + */ +#define WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WCL_BASE + 0x558) +/** WCL_CORE_1_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1,1 means value. + */ +#define WCL_CORE_1_WORLD_PHASE (BIT(0)) +#define WCL_CORE_1_WORLD_PHASE_M (WCL_CORE_1_WORLD_PHASE_V << WCL_CORE_1_WORLD_PHASE_S) +#define WCL_CORE_1_WORLD_PHASE_V 0x00000001U +#define WCL_CORE_1_WORLD_PHASE_S 0 + +/** WCL_Core_1_NMI_MASK_ENABLE_REG register + * Core_1 NMI mask enable register + */ +#define WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WCL_BASE + 0x580) +/** WCL_CORE_1_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask, it can write any value, when write this + * register,the hardware start masking NMI interrupt + */ +#define WCL_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_ENABLE_M (WCL_CORE_1_NMI_MASK_ENABLE_V << WCL_CORE_1_NMI_MASK_ENABLE_S) +#define WCL_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_ENABLE_S 0 + +/** WCL_Core_1_NMI_MASK_TRIGGER_ADDR_REG register + * Core_1 NMI mask trigger addr register + */ +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x584) +/** WCL_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address + */ +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 + +/** WCL_Core_1_NMI_MASK_DISABLE_REG register + * Core_1 NMI mask disable register + */ +#define WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WCL_BASE + 0x588) +/** WCL_CORE_1_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask, it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ +#define WCL_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_DISABLE_M (WCL_CORE_1_NMI_MASK_DISABLE_V << WCL_CORE_1_NMI_MASK_DISABLE_S) +#define WCL_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_DISABLE_S 0 + +/** WCL_Core_1_NMI_MASK_CANCLE_REG register + * Core_1 NMI mask disable register + */ +#define WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WCL_BASE + 0x58c) +/** WCL_CORE_1_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ +#define WCL_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_CANCEL_M (WCL_CORE_1_NMI_MASK_CANCEL_V << WCL_CORE_1_NMI_MASK_CANCEL_S) +#define WCL_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_CANCEL_S 0 + +/** WCL_Core_1_NMI_MASK_REG register + * Core_1 NMI mask register + */ +#define WCL_CORE_1_NMI_MASK_REG (DR_REG_WCL_BASE + 0x590) +/** WCL_CORE_1_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ +#define WCL_CORE_1_NMI_MASK (BIT(0)) +#define WCL_CORE_1_NMI_MASK_M (WCL_CORE_1_NMI_MASK_V << WCL_CORE_1_NMI_MASK_S) +#define WCL_CORE_1_NMI_MASK_V 0x00000001U +#define WCL_CORE_1_NMI_MASK_S 0 + +/** WCL_Core_1_NMI_MASK_PHASE_REG register + * Core_1 NMI mask phase register + */ +#define WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WCL_BASE + 0x594) +/** WCL_CORE_1_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ +#define WCL_CORE_1_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_1_NMI_MASK_PHASE_M (WCL_CORE_1_NMI_MASK_PHASE_V << WCL_CORE_1_NMI_MASK_PHASE_S) +#define WCL_CORE_1_NMI_MASK_PHASE_V 0x00000001U +#define WCL_CORE_1_NMI_MASK_PHASE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_WORLD_CONTROLLER_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/world_controller_struct.h b/components/soc/esp32s3/include/soc/world_controller_struct.h index 0791caf4b8..80f6661b35 100644 --- a/components/soc/esp32s3/include/soc/world_controller_struct.h +++ b/components/soc/esp32s3/include/soc/world_controller_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,773 +10,1572 @@ extern "C" { #endif -typedef volatile struct world_controller_dev_s { - uint32_t wcl_core_0_entry_1_addr; - uint32_t wcl_core_0_entry_2_addr; - uint32_t wcl_core_0_entry_3_addr; - uint32_t wcl_core_0_entry_4_addr; - uint32_t wcl_core_0_entry_5_addr; - uint32_t wcl_core_0_entry_6_addr; - uint32_t wcl_core_0_entry_7_addr; - uint32_t wcl_core_0_entry_8_addr; - uint32_t wcl_core_0_entry_9_addr; - uint32_t wcl_core_0_entry_10_addr; - uint32_t wcl_core_0_entry_11_addr; - uint32_t wcl_core_0_entry_12_addr; - uint32_t wcl_core_0_entry_13_addr; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_0_entry_check : 13; /*This filed is used to enable entry address check */ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } wcl_core_0_entry_check; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t wcl_core_0_message_addr; - union { - struct { - uint32_t reg_core_0_message_max : 4; /*This filed is used to set the max value of clear write_buffer*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wcl_core_0_message_max; - union { - struct { - uint32_t reg_core_0_from_world_1 : 1; /*This bit is used to confirm world before enter entry 1 */ - uint32_t reg_core_0_from_entry_1 : 4; /*This filed is used to confirm in which entry before enter entry 1*/ - uint32_t reg_core_0_current_1 : 1; /*This bit is used to confirm whether the current state is in entry 1 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable1; - union { - struct { - uint32_t reg_core_0_from_world_2 : 1; /*This bit is used to confirm world before enter entry 2 */ - uint32_t reg_core_0_from_entry_2 : 4; /*This filed is used to confirm in which entry before enter entry 2*/ - uint32_t reg_core_0_current_2 : 1; /*This bit is used to confirm whether the current state is in entry 2 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable2; - union { - struct { - uint32_t reg_core_0_from_world_3 : 1; /*This bit is used to confirm world before enter entry 3 */ - uint32_t reg_core_0_from_entry_3 : 4; /*This filed is used to confirm in which entry before enter entry 3*/ - uint32_t reg_core_0_current_3 : 1; /*This bit is used to confirm whether the current state is in entry 3 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable3; - union { - struct { - uint32_t reg_core_0_from_world_4 : 1; /*This bit is used to confirm world before enter entry 4 */ - uint32_t reg_core_0_from_entry_4 : 4; /*This filed is used to confirm in which entry before enter entry 4*/ - uint32_t reg_core_0_current_4 : 1; /*This bit is used to confirm whether the current state is in entry 4 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable4; - union { - struct { - uint32_t reg_core_0_from_world_5 : 1; /*This bit is used to confirm world before enter entry 5 */ - uint32_t reg_core_0_from_entry_5 : 4; /*This filed is used to confirm in which entry before enter entry 5*/ - uint32_t reg_core_0_current_5 : 1; /*This bit is used to confirm whether the current state is in entry 5 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable5; - union { - struct { - uint32_t reg_core_0_from_world_6 : 1; /*This bit is used to confirm world before enter entry 6 */ - uint32_t reg_core_0_from_entry_6 : 4; /*This filed is used to confirm in which entry before enter entry 6*/ - uint32_t reg_core_0_current_6 : 1; /*This bit is used to confirm whether the current state is in entry 6 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable6; - union { - struct { - uint32_t reg_core_0_from_world_7 : 1; /*This bit is used to confirm world before enter entry 7 */ - uint32_t reg_core_0_from_entry_7 : 4; /*This filed is used to confirm in which entry before enter entry 7*/ - uint32_t reg_core_0_current_7 : 1; /*This bit is used to confirm whether the current state is in entry 7 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable7; - union { - struct { - uint32_t reg_core_0_from_world_8 : 1; /*This bit is used to confirm world before enter entry 8 */ - uint32_t reg_core_0_from_entry_8 : 4; /*This filed is used to confirm in which entry before enter entry 8*/ - uint32_t reg_core_0_current_8 : 1; /*This bit is used to confirm whether the current state is in entry 8 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable8; - union { - struct { - uint32_t reg_core_0_from_world_9 : 1; /*This bit is used to confirm world before enter entry 9 */ - uint32_t reg_core_0_from_entry_9 : 4; /*This filed is used to confirm in which entry before enter entry 9*/ - uint32_t reg_core_0_current_9 : 1; /*This bit is used to confirm whether the current state is in entry 9 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable9; - union { - struct { - uint32_t reg_core_0_from_world_10 : 1; /*This bit is used to confirm world before enter entry 10 */ - uint32_t reg_core_0_from_entry_10 : 4; /*This filed is used to confirm in which entry before enter entry 10*/ - uint32_t reg_core_0_current_10 : 1; /*This bit is used to confirm whether the current state is in entry 10 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable10; - union { - struct { - uint32_t reg_core_0_from_world_11 : 1; /*This bit is used to confirm world before enter entry 11 */ - uint32_t reg_core_0_from_entry_11 : 4; /*This filed is used to confirm in which entry before enter entry 11*/ - uint32_t reg_core_0_current_11 : 1; /*This bit is used to confirm whether the current state is in entry 11 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable11; - union { - struct { - uint32_t core_0_from_world_12 : 1; /*This bit is used to confirm world before enter entry 12 */ - uint32_t core_0_from_entry_12 : 4; /*This filed is used to confirm in which entry before enter entry 12*/ - uint32_t core_0_current_12 : 1; /*This bit is used to confirm whether the current state is in entry 12 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable12; - union { - struct { - uint32_t reg_core_0_from_world_13 : 1; /*This bit is used to confirm world before enter entry 13 */ - uint32_t reg_core_0_from_entry_13 : 4; /*This filed is used to confirm in which entry before enter entry 13*/ - uint32_t reg_core_0_current_13 : 1; /*This bit is used to confirm whether the current state is in entry 13 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable13; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_0_statustable_current: 13; /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } wcl_core_0_statustable_current; - uint32_t reserved_100; - uint32_t reserved_104; - union { - struct { - uint32_t reg_core_0_message_match : 1; /*This bit indicates whether the check is successful*/ - uint32_t reg_core_0_message_expect : 4; /*This field indicates the data to be written next time*/ - uint32_t reg_core_0_message_dataphase : 1; /*If this bit is 1*/ - uint32_t reg_core_0_message_addressphase: 1; /*If this bit is 1*/ - uint32_t reserved7 : 25; - }; - uint32_t val; - } wcl_core_0_message_phase; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t wcl_core_0_world_trigger_addr; - union { - struct { - uint32_t reg_core_0_world_prepare : 2; /*This field to used to set world to enter*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_prepare; - uint32_t wcl_core_0_world_update; - uint32_t wcl_core_0_world_cancel; - union { - struct { - uint32_t reg_core_0_world_iram0 : 2; /*this field is used to read current world of Iram0 bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_iram0; - union { - struct { - uint32_t reg_core_0_world_dram0_pif : 2; /*this field is used to read current world of Dram0 bus and PIF bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_dram0_pif; - union { - struct { - uint32_t reg_core_0_world_phase : 1; /*This bit indicates whether is preparing to switch to WORLD1*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_world_phase; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t wcl_core_0_nmi_mask_enable; - uint32_t wcl_core_0_nmi_mask_trigger_addr; - uint32_t wcl_core_0_nmi_mask_disable; - uint32_t wcl_core_0_nmi_mask_cancle; - union { - struct { - uint32_t reg_core_0_nmi_mask : 1; /*this bit is used to mask NMI interrupt*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_nmi_mask; - union { - struct { - uint32_t reg_core_0_nmi_mask_phase : 1; /*this bit is used to indicates whether the NMI interrupt is being masked*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_nmi_mask_phase; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t wcl_core_1_entry_1_addr; - uint32_t wcl_core_1_entry_2_addr; - uint32_t wcl_core_1_entry_3_addr; - uint32_t wcl_core_1_entry_4_addr; - uint32_t wcl_core_1_entry_5_addr; - uint32_t wcl_core_1_entry_6_addr; - uint32_t wcl_core_1_entry_7_addr; - uint32_t wcl_core_1_entry_8_addr; - uint32_t wcl_core_1_entry_9_addr; - uint32_t wcl_core_1_entry_10_addr; - uint32_t wcl_core_1_entry_11_addr; - uint32_t wcl_core_1_entry_12_addr; - uint32_t wcl_core_1_entry_13_addr; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_1_entry_check : 13; /*This filed is used to enable entry address check */ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } wcl_core_1_entry_check; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t wcl_core_1_message_addr; - union { - struct { - uint32_t reg_core_1_message_max : 4; /*This filed is used to set the max value of clear write_buffer*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wcl_core_1_message_max; - union { - struct { - uint32_t reg_core_1_from_world_1 : 1; /*This bit is used to confirm world before enter entry 1 */ - uint32_t reg_core_1_from_entry_1 : 4; /*This filed is used to confirm in which entry before enter entry 1*/ - uint32_t reg_core_1_current_1 : 1; /*This bit is used to confirm whether the current state is in entry 1 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable1; - union { - struct { - uint32_t reg_core_1_from_world_2 : 1; /*This bit is used to confirm world before enter entry 2 */ - uint32_t reg_core_1_from_entry_2 : 4; /*This filed is used to confirm in which entry before enter entry 2*/ - uint32_t reg_core_1_current_2 : 1; /*This bit is used to confirm whether the current state is in entry 2 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable2; - union { - struct { - uint32_t reg_core_1_from_world_3 : 1; /*This bit is used to confirm world before enter entry 3 */ - uint32_t reg_core_1_from_entry_3 : 4; /*This filed is used to confirm in which entry before enter entry 3*/ - uint32_t reg_core_1_current_3 : 1; /*This bit is used to confirm whether the current state is in entry 3 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable3; - union { - struct { - uint32_t reg_core_1_from_world_4 : 1; /*This bit is used to confirm world before enter entry 4 */ - uint32_t reg_core_1_from_entry_4 : 4; /*This filed is used to confirm in which entry before enter entry 4*/ - uint32_t reg_core_1_current_4 : 1; /*This bit is used to confirm whether the current state is in entry 4 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable4; - union { - struct { - uint32_t reg_core_1_from_world_5 : 1; /*This bit is used to confirm world before enter entry 5 */ - uint32_t reg_core_1_from_entry_5 : 4; /*This filed is used to confirm in which entry before enter entry 5*/ - uint32_t reg_core_1_current_5 : 1; /*This bit is used to confirm whether the current state is in entry 5 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable5; - union { - struct { - uint32_t reg_core_1_from_world_6 : 1; /*This bit is used to confirm world before enter entry 6 */ - uint32_t reg_core_1_from_entry_6 : 4; /*This filed is used to confirm in which entry before enter entry 6*/ - uint32_t reg_core_1_current_6 : 1; /*This bit is used to confirm whether the current state is in entry 6 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable6; - union { - struct { - uint32_t reg_core_1_from_world_7 : 1; /*This bit is used to confirm world before enter entry 7 */ - uint32_t reg_core_1_from_entry_7 : 4; /*This filed is used to confirm in which entry before enter entry 7*/ - uint32_t reg_core_1_current_7 : 1; /*This bit is used to confirm whether the current state is in entry 7 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable7; - union { - struct { - uint32_t reg_core_1_from_world_8 : 1; /*This bit is used to confirm world before enter entry 8 */ - uint32_t reg_core_1_from_entry_8 : 4; /*This filed is used to confirm in which entry before enter entry 8*/ - uint32_t reg_core_1_current_8 : 1; /*This bit is used to confirm whether the current state is in entry 8 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable8; - union { - struct { - uint32_t reg_core_1_from_world_9 : 1; /*This bit is used to confirm world before enter entry 9 */ - uint32_t reg_core_1_from_entry_9 : 4; /*This filed is used to confirm in which entry before enter entry 9*/ - uint32_t reg_core_1_current_9 : 1; /*This bit is used to confirm whether the current state is in entry 9 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable9; - union { - struct { - uint32_t reg_core_1_from_world_10 : 1; /*This bit is used to confirm world before enter entry 10 */ - uint32_t reg_core_1_from_entry_10 : 4; /*This filed is used to confirm in which entry before enter entry 10*/ - uint32_t reg_core_1_current_10 : 1; /*This bit is used to confirm whether the current state is in entry 10 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable10; - union { - struct { - uint32_t reg_core_1_from_world_11 : 1; /*This bit is used to confirm world before enter entry 11 */ - uint32_t reg_core_1_from_entry_11 : 4; /*This filed is used to confirm in which entry before enter entry 11*/ - uint32_t reg_core_1_current_11 : 1; /*This bit is used to confirm whether the current state is in entry 11 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable11; - union { - struct { - uint32_t core_1_from_world_12 : 1; /*This bit is used to confirm world before enter entry 12 */ - uint32_t core_1_from_entry_12 : 4; /*This filed is used to confirm in which entry before enter entry 12*/ - uint32_t core_1_current_12 : 1; /*This bit is used to confirm whether the current state is in entry 12 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable12; - union { - struct { - uint32_t reg_core_1_from_world_13 : 1; /*This bit is used to confirm world before enter entry 13 */ - uint32_t reg_core_1_from_entry_13 : 4; /*This filed is used to confirm in which entry before enter entry 13*/ - uint32_t reg_core_1_current_13 : 1; /*This bit is used to confirm whether the current state is in entry 13 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable13; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_1_statustable_current: 13; /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } wcl_core_1_statustable_current; - uint32_t reserved_500; - uint32_t reserved_504; - union { - struct { - uint32_t reg_core_1_message_match : 1; /*This bit indicates whether the check is successful*/ - uint32_t reg_core_1_message_expect : 4; /*This field indicates the data to be written next time*/ - uint32_t reg_core_1_message_dataphase : 1; /*If this bit is 1*/ - uint32_t reg_core_1_message_addressphase: 1; /*If this bit is 1*/ - uint32_t reserved7 : 25; - }; - uint32_t val; - } wcl_core_1_message_phase; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t wcl_core_1_world_trigger_addr; - union { - struct { - uint32_t reg_core_1_world_prepare : 2; /*This field to used to set world to enter*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_prepare; - uint32_t wcl_core_1_world_update; - uint32_t wcl_core_1_world_cancel; - union { - struct { - uint32_t reg_core_1_world_iram0 : 2; /*this field is used to read current world of Iram0 bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_iram0; - union { - struct { - uint32_t reg_core_1_world_dram0_pif : 2; /*this field is used to read current world of Dram0 bus and PIF bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_dram0_pif; - union { - struct { - uint32_t reg_core_1_world_phase : 1; /*This bit indicates whether is preparing to switch to WORLD1*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_world_phase; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t wcl_core_1_nmi_mask_enable; - uint32_t wcl_core_1_nmi_mask_trigger_addr; - uint32_t wcl_core_1_nmi_mask_disable; - uint32_t wcl_core_1_nmi_mask_cancle; - union { - struct { - uint32_t reg_core_1_nmi_mask : 1; /*this bit is used to mask NMI interrupt*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_nmi_mask; - union { - struct { - uint32_t reg_core_1_nmi_mask_phase : 1; /*this bit is used to indicates whether the NMI interrupt is being masked*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_nmi_mask_phase; -} world_controller_dev_t; -extern world_controller_dev_t WORLD_CONTROLLER; +/** Group: WORLD1 to WORLD0 configuration Registers */ +/** Type of core_0_entry_1_addr register + * Core_0 Entry 1 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_1_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 1 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_1_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_1_addr_reg_t; + +/** Type of core_0_entry_2_addr register + * Core_0 Entry 2 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_2_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 2 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_2_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_2_addr_reg_t; + +/** Type of core_0_entry_3_addr register + * Core_0 Entry 3 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_3_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 3 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_3_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_3_addr_reg_t; + +/** Type of core_0_entry_4_addr register + * Core_0 Entry 4 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_4_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 4 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_4_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_4_addr_reg_t; + +/** Type of core_0_entry_5_addr register + * Core_0 Entry 5 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_5_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 5 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_5_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_5_addr_reg_t; + +/** Type of core_0_entry_6_addr register + * Core_0 Entry 6 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_6_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 6 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_6_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_6_addr_reg_t; + +/** Type of core_0_entry_7_addr register + * Core_0 Entry 7 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_7_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 7 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_7_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_7_addr_reg_t; + +/** Type of core_0_entry_8_addr register + * Core_0 Entry 8 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_8_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 8 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_8_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_8_addr_reg_t; + +/** Type of core_0_entry_9_addr register + * Core_0 Entry 9 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_9_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 9 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_9_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_9_addr_reg_t; + +/** Type of core_0_entry_10_addr register + * Core_0 Entry 10 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_10_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 10 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_10_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_10_addr_reg_t; + +/** Type of core_0_entry_11_addr register + * Core_0 Entry 11 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_11_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 11 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_11_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_11_addr_reg_t; + +/** Type of core_0_entry_12_addr register + * Core_0 Entry 12 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_12_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 12 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_12_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_12_addr_reg_t; + +/** Type of core_0_entry_13_addr register + * Core_0 Entry 13 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_13_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 13 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_13_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_13_addr_reg_t; + +/** Type of core_0_entry_check register + * Core_0 Entry check configuration Register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_0_entry_check : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + uint32_t core_0_entry_check:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_0_entry_check_reg_t; + +/** Type of core_0_message_addr register + * Clear writer_buffer write address configuration register + */ +typedef union { + struct { + /** core_0_message_addr : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + uint32_t core_0_message_addr:32; + }; + uint32_t val; +} wcl_core_0_message_addr_reg_t; + +/** Type of core_0_message_max register + * Clear writer_buffer write number configuration register + */ +typedef union { + struct { + /** core_0_message_max : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + uint32_t core_0_message_max:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} wcl_core_0_message_max_reg_t; + +/** Type of core_0_message_phase register + * Clear writer_buffer status register + */ +typedef union { + struct { + /** core_0_message_match : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + uint32_t core_0_message_match:1; + /** core_0_message_expect : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + uint32_t core_0_message_expect:4; + /** core_0_message_dataphase : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking data + */ + uint32_t core_0_message_dataphase:1; + /** core_0_message_addressphase : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking address. + */ + uint32_t core_0_message_addressphase:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} wcl_core_0_message_phase_reg_t; + +/** Type of core_1_entry_1_addr register + * Core_1 Entry 1 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_1_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 1 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_1_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_1_addr_reg_t; + +/** Type of core_1_entry_2_addr register + * Core_1 Entry 2 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_2_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 2 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_2_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_2_addr_reg_t; + +/** Type of core_1_entry_3_addr register + * Core_1 Entry 3 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_3_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 3 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_3_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_3_addr_reg_t; + +/** Type of core_1_entry_4_addr register + * Core_1 Entry 4 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_4_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 4 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_4_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_4_addr_reg_t; + +/** Type of core_1_entry_5_addr register + * Core_1 Entry 5 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_5_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 5 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_5_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_5_addr_reg_t; + +/** Type of core_1_entry_6_addr register + * Core_1 Entry 6 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_6_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 6 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_6_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_6_addr_reg_t; + +/** Type of core_1_entry_7_addr register + * Core_1 Entry 7 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_7_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 7 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_7_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_7_addr_reg_t; + +/** Type of core_1_entry_8_addr register + * Core_1 Entry 8 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_8_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 8 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_8_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_8_addr_reg_t; + +/** Type of core_1_entry_9_addr register + * Core_1 Entry 9 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_9_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 9 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_9_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_9_addr_reg_t; + +/** Type of core_1_entry_10_addr register + * Core_1 Entry 10 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_10_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 10 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_10_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_10_addr_reg_t; + +/** Type of core_1_entry_11_addr register + * Core_1 Entry 11 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_11_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 11 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_11_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_11_addr_reg_t; + +/** Type of core_1_entry_12_addr register + * Core_1 Entry 12 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_12_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 12 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_12_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_12_addr_reg_t; + +/** Type of core_1_entry_13_addr register + * Core_1 Entry 13 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_13_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 13 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_13_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_13_addr_reg_t; + +/** Type of core_1_entry_check register + * Core_1 Entry check configuration Register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_1_entry_check : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + uint32_t core_1_entry_check:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_1_entry_check_reg_t; + +/** Type of core_1_message_addr register + * Clear writer_buffer write address configuration register + */ +typedef union { + struct { + /** core_1_message_addr : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + uint32_t core_1_message_addr:32; + }; + uint32_t val; +} wcl_core_1_message_addr_reg_t; + +/** Type of core_1_message_max register + * Clear writer_buffer write number configuration register + */ +typedef union { + struct { + /** core_1_message_max : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + uint32_t core_1_message_max:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} wcl_core_1_message_max_reg_t; + +/** Type of core_1_message_phase register + * Clear writer_buffer status register + */ +typedef union { + struct { + /** core_1_message_match : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + uint32_t core_1_message_match:1; + /** core_1_message_expect : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + uint32_t core_1_message_expect:4; + /** core_1_message_dataphase : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking data + */ + uint32_t core_1_message_dataphase:1; + /** core_1_message_addressphase : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking address. + */ + uint32_t core_1_message_addressphase:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} wcl_core_1_message_phase_reg_t; + + +/** Group: StatusTable Registers */ +/** Type of core_0_statustable1 register + * Status register of world switch of entry 1 + */ +typedef union { + struct { + /** core_0_from_world_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + uint32_t core_0_from_world_1:1; + /** core_0_from_entry_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + uint32_t core_0_from_entry_1:4; + /** core_0_current_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + uint32_t core_0_current_1:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable1_reg_t; + +/** Type of core_0_statustable2 register + * Status register of world switch of entry 2 + */ +typedef union { + struct { + /** core_0_from_world_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + uint32_t core_0_from_world_2:1; + /** core_0_from_entry_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + uint32_t core_0_from_entry_2:4; + /** core_0_current_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + uint32_t core_0_current_2:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable2_reg_t; + +/** Type of core_0_statustable3 register + * Status register of world switch of entry 3 + */ +typedef union { + struct { + /** core_0_from_world_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + uint32_t core_0_from_world_3:1; + /** core_0_from_entry_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + uint32_t core_0_from_entry_3:4; + /** core_0_current_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + uint32_t core_0_current_3:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable3_reg_t; + +/** Type of core_0_statustable4 register + * Status register of world switch of entry 4 + */ +typedef union { + struct { + /** core_0_from_world_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + uint32_t core_0_from_world_4:1; + /** core_0_from_entry_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + uint32_t core_0_from_entry_4:4; + /** core_0_current_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + uint32_t core_0_current_4:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable4_reg_t; + +/** Type of core_0_statustable5 register + * Status register of world switch of entry 5 + */ +typedef union { + struct { + /** core_0_from_world_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + uint32_t core_0_from_world_5:1; + /** core_0_from_entry_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + uint32_t core_0_from_entry_5:4; + /** core_0_current_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + uint32_t core_0_current_5:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable5_reg_t; + +/** Type of core_0_statustable6 register + * Status register of world switch of entry 6 + */ +typedef union { + struct { + /** core_0_from_world_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + uint32_t core_0_from_world_6:1; + /** core_0_from_entry_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + uint32_t core_0_from_entry_6:4; + /** core_0_current_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + uint32_t core_0_current_6:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable6_reg_t; + +/** Type of core_0_statustable7 register + * Status register of world switch of entry 7 + */ +typedef union { + struct { + /** core_0_from_world_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + uint32_t core_0_from_world_7:1; + /** core_0_from_entry_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + uint32_t core_0_from_entry_7:4; + /** core_0_current_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + uint32_t core_0_current_7:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable7_reg_t; + +/** Type of core_0_statustable8 register + * Status register of world switch of entry 8 + */ +typedef union { + struct { + /** core_0_from_world_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + uint32_t core_0_from_world_8:1; + /** core_0_from_entry_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + uint32_t core_0_from_entry_8:4; + /** core_0_current_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + uint32_t core_0_current_8:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable8_reg_t; + +/** Type of core_0_statustable9 register + * Status register of world switch of entry 9 + */ +typedef union { + struct { + /** core_0_from_world_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + uint32_t core_0_from_world_9:1; + /** core_0_from_entry_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + uint32_t core_0_from_entry_9:4; + /** core_0_current_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + uint32_t core_0_current_9:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable9_reg_t; + +/** Type of core_0_statustable10 register + * Status register of world switch of entry 10 + */ +typedef union { + struct { + /** core_0_from_world_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + uint32_t core_0_from_world_10:1; + /** core_0_from_entry_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + uint32_t core_0_from_entry_10:4; + /** core_0_current_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + uint32_t core_0_current_10:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable10_reg_t; + +/** Type of core_0_statustable11 register + * Status register of world switch of entry 11 + */ +typedef union { + struct { + /** core_0_from_world_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + uint32_t core_0_from_world_11:1; + /** core_0_from_entry_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + uint32_t core_0_from_entry_11:4; + /** core_0_current_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + uint32_t core_0_current_11:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable11_reg_t; + +/** Type of core_0_statustable12 register + * Status register of world switch of entry 12 + */ +typedef union { + struct { + /** core_0_from_world_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + uint32_t core_0_from_world_12:1; + /** core_0_from_entry_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + uint32_t core_0_from_entry_12:4; + /** core_0_current_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + uint32_t core_0_current_12:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable12_reg_t; + +/** Type of core_0_statustable13 register + * Status register of world switch of entry 13 + */ +typedef union { + struct { + /** core_0_from_world_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + uint32_t core_0_from_world_13:1; + /** core_0_from_entry_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + uint32_t core_0_from_entry_13:4; + /** core_0_current_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + uint32_t core_0_current_13:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable13_reg_t; + +/** Type of core_0_statustable_current register + * Status register of statustable current + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_0_statustable_current : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 + * represents the current field of STATUSTABLE2 + */ + uint32_t core_0_statustable_current:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_0_statustable_current_reg_t; + +/** Type of core_1_statustable1 register + * Status register of world switch of entry 1 + */ +typedef union { + struct { + /** core_1_from_world_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + uint32_t core_1_from_world_1:1; + /** core_1_from_entry_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + uint32_t core_1_from_entry_1:4; + /** core_1_current_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + uint32_t core_1_current_1:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable1_reg_t; + +/** Type of core_1_statustable2 register + * Status register of world switch of entry 2 + */ +typedef union { + struct { + /** core_1_from_world_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + uint32_t core_1_from_world_2:1; + /** core_1_from_entry_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + uint32_t core_1_from_entry_2:4; + /** core_1_current_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + uint32_t core_1_current_2:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable2_reg_t; + +/** Type of core_1_statustable3 register + * Status register of world switch of entry 3 + */ +typedef union { + struct { + /** core_1_from_world_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + uint32_t core_1_from_world_3:1; + /** core_1_from_entry_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + uint32_t core_1_from_entry_3:4; + /** core_1_current_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + uint32_t core_1_current_3:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable3_reg_t; + +/** Type of core_1_statustable4 register + * Status register of world switch of entry 4 + */ +typedef union { + struct { + /** core_1_from_world_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + uint32_t core_1_from_world_4:1; + /** core_1_from_entry_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + uint32_t core_1_from_entry_4:4; + /** core_1_current_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + uint32_t core_1_current_4:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable4_reg_t; + +/** Type of core_1_statustable5 register + * Status register of world switch of entry 5 + */ +typedef union { + struct { + /** core_1_from_world_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + uint32_t core_1_from_world_5:1; + /** core_1_from_entry_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + uint32_t core_1_from_entry_5:4; + /** core_1_current_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + uint32_t core_1_current_5:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable5_reg_t; + +/** Type of core_1_statustable6 register + * Status register of world switch of entry 6 + */ +typedef union { + struct { + /** core_1_from_world_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + uint32_t core_1_from_world_6:1; + /** core_1_from_entry_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + uint32_t core_1_from_entry_6:4; + /** core_1_current_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + uint32_t core_1_current_6:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable6_reg_t; + +/** Type of core_1_statustable7 register + * Status register of world switch of entry 7 + */ +typedef union { + struct { + /** core_1_from_world_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + uint32_t core_1_from_world_7:1; + /** core_1_from_entry_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + uint32_t core_1_from_entry_7:4; + /** core_1_current_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + uint32_t core_1_current_7:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable7_reg_t; + +/** Type of core_1_statustable8 register + * Status register of world switch of entry 8 + */ +typedef union { + struct { + /** core_1_from_world_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + uint32_t core_1_from_world_8:1; + /** core_1_from_entry_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + uint32_t core_1_from_entry_8:4; + /** core_1_current_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + uint32_t core_1_current_8:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable8_reg_t; + +/** Type of core_1_statustable9 register + * Status register of world switch of entry 9 + */ +typedef union { + struct { + /** core_1_from_world_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + uint32_t core_1_from_world_9:1; + /** core_1_from_entry_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + uint32_t core_1_from_entry_9:4; + /** core_1_current_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + uint32_t core_1_current_9:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable9_reg_t; + +/** Type of core_1_statustable10 register + * Status register of world switch of entry 10 + */ +typedef union { + struct { + /** core_1_from_world_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + uint32_t core_1_from_world_10:1; + /** core_1_from_entry_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + uint32_t core_1_from_entry_10:4; + /** core_1_current_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + uint32_t core_1_current_10:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable10_reg_t; + +/** Type of core_1_statustable11 register + * Status register of world switch of entry 11 + */ +typedef union { + struct { + /** core_1_from_world_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + uint32_t core_1_from_world_11:1; + /** core_1_from_entry_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + uint32_t core_1_from_entry_11:4; + /** core_1_current_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + uint32_t core_1_current_11:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable11_reg_t; + +/** Type of core_1_statustable12 register + * Status register of world switch of entry 12 + */ +typedef union { + struct { + /** core_1_from_world_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + uint32_t core_1_from_world_12:1; + /** core_1_from_entry_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + uint32_t core_1_from_entry_12:4; + /** core_1_current_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + uint32_t core_1_current_12:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable12_reg_t; + +/** Type of core_1_statustable13 register + * Status register of world switch of entry 13 + */ +typedef union { + struct { + /** core_1_from_world_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + uint32_t core_1_from_world_13:1; + /** core_1_from_entry_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + uint32_t core_1_from_entry_13:4; + /** core_1_current_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + uint32_t core_1_current_13:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable13_reg_t; + +/** Type of core_1_statustable_current register + * Status register of statustable current + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_1_statustable_current : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1 + */ + uint32_t core_1_statustable_current:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_1_statustable_current_reg_t; + + +/** Group: WORLD0 to WORLD1 configuration Registers */ +/** Type of core_0_world_trigger_addr register + * Core_0 trigger address configuration Register + */ +typedef union { + struct { + /** core_0_world_trigger_addr : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ + uint32_t core_0_world_trigger_addr:32; + }; + uint32_t val; +} wcl_core_0_world_trigger_addr_reg_t; + +/** Type of core_0_world_prepare register + * Core_0 prepare world configuration Register + */ +typedef union { + struct { + /** core_0_world_prepare : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + */ + uint32_t core_0_world_prepare:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_prepare_reg_t; + +/** Type of core_0_world_update register + * Core_0 configuration update register + */ +typedef union { + struct { + /** core_0_update : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ + uint32_t core_0_update:32; + }; + uint32_t val; +} wcl_core_0_world_update_reg_t; + +/** Type of core_0_world_cancel register + * Core_0 configuration cancel register + */ +typedef union { + struct { + /** core_0_world_cancel : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,use this register to cancel world switch, jujst need + * write any value,the hardware only checks the write operation of this register and + * does not case about its value + */ + uint32_t core_0_world_cancel:32; + }; + uint32_t val; +} wcl_core_0_world_cancel_reg_t; + +/** Type of core_0_world_iram0 register + * Core_0 Iram0 world register + */ +typedef union { + struct { + /** core_0_world_iram0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + uint32_t core_0_world_iram0:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_iram0_reg_t; + +/** Type of core_0_world_dram0_pif register + * Core_0 dram0 and PIF world register + */ +typedef union { + struct { + /** core_0_world_dram0_pif : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + uint32_t core_0_world_dram0_pif:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_dram0_pif_reg_t; + +/** Type of core_0_world_phase register + * Core_0 world status register + */ +typedef union { + struct { + /** core_0_world_phase : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1, 1 means value. + */ + uint32_t core_0_world_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_world_phase_reg_t; + +/** Type of core_1_world_trigger_addr register + * Core_1 trigger address configuration Register + */ +typedef union { + struct { + /** core_1_world_trigger_addr : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ + uint32_t core_1_world_trigger_addr:32; + }; + uint32_t val; +} wcl_core_1_world_trigger_addr_reg_t; + +/** Type of core_1_world_prepare register + * Core_1 prepare world configuration Register + */ +typedef union { + struct { + /** core_1_world_prepare : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + */ + uint32_t core_1_world_prepare:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_prepare_reg_t; + +/** Type of core_1_world_update register + * Core_1 configuration update register + */ +typedef union { + struct { + /** core_1_update : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ + uint32_t core_1_update:32; + }; + uint32_t val; +} wcl_core_1_world_update_reg_t; + +/** Type of core_1_world_cancel register + * Core_1 configuration cancel register + */ +typedef union { + struct { + /** core_1_world_cancel : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,can use this register to cancel world switch. can + * write any value, the hardware only checks the write operation of this register and + * does not case about its value + */ + uint32_t core_1_world_cancel:32; + }; + uint32_t val; +} wcl_core_1_world_cancel_reg_t; + +/** Type of core_1_world_iram0 register + * Core_1 Iram0 world register + */ +typedef union { + struct { + /** core_1_world_iram0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + uint32_t core_1_world_iram0:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_iram0_reg_t; + +/** Type of core_1_world_dram0_pif register + * Core_1 dram0 and PIF world register + */ +typedef union { + struct { + /** core_1_world_dram0_pif : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + uint32_t core_1_world_dram0_pif:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_dram0_pif_reg_t; + +/** Type of core_1_world_phase register + * Core_0 world status register + */ +typedef union { + struct { + /** core_1_world_phase : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1,1 means value. + */ + uint32_t core_1_world_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_world_phase_reg_t; + + +/** Group: NMI mask configuration Registers */ +/** Type of core_0_nmi_mask_enable register + * Core_0 NMI mask enable register + */ +typedef union { + struct { + /** core_0_nmi_mask_enable : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask,it can write any value,when write this + * register,the hardware start masking NMI interrupt + */ + uint32_t core_0_nmi_mask_enable:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_enable_reg_t; + +/** Type of core_0_nmi_mask_trigger_addr register + * Core_0 NMI mask trigger address register + */ +typedef union { + struct { + /** core_0_nmi_mask_trigger_addr : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address, when CPU executes to this address,NMI + * mask automatically fails + */ + uint32_t core_0_nmi_mask_trigger_addr:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_trigger_addr_reg_t; + +/** Type of core_0_nmi_mask_disable register + * Core_0 NMI mask disable register + */ +typedef union { + struct { + /** core_0_nmi_mask_disable : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask,it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ + uint32_t core_0_nmi_mask_disable:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_disable_reg_t; + +/** Type of core_0_nmi_mask_cancle register + * Core_0 NMI mask disable register + */ +typedef union { + struct { + /** core_0_nmi_mask_cancel : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + uint32_t core_0_nmi_mask_cancel:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_cancle_reg_t; + +/** Type of core_0_nmi_mask register + * Core_0 NMI mask register + */ +typedef union { + struct { + /** core_0_nmi_mask : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + uint32_t core_0_nmi_mask:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_nmi_mask_reg_t; + +/** Type of core_0_nmi_mask_phase register + * Core_0 NMI mask phase register + */ +typedef union { + struct { + /** core_0_nmi_mask_phase : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ + uint32_t core_0_nmi_mask_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_nmi_mask_phase_reg_t; + +/** Type of core_1_nmi_mask_enable register + * Core_1 NMI mask enable register + */ +typedef union { + struct { + /** core_1_nmi_mask_enable : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask, it can write any value, when write this + * register,the hardware start masking NMI interrupt + */ + uint32_t core_1_nmi_mask_enable:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_enable_reg_t; + +/** Type of core_1_nmi_mask_trigger_addr register + * Core_1 NMI mask trigger addr register + */ +typedef union { + struct { + /** core_1_nmi_mask_trigger_addr : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address + */ + uint32_t core_1_nmi_mask_trigger_addr:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_trigger_addr_reg_t; + +/** Type of core_1_nmi_mask_disable register + * Core_1 NMI mask disable register + */ +typedef union { + struct { + /** core_1_nmi_mask_disable : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask, it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ + uint32_t core_1_nmi_mask_disable:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_disable_reg_t; + +/** Type of core_1_nmi_mask_cancle register + * Core_1 NMI mask disable register + */ +typedef union { + struct { + /** core_1_nmi_mask_cancel : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + uint32_t core_1_nmi_mask_cancel:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_cancle_reg_t; + +/** Type of core_1_nmi_mask register + * Core_1 NMI mask register + */ +typedef union { + struct { + /** core_1_nmi_mask : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + uint32_t core_1_nmi_mask:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_nmi_mask_reg_t; + +/** Type of core_1_nmi_mask_phase register + * Core_1 NMI mask phase register + */ +typedef union { + struct { + /** core_1_nmi_mask_phase : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ + uint32_t core_1_nmi_mask_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_nmi_mask_phase_reg_t; + + +typedef struct { + volatile wcl_core_0_entry_1_addr_reg_t core_0_entry_1_addr; + volatile wcl_core_0_entry_2_addr_reg_t core_0_entry_2_addr; + volatile wcl_core_0_entry_3_addr_reg_t core_0_entry_3_addr; + volatile wcl_core_0_entry_4_addr_reg_t core_0_entry_4_addr; + volatile wcl_core_0_entry_5_addr_reg_t core_0_entry_5_addr; + volatile wcl_core_0_entry_6_addr_reg_t core_0_entry_6_addr; + volatile wcl_core_0_entry_7_addr_reg_t core_0_entry_7_addr; + volatile wcl_core_0_entry_8_addr_reg_t core_0_entry_8_addr; + volatile wcl_core_0_entry_9_addr_reg_t core_0_entry_9_addr; + volatile wcl_core_0_entry_10_addr_reg_t core_0_entry_10_addr; + volatile wcl_core_0_entry_11_addr_reg_t core_0_entry_11_addr; + volatile wcl_core_0_entry_12_addr_reg_t core_0_entry_12_addr; + volatile wcl_core_0_entry_13_addr_reg_t core_0_entry_13_addr; + uint32_t reserved_034[18]; + volatile wcl_core_0_entry_check_reg_t core_0_entry_check; + volatile wcl_core_0_statustable1_reg_t core_0_statustable1; + volatile wcl_core_0_statustable2_reg_t core_0_statustable2; + volatile wcl_core_0_statustable3_reg_t core_0_statustable3; + volatile wcl_core_0_statustable4_reg_t core_0_statustable4; + volatile wcl_core_0_statustable5_reg_t core_0_statustable5; + volatile wcl_core_0_statustable6_reg_t core_0_statustable6; + volatile wcl_core_0_statustable7_reg_t core_0_statustable7; + volatile wcl_core_0_statustable8_reg_t core_0_statustable8; + volatile wcl_core_0_statustable9_reg_t core_0_statustable9; + volatile wcl_core_0_statustable10_reg_t core_0_statustable10; + volatile wcl_core_0_statustable11_reg_t core_0_statustable11; + volatile wcl_core_0_statustable12_reg_t core_0_statustable12; + volatile wcl_core_0_statustable13_reg_t core_0_statustable13; + uint32_t reserved_0b4[18]; + volatile wcl_core_0_statustable_current_reg_t core_0_statustable_current; + volatile wcl_core_0_message_addr_reg_t core_0_message_addr; + volatile wcl_core_0_message_max_reg_t core_0_message_max; + volatile wcl_core_0_message_phase_reg_t core_0_message_phase; + uint32_t reserved_10c[13]; + volatile wcl_core_0_world_trigger_addr_reg_t core_0_world_trigger_addr; + volatile wcl_core_0_world_prepare_reg_t core_0_world_prepare; + volatile wcl_core_0_world_update_reg_t core_0_world_update; + volatile wcl_core_0_world_cancel_reg_t core_0_world_cancel; + volatile wcl_core_0_world_iram0_reg_t core_0_world_iram0; + volatile wcl_core_0_world_dram0_pif_reg_t core_0_world_dram0_pif; + volatile wcl_core_0_world_phase_reg_t core_0_world_phase; + uint32_t reserved_15c[9]; + volatile wcl_core_0_nmi_mask_enable_reg_t core_0_nmi_mask_enable; + volatile wcl_core_0_nmi_mask_trigger_addr_reg_t core_0_nmi_mask_trigger_addr; + volatile wcl_core_0_nmi_mask_disable_reg_t core_0_nmi_mask_disable; + volatile wcl_core_0_nmi_mask_cancle_reg_t core_0_nmi_mask_cancle; + volatile wcl_core_0_nmi_mask_reg_t core_0_nmi_mask; + volatile wcl_core_0_nmi_mask_phase_reg_t core_0_nmi_mask_phase; + uint32_t reserved_198[154]; + volatile wcl_core_1_entry_1_addr_reg_t core_1_entry_1_addr; + volatile wcl_core_1_entry_2_addr_reg_t core_1_entry_2_addr; + volatile wcl_core_1_entry_3_addr_reg_t core_1_entry_3_addr; + volatile wcl_core_1_entry_4_addr_reg_t core_1_entry_4_addr; + volatile wcl_core_1_entry_5_addr_reg_t core_1_entry_5_addr; + volatile wcl_core_1_entry_6_addr_reg_t core_1_entry_6_addr; + volatile wcl_core_1_entry_7_addr_reg_t core_1_entry_7_addr; + volatile wcl_core_1_entry_8_addr_reg_t core_1_entry_8_addr; + volatile wcl_core_1_entry_9_addr_reg_t core_1_entry_9_addr; + volatile wcl_core_1_entry_10_addr_reg_t core_1_entry_10_addr; + volatile wcl_core_1_entry_11_addr_reg_t core_1_entry_11_addr; + volatile wcl_core_1_entry_12_addr_reg_t core_1_entry_12_addr; + volatile wcl_core_1_entry_13_addr_reg_t core_1_entry_13_addr; + uint32_t reserved_434[18]; + volatile wcl_core_1_entry_check_reg_t core_1_entry_check; + volatile wcl_core_1_statustable1_reg_t core_1_statustable1; + volatile wcl_core_1_statustable2_reg_t core_1_statustable2; + volatile wcl_core_1_statustable3_reg_t core_1_statustable3; + volatile wcl_core_1_statustable4_reg_t core_1_statustable4; + volatile wcl_core_1_statustable5_reg_t core_1_statustable5; + volatile wcl_core_1_statustable6_reg_t core_1_statustable6; + volatile wcl_core_1_statustable7_reg_t core_1_statustable7; + volatile wcl_core_1_statustable8_reg_t core_1_statustable8; + volatile wcl_core_1_statustable9_reg_t core_1_statustable9; + volatile wcl_core_1_statustable10_reg_t core_1_statustable10; + volatile wcl_core_1_statustable11_reg_t core_1_statustable11; + volatile wcl_core_1_statustable12_reg_t core_1_statustable12; + volatile wcl_core_1_statustable13_reg_t core_1_statustable13; + uint32_t reserved_4b4[18]; + volatile wcl_core_1_statustable_current_reg_t core_1_statustable_current; + volatile wcl_core_1_message_addr_reg_t core_1_message_addr; + volatile wcl_core_1_message_max_reg_t core_1_message_max; + volatile wcl_core_1_message_phase_reg_t core_1_message_phase; + uint32_t reserved_50c[13]; + volatile wcl_core_1_world_trigger_addr_reg_t core_1_world_trigger_addr; + volatile wcl_core_1_world_prepare_reg_t core_1_world_prepare; + volatile wcl_core_1_world_update_reg_t core_1_world_update; + volatile wcl_core_1_world_cancel_reg_t core_1_world_cancel; + volatile wcl_core_1_world_iram0_reg_t core_1_world_iram0; + volatile wcl_core_1_world_dram0_pif_reg_t core_1_world_dram0_pif; + volatile wcl_core_1_world_phase_reg_t core_1_world_phase; + uint32_t reserved_55c[9]; + volatile wcl_core_1_nmi_mask_enable_reg_t core_1_nmi_mask_enable; + volatile wcl_core_1_nmi_mask_trigger_addr_reg_t core_1_nmi_mask_trigger_addr; + volatile wcl_core_1_nmi_mask_disable_reg_t core_1_nmi_mask_disable; + volatile wcl_core_1_nmi_mask_cancle_reg_t core_1_nmi_mask_cancle; + volatile wcl_core_1_nmi_mask_reg_t core_1_nmi_mask; + volatile wcl_core_1_nmi_mask_phase_reg_t core_1_nmi_mask_phase; +} wcl_dev_t; + +extern wcl_dev_t WORLD_CONTROLLER; + +#ifndef __cplusplus +_Static_assert(sizeof(wcl_dev_t) == 0x598, "Invalid size of wcl_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index de6ed0abcf..66ed5c0387 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -47,3 +47,4 @@ PROVIDE ( USB_SERIAL_JTAG = 0x60038000 ); PROVIDE ( USB0 = 0x60080000 ); PROVIDE ( USBH = 0x60080000 ); PROVIDE ( USB_WRAP = 0x60039000 ); +PROVIDE ( WORLD_CONTROLLER = 0x600D0000 ); diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index c841865242..6242daf0fb 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1253,7 +1253,7 @@ components/soc/esp32s3/include/soc/usb_wrap_reg.h components/soc/esp32s3/include/soc/usb_wrap_struct.h components/soc/esp32s3/include/soc/usbh_struct.h components/soc/esp32s3/include/soc/wdev_reg.h -components/soc/esp32s3/include/soc/world_controller_reg.h +components/soc/esp32s3/interrupts.c components/soc/esp32s3/ledc_periph.c components/soc/esp32s3/rtc_io_periph.c components/soc/esp32s3/sdio_slave_periph.c diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 065adf8f4d..290a41af41 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -145,8 +145,6 @@ components/esp_rom/include/esp32/rom/uart.h ### To be fixed: files which don't compile for esp32s3 target: -components/soc/esp32s3/include/soc/world_controller_struct.h - ### To be fixed: files which don't compile for esp32c3 target: