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Merge branch 'bugfix/soc_cpu_subsys_region_v5.2' into 'release/v5.2'

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fix(soc): change debug addr range to CPU subsystem range (v5.2)

See merge request espressif/esp-idf!28671
This commit is contained in:
Mahavir Jain 2024-02-16 13:47:49 +08:00
commit cc2db3d190
6 changed files with 34 additions and 29 deletions
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11
components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -26,8 +26,13 @@ static inline bool __is_valid_memory_region(intptr_t addr)
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) || (addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) ||
/* RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them */ /* RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them */
#endif #endif
(addr >= SOC_PERIPHERAL_LOW && addr < SOC_PERIPHERAL_HIGH) || #if defined(SOC_DEBUG_LOW) && defined(SOC_DEBUG_HIGH)
(addr >= SOC_DEBUG_LOW && addr < SOC_DEBUG_HIGH); (addr >= SOC_DEBUG_LOW && addr < SOC_DEBUG_HIGH) ||
#endif
#if defined(SOC_CPU_SUBSYSTEM_LOW) && defined(SOC_CPU_SUBSYSTEM_HIGH)
(addr >= SOC_CPU_SUBSYSTEM_LOW && addr < SOC_CPU_SUBSYSTEM_HIGH) ||
#endif
(addr >= SOC_PERIPHERAL_LOW && addr < SOC_PERIPHERAL_HIGH);
} }
static inline bool is_valid_memory_region(intptr_t addr) static inline bool is_valid_memory_region(intptr_t addr)

14
components/esp_hw_support/port/esp32c6/cpu_region_protect.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -32,10 +32,10 @@ static void esp_cpu_configure_invalid_regions(void)
__attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
// 1. Gap at bottom of address space // 1. Gap at bottom of address space
PMA_ENTRY_SET_TOR(0, SOC_DEBUG_LOW, PMA_TOR | PMA_NONE); PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE);
// 2. Gap between debug region & IROM // 2. Gap between CPU subsystem region & IROM
PMA_ENTRY_SET_TOR(1, SOC_DEBUG_HIGH, PMA_NONE); PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
// 3. Gap between ROM & RAM // 3. Gap between ROM & RAM
@ -111,10 +111,10 @@ void esp_cpu_configure_region_protection(void)
// Configure all the valid address regions using PMP // Configure all the valid address regions using PMP
// //
// 1. Debug region // 1. CPU Subsystem region - contains debug mode code and interrupt config registers
const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH); const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX); PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
// 2.1 I-ROM // 2.1 I-ROM
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE); PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);

14
components/esp_hw_support/port/esp32h2/cpu_region_protect.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -32,10 +32,10 @@ static void esp_cpu_configure_invalid_regions(void)
__attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X; __attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
// 1. Gap at bottom of address space // 1. Gap at bottom of address space
PMA_ENTRY_SET_TOR(0, SOC_DEBUG_LOW, PMA_TOR | PMA_NONE); PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE);
// 2. Gap between debug region & IROM // 2. Gap between CPU subsystem region & IROM
PMA_ENTRY_SET_TOR(1, SOC_DEBUG_HIGH, PMA_NONE); PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE); PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
// 3. Gap between ROM & RAM // 3. Gap between ROM & RAM
@ -111,10 +111,10 @@ void esp_cpu_configure_region_protection(void)
// Configure all the valid address regions using PMP // Configure all the valid address regions using PMP
// //
// 1. Debug region // 1. CPU Subsystem region - contains debug mode code and interrupt config registers
const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_DEBUG_LOW, SOC_DEBUG_HIGH); const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX); PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
_Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
// 2.1 I-ROM // 2.1 I-ROM
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE); PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);

8
components/soc/esp32c6/include/soc/soc.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -203,9 +203,9 @@
#define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000 #define SOC_PERIPHERAL_HIGH 0x60100000
// Debug region, not used by software // CPU sub-system region, contains interrupt config registers
#define SOC_DEBUG_LOW 0x20000000 #define SOC_CPU_SUBSYSTEM_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4087e610 #define SOC_ROM_STACK_START 0x4087e610

8
components/soc/esp32h2/include/soc/soc.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -201,9 +201,9 @@
#define SOC_PERIPHERAL_LOW 0x60000000 #define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000 #define SOC_PERIPHERAL_HIGH 0x60100000
// Debug region, not used by software // CPU sub-system region, contains interrupt config registers
#define SOC_DEBUG_LOW 0x20000000 #define SOC_CPU_SUBSYSTEM_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4084f380 #define SOC_ROM_STACK_START 0x4084f380

8
components/soc/esp32p4/include/soc/soc.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -220,9 +220,9 @@
#define SOC_LP_PERIPH_LOW 0x50110000 #define SOC_LP_PERIPH_LOW 0x50110000
#define SOC_LP_PERIPH_HIGH 0x50130000 #define SOC_LP_PERIPH_HIGH 0x50130000
// Debug region, not used by software // CPU sub-system region, contains interrupt config registers
#define SOC_DEBUG_LOW 0x20000000 #define SOC_CPU_SUBSYSTEM_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4ff3cfc0 #define SOC_ROM_STACK_START 0x4ff3cfc0