feat(hal): add esp32h21 modem_clock hal layer

2025-03-09 17:19:09 -04:00 · 2025-02-20 15:18:13 +08:00 · 2025-02-20 15:18:13 +08:00 · d305628c25
commit d305628c25
parent 88a3a6c58d
6 changed files with 589 additions and 1 deletions
--- a/components/hal/esp32h21/include/hal/lp_clkrst_ll.h
+++ b/components/hal/esp32h21/include/hal/lp_clkrst_ll.h
@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 LP CLKRST & LP PERI register operations
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value)
+{
+    hw->lpperi.clkrst_lp_bletimer_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
+{
+    return hw->lpperi.clkrst_lp_bletimer_div_num;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
+{
+    hw->lpperi.clkrst_lp_bletimer_32k_sel = src;
+}
+
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/hal/esp32h21/include/hal/modem_lpcon_ll.h
+++ b/components/hal/esp32h21/include/hal/modem_lpcon_ll.h
@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 MODEM LPCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_lpcon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
+{
+    return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_coex_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_fe_mem_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf_force_on.clk_coex_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf_force_on.clk_fe_mem_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.rst_coex = 1;
+    hw->rst_conf.rst_coex = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.val = 0xf;
+    hw->rst_conf.val = 0;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
+{
+    return hw->date.val;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/hal/esp32h21/include/hal/modem_syscon_ll.h
+++ b/components/hal/esp32h21/include/hal/modem_syscon_ll.h
@ -0,0 +1,275 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 MODEM SYSCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_syscon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
+{
+    // ESP32-H21 Not Support
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_etm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zb_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zb_mac_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_modem_sec_en = en;
+    hw->clk_conf.clk_modem_sec_ecb_en = en;
+    hw->clk_conf.clk_modem_sec_ccm_en = en;
+    hw->clk_conf.clk_modem_sec_bah_en = en;
+    hw->clk_conf.clk_modem_sec_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_ble_timer_apb_en = en;
+    hw->clk_conf.clk_ble_timer_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_data_dump_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_etm_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_modem_sec_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_ble_timer_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_data_dump_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_fe = 1;
+    hw->modem_rst_conf.rst_fe = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac_apb = 1;
+    hw->modem_rst_conf.rst_btmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac = 1;
+    hw->modem_rst_conf.rst_btmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb_apb = 1;
+    hw->modem_rst_conf.rst_btbb_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb = 1;
+    hw->modem_rst_conf.rst_btbb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_etm = 1;
+    hw->modem_rst_conf.rst_etm = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac = 1;
+    hw->modem_rst_conf.rst_zbmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac_apb = 1;
+    hw->modem_rst_conf.rst_zbmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_modem_ecb = 1;
+    hw->modem_rst_conf.rst_modem_ccm = 1;
+    hw->modem_rst_conf.rst_modem_bah = 1;
+    hw->modem_rst_conf.rst_modem_sec = 1;
+    hw->modem_rst_conf.rst_modem_ecb = 0;
+    hw->modem_rst_conf.rst_modem_ccm = 0;
+    hw->modem_rst_conf.rst_modem_bah = 0;
+    hw->modem_rst_conf.rst_modem_sec = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_ble_timer = 1;
+    hw->modem_rst_conf.rst_ble_timer = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_data_dump = 1;
+    hw->modem_rst_conf.rst_data_dump = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.val = 0xffffffff;
+    hw->modem_rst_conf.val = 0;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
+{
+    if(en){
+        hw->clk_conf1.val = hw->clk_conf1.val | mask;
+    } else {
+        hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
+    }
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_txlogain_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_16m_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_32m_en = en;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_sdm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_adc_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1_force_on.clk_fe_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1_force_on.clk_bt_fo = en;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
+{
+    return hw->date.val;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/hal/esp32h21/modem_clock_hal.c
+++ b/components/hal/esp32h21/modem_clock_hal.c
@ -0,0 +1,125 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The HAL layer for MODEM CLOCK (ESP32-H21 specific part)
+#include <stdbool.h>
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "hal/modem_clock_hal.h"
+#include "hal/lp_clkrst_ll.h"
+#include "hal/modem_clock_types.h"
+#include "hal/assert.h"
+
+typedef enum {
+    MODEM_CLOCK_XTAL32K_CODE = 0,
+    MODEM_CLOCK_RC32K_CODE   = 1,
+    MODEM_CLOCK_EXT32K_CODE  = 2
+} modem_clock_32k_clk_src_code_t;
+
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
+}
+
+void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
+    modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_txlogain_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
+}
+
+void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
+{
+    lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
+}
+
+void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    // BLE RTC Timer has bees moved to LP_AON domain, No clock gate on ESP32-H21
+}
+
+void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
+}
+
+void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}
+
+void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
+}
+
+void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@ -43,6 +43,10 @@ config SOC_SPI_FLASH_SUPPORTED
    bool
    default y

+config SOC_MODEM_CLOCK_SUPPORTED
+    bool
+    default y
+
 config SOC_PAU_SUPPORTED
    bool
    default y
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@ -63,7 +63,7 @@
 // #define SOC_WDT_SUPPORTED               1    //TODO: [ESP32H21] IDF-11528
 #define SOC_SPI_FLASH_SUPPORTED         1       //TODO: [ESP32H21] IDF-11526
 // #define SOC_RNG_SUPPORTED               1    //TODO: [ESP32H21] IDF-11503
-// #define SOC_MODEM_CLOCK_SUPPORTED       1
+#define SOC_MODEM_CLOCK_SUPPORTED       1
 // #define SOC_REG_I2C_SUPPORTED           1    //TODO: [ESP32H21] IDF-11550
 // #define SOC_PHY_SUPPORTED               1
 // #define SOC_PCNT_SUPPORTED              1    //TODO: [ESP32H21] IDF-11566