From 19e96add8a64eed8eb3cf0890b67b85c8d186fb3 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 6 Dec 2018 14:43:24 +0800 Subject: [PATCH 1/2] soc/rtc: reset BBPLL configuration after enabling it A workaround to reset BBPLL configuration after light sleep. Fixes the issue that Wi-Fi can not receive packets after waking up from light sleep. Ref. https://github.com/espressif/esp-idf/issues/2711 --- components/soc/esp32/rtc_clk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 79f9f23da9..67cef3ea97 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -39,10 +39,16 @@ #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) #define RTC_SLOW_CLK_FREQ_32K 32768 +/* BBPLL configuration values */ #define BBPLL_ENDIV5_VAL_320M 0x43 #define BBPLL_BBADC_DSMP_VAL_320M 0x84 #define BBPLL_ENDIV5_VAL_480M 0xc3 #define BBPLL_BBADC_DSMP_VAL_480M 0x74 +#define BBPLL_IR_CAL_DELAY_VAL 0x18 +#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 +#define BBPLL_OC_ENB_FCAL_VAL 0x9a +#define BBPLL_OC_ENB_VCON_VAL 0x00 + #define APLL_SDM_STOP_VAL_1 0x09 #define APLL_SDM_STOP_VAL_2_REV0 0x69 @@ -429,6 +435,12 @@ static void rtc_clk_bbpll_enable() CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); + + /* reset BBPLL configuration */ + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL); } /** From c7a297195f333eec16bd6d90993f241a125fcbf1 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 12 Dec 2018 12:22:48 +0800 Subject: [PATCH 2/2] soc/rtc: reset another BBPLL related register Follow-up to b21ffc8a: an additional register needs to be reset. Ref. https://github.com/espressif/esp-idf/issues/2711 --- components/soc/esp32/rtc_clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 67cef3ea97..8c2948553d 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -48,7 +48,7 @@ #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 #define BBPLL_OC_ENB_FCAL_VAL 0x9a #define BBPLL_OC_ENB_VCON_VAL 0x00 - +#define BBPLL_BBADC_CAL_7_0_VAL 0x00 #define APLL_SDM_STOP_VAL_1 0x09 #define APLL_SDM_STOP_VAL_2_REV0 0x69 @@ -441,6 +441,7 @@ static void rtc_clk_bbpll_enable() I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL); I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL); I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL); } /**