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Merge branch 'bugfix/fix_batch_of_i2c_issue_v5.3' into 'release/v5.3'

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fix(i2c_master): Fix an I2C issue that slave streth happen but master timeout...etc.4MR (backport v5.3)

See merge request espressif/esp-idf!33475
This commit is contained in:
morris 2024-09-13 15:49:39 +08:00
commit df00c22439
11 changed files with 255 additions and 120 deletions
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5
components/driver/i2c/i2c.c
View File

@ -684,7 +684,10 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
gpio_set_level(sda_io, 1); // STOP, SDA low -> high while SCL is HIGH gpio_set_level(sda_io, 1); // STOP, SDA low -> high while SCL is HIGH
i2c_set_pin(i2c_num, sda_io, scl_io, 1, 1, I2C_MODE_MASTER); i2c_set_pin(i2c_num, sda_io, scl_io, 1, 1, I2C_MODE_MASTER);
#else #else
i2c_ll_master_clr_bus(i2c_context[i2c_num].hal.dev, I2C_CLR_BUS_SCL_NUM); i2c_ll_master_clr_bus(i2c_context[i2c_num].hal.dev, I2C_CLR_BUS_SCL_NUM, true);
while (i2c_ll_master_is_bus_clear_done(i2c_context[i2c_num].hal.dev)) {
}
i2c_ll_update(i2c_context[i2c_num].hal.dev);
#endif #endif
return ESP_OK; return ESP_OK;
} }

61
components/esp_driver_i2c/i2c_master.c
View File

@ -46,8 +46,11 @@ static const char *TAG = "i2c.master";
#define I2C_FIFO_LEN(port_num) (SOC_I2C_FIFO_LEN) #define I2C_FIFO_LEN(port_num) (SOC_I2C_FIFO_LEN)
#endif #endif
#define I2C_CLR_BUS_TIMEOUT_MS (50) // 50ms is sufficient for clearing the bus
static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle) static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
{ {
esp_err_t ret = ESP_OK;
#if !SOC_I2C_SUPPORT_HW_CLR_BUS #if !SOC_I2C_SUPPORT_HW_CLR_BUS
const int scl_half_period = 5; // use standard 100kHz data rate const int scl_half_period = 5; // use standard 100kHz data rate
int i = 0; int i = 0;
@ -74,9 +77,23 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
i2c_common_set_pins(handle); i2c_common_set_pins(handle);
#else #else
i2c_hal_context_t *hal = &handle->hal; i2c_hal_context_t *hal = &handle->hal;
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT); i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT, true);
// If the i2c master clear bus state machine got disturbed when its work, it would go into error state.
// The solution here is to use freertos tick counter to set time threshold. If its not return on time,
// return invalid state and turn off the state machine for avoiding its always wrong.
TickType_t start_tick = xTaskGetTickCount();
const TickType_t timeout_ticks = pdMS_TO_TICKS(I2C_CLR_BUS_TIMEOUT_MS);
while (i2c_ll_master_is_bus_clear_done(hal->dev)) {
if ((xTaskGetTickCount() - start_tick) > timeout_ticks) {
ESP_LOGE(TAG, "clear bus failed.");
i2c_ll_master_clr_bus(hal->dev, 0, false);
ret = ESP_ERR_INVALID_STATE;
break;
}
}
i2c_ll_update(hal->dev);
#endif #endif
return ESP_OK; return ret;
} }
/** /**
@ -88,6 +105,7 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
*/ */
static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master) static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
{ {
esp_err_t ret = ESP_OK;
i2c_hal_context_t *hal = &i2c_master->base->hal; i2c_hal_context_t *hal = &i2c_master->base->hal;
#if !SOC_I2C_SUPPORT_HW_FSM_RST #if !SOC_I2C_SUPPORT_HW_FSM_RST
i2c_hal_timing_config_t timing_config; i2c_hal_timing_config_t timing_config;
@ -97,7 +115,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_get_filter(hal->dev, &filter_cfg); i2c_ll_master_get_filter(hal->dev, &filter_cfg);
//to reset the I2C hw module, we need re-enable the hw //to reset the I2C hw module, we need re-enable the hw
s_i2c_master_clear_bus(i2c_master->base); ret = s_i2c_master_clear_bus(i2c_master->base);
I2C_RCC_ATOMIC() { I2C_RCC_ATOMIC() {
i2c_ll_reset_register(i2c_master->base->port_num); i2c_ll_reset_register(i2c_master->base->port_num);
} }
@ -109,9 +127,9 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_set_filter(hal->dev, filter_cfg); i2c_ll_master_set_filter(hal->dev, filter_cfg);
#else #else
i2c_ll_master_fsm_rst(hal->dev); i2c_ll_master_fsm_rst(hal->dev);
s_i2c_master_clear_bus(i2c_master->base); ret = s_i2c_master_clear_bus(i2c_master->base);
#endif #endif
return ESP_OK; return ret;
} }
static void s_i2c_err_log_print(i2c_master_event_t event, bool bypass_nack_log) static void s_i2c_err_log_print(i2c_master_event_t event, bool bypass_nack_log)
@ -540,7 +558,7 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
// Sometimes when the FSM get stuck, the ACK_ERR interrupt will occur endlessly until we reset the FSM and clear bus. // Sometimes when the FSM get stuck, the ACK_ERR interrupt will occur endlessly until we reset the FSM and clear bus.
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
if (i2c_master->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(hal->dev)) { if (i2c_master->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(hal->dev)) {
s_i2c_hw_fsm_reset(i2c_master); ESP_RETURN_ON_ERROR(s_i2c_hw_fsm_reset(i2c_master), TAG, "reset hardware failed");
} }
if (i2c_master->base->pm_lock) { if (i2c_master->base->pm_lock) {
@ -554,23 +572,13 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
i2c_master->rx_cnt = 0; i2c_master->rx_cnt = 0;
i2c_master->read_len_static = 0; i2c_master->read_len_static = 0;
i2c_hal_master_set_scl_timeout_val(hal, i2c_dev->scl_wait_us, i2c_master->base->clk_src_freq_hz);
if (!i2c_master->base->is_lp_i2c) {
I2C_CLOCK_SRC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
#if SOC_LP_I2C_SUPPORTED
else {
LP_I2C_SRC_CLK_ATOMIC() {
lp_i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
#endif
I2C_CLOCK_SRC_ATOMIC() { I2C_CLOCK_SRC_ATOMIC() {
i2c_hal_set_bus_timing(hal, i2c_dev->scl_speed_hz, i2c_master->base->clk_src, i2c_master->base->clk_src_freq_hz); i2c_hal_set_bus_timing(hal, i2c_dev->scl_speed_hz, i2c_master->base->clk_src, i2c_master->base->clk_src_freq_hz);
} }
// Set the timeout value
i2c_hal_master_set_scl_timeout_val(hal, i2c_dev->scl_wait_us, i2c_master->base->clk_src_freq_hz);
i2c_ll_master_set_fractional_divider(hal->dev, 0, 0); i2c_ll_master_set_fractional_divider(hal->dev, 0, 0);
i2c_ll_update(hal->dev); i2c_ll_update(hal->dev);
@ -909,6 +917,19 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast
} }
ESP_GOTO_ON_ERROR(i2c_param_master_config(i2c_master->base, bus_config), err, TAG, "i2c configure parameter failed"); ESP_GOTO_ON_ERROR(i2c_param_master_config(i2c_master->base, bus_config), err, TAG, "i2c configure parameter failed");
if (!i2c_master->base->is_lp_i2c) {
I2C_CLOCK_SRC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
#if SOC_LP_I2C_SUPPORTED
else {
LP_I2C_SRC_CLK_ATOMIC() {
lp_i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
#endif
i2c_master->bus_lock_mux = xSemaphoreCreateBinaryWithCaps(I2C_MEM_ALLOC_CAPS); i2c_master->bus_lock_mux = xSemaphoreCreateBinaryWithCaps(I2C_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(i2c_master->bus_lock_mux, ESP_ERR_NO_MEM, err, TAG, "No memory for binary semaphore"); ESP_GOTO_ON_FALSE(i2c_master->bus_lock_mux, ESP_ERR_NO_MEM, err, TAG, "No memory for binary semaphore");
xSemaphoreGive(i2c_master->bus_lock_mux); xSemaphoreGive(i2c_master->bus_lock_mux);

24
components/hal/esp32/include/hal/i2c_ll.h
View File

@ -106,7 +106,7 @@ static inline void i2c_ll_master_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_confi
/* SCL period. According to the TRM, we should always subtract 1 to SCL low period */ /* SCL period. According to the TRM, we should always subtract 1 to SCL low period */
HAL_ASSERT(bus_cfg->scl_low > 0); HAL_ASSERT(bus_cfg->scl_low > 0);
hw->scl_low_period.period = bus_cfg->scl_low - 1; hw->scl_low_period.period = bus_cfg->scl_low - 1;
/* Still according to the TRM, if filter is not enbled, we have to subtract 7, /* Still according to the TRM, if filter is not enabled, we have to subtract 7,
* if SCL filter is enabled, we have to subtract: * if SCL filter is enabled, we have to subtract:
* 8 if SCL filter is between 0 and 2 (included) * 8 if SCL filter is between 0 and 2 (included)
* 6 + SCL threshold if SCL filter is between 3 and 7 (included) * 6 + SCL threshold if SCL filter is between 3 and 7 (included)
@ -547,7 +547,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -612,7 +612,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief Reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -633,11 +633,23 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
;//ESP32 do not support ;//ESP32 do not support
} }
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return false;
}
/** /**
* @brief Set I2C source clock * @brief Set I2C source clock
* *
@ -875,7 +887,7 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1058,7 +1070,7 @@ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in APB cycle) * @param hight_period The I2C SCL high period (in APB cycle)
* @param low_period The I2C SCL low period (in APB cycle) * @param low_period The I2C SCL low period (in APB cycle)
* *
* @return None. * @return None.

34
components/hal/esp32c2/include/hal/i2c_ll.h
View File

@ -583,7 +583,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -647,7 +647,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -667,18 +667,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -756,7 +767,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -791,7 +803,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -906,7 +918,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.

36
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@ -663,7 +663,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -698,7 +698,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM. * @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
*/ */
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{ {
@ -770,7 +770,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -790,18 +790,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -929,7 +940,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -968,7 +980,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1155,7 +1167,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.

42
components/hal/esp32c5/include/hal/i2c_ll.h
View File

@ -611,7 +611,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -646,7 +646,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM. * @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
*/ */
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{ {
@ -738,18 +738,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -790,8 +801,8 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1; ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
} }
@ -806,8 +817,8 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
{ {
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0; hw->fifo_conf.fifo_addr_cfg_en = 0;
} }
@ -863,7 +874,8 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -902,7 +914,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1090,7 +1102,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param hight_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.

34
components/hal/esp32c6/include/hal/i2c_ll.h
View File

@ -734,7 +734,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -754,18 +754,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses, // hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value. // and we should set conf_upgate bit to synchronize register value after this function.
while (hw->scl_sp_conf.scl_rst_slv_en); }
hw->ctr.conf_upgate = 1;
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -885,8 +896,8 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1; ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
} }
@ -901,8 +912,8 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
{ {
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0; hw->fifo_conf.fifo_addr_cfg_en = 0;
} }
@ -972,7 +983,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////

44
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@ -613,7 +613,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -648,7 +648,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM. * @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
*/ */
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{ {
@ -720,7 +720,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -740,18 +740,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -792,8 +803,8 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1; ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
} }
@ -808,8 +819,8 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
{ {
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0; hw->fifo_conf.fifo_addr_cfg_en = 0;
} }
@ -879,7 +890,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -918,7 +930,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1106,7 +1118,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.

44
components/hal/esp32p4/include/hal/i2c_ll.h
View File

@ -615,7 +615,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -650,7 +650,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM. * @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
*/ */
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{ {
@ -722,7 +722,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -742,18 +742,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
} }
/** /**
@ -889,8 +900,8 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1; ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
} }
@ -905,8 +916,8 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
{ {
typeof(hw->ctr) ctrl_reg; typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0; ctrl_reg.val = 0;
ctrl_reg.sda_force_out = 1; ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 1; ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val; hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0; hw->fifo_conf.fifo_addr_cfg_en = 0;
} }
@ -976,7 +987,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -1015,7 +1027,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1203,7 +1215,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.

23
components/hal/esp32s2/include/hal/i2c_ll.h
View File

@ -573,7 +573,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -658,16 +658,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 0; hw->scl_sp_conf.scl_rst_slv_en = 0;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = 1;
} }
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return false; // not supported on esp32s2
}
/** /**
* @brief Set I2C source clock * @brief Set I2C source clock
* *
@ -717,7 +730,7 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
* Otherwise it is not needed. * Otherwise it is not needed.
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param internal_od_ena Set true to enble internal open-drain, otherwise, set it false. * @param internal_od_ena Set true to enable internal open-drain, otherwise, set it false.
* *
* @return None * @return None
*/ */
@ -908,7 +921,7 @@ typedef enum {
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1096,7 +1109,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in APB cycle, hight_period > 2) * @param hight_period The I2C SCL high period (in APB cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in APB cycle, low_period > 1) * @param low_period The I2C SCL low period (in APB cycle, low_period > 1)
* *
* @return None. * @return None.

28
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@ -671,7 +671,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
* *
* @return None. * @return None.
*/ */
@ -706,7 +706,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM. * @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer * @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen * @param len Amount of data needs to be written
*/ */
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len) static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{ {
@ -778,7 +778,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
} }
/** /**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM * @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* *
@ -797,16 +797,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out. * @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
* *
* @return None * @return None
*/ */
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{ {
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses; hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1; hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1; hw->ctr.conf_upgate = 1;
} }
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return false; // not supported on esp32s3
}
/** /**
* @brief Set I2C source clock * @brief Set I2C source clock
* *
@ -931,7 +944,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us) static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{ {
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000); uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us); // round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
} }
//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@ -986,7 +1000,7 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period. * @param wait_high_period The I2C SCL wait rising edge period.
* *
@ -1157,7 +1171,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing * @brief Configure I2C SCL timing
* *
* @param hw Beginning address of the peripheral registers * @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) * @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* *
* @return None. * @return None.