From e12812a4d7c6ed7be05a50eb1e186759251848e1 Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 24 Dec 2024 14:22:38 +0800 Subject: [PATCH] fix(psram): fixed mode reg read bad timing on octal and hex psrams --- components/esp_psram/device/esp_psram_impl_ap_hex.c | 7 +++++-- components/esp_psram/esp32s3/esp_psram_impl_octal.c | 5 +++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c index 7832460eb3..5741acef32 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_hex.c +++ b/components/esp_psram/device/esp_psram_impl_ap_hex.c @@ -30,16 +30,19 @@ #if CONFIG_SPIRAM_SPEED_250M #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(18-1)) +#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(9-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(9-1)) #define AP_HEX_PSRAM_RD_LATENCY 6 #define AP_HEX_PSRAM_WR_LATENCY 3 #elif CONFIG_SPIRAM_SPEED_200M #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(14-1)) +#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(7-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(7-1)) #define AP_HEX_PSRAM_RD_LATENCY 4 #define AP_HEX_PSRAM_WR_LATENCY 1 #else #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) +#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define AP_HEX_PSRAM_RD_LATENCY 2 #define AP_HEX_PSRAM_WR_LATENCY 2 @@ -137,7 +140,7 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co int cmd_len = 16; uint32_t addr = 0x0; int addr_bit_len = 32; - int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN; + int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN; hex_psram_mode_reg_t mode_reg = {0}; int data_bit_len = 16; @@ -216,7 +219,7 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg) { int cmd_len = 16; int addr_bit_len = 32; - int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN; + int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN; int data_bit_len = 16; //Read MR0~1 register diff --git a/components/esp_psram/esp32s3/esp_psram_impl_octal.c b/components/esp_psram/esp32s3/esp_psram_impl_octal.c index f2a775ed0e..358bfb7f3a 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_octal.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_octal.c @@ -31,6 +31,7 @@ #define OCT_PSRAM_WR_CMD_BITLEN 16 #define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) +#define OCT_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define OCT_PSRAM_CS1_IO MSPI_IOMUX_PIN_NUM_CS1 #define OCT_PSRAM_VENDOR_ID 0xD @@ -115,7 +116,7 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co int cmd_len = 16; uint32_t addr = 0x0; //0x0 is the MR0 register int addr_bit_len = 32; - int dummy = OCT_PSRAM_RD_DUMMY_BITLEN; + int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN; opi_psram_mode_reg_t mode_reg = {0}; int data_bit_len = 16; @@ -178,7 +179,7 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg) esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE; int cmd_len = 16; int addr_bit_len = 32; - int dummy = OCT_PSRAM_RD_DUMMY_BITLEN; + int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN; int data_bit_len = 16; //Read MR0~1 register