feat(pwr_glitch): Add power glitch support on esp32c5/esp32c61

components/bootloader_support/private_include/bootloader_soc.h

@@ -24,6 +24,14 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
  */
 void bootloader_ana_clock_glitch_reset_config(bool enable);
 
+/**
+ * @brief Configure analog power glitch reset & glitch reset dref
+ *
+ * @param enable Boolean to enable or disable power glitch reset
+ * @param dref voltage threshold
+ */
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
+
 #ifdef __cplusplus
 }
 #endif

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -92,11 +92,10 @@ static inline void bootloader_hardware_init(void)
 
 static inline void bootloader_ana_reset_config(void)
 {
-    // TODO: [ESP32C5] IDF-8650
-    //Enable super WDT reset.
-    // bootloader_ana_super_wdt_reset_config(true);
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
+    uint8_t power_glitch_dref = 0;
+    bootloader_power_glitch_reset_config(true, power_glitch_dref);
 }
 
 esp_err_t bootloader_init(void)

components/bootloader_support/src/esp32c5/bootloader_soc.c

@@ -7,18 +7,29 @@
 #include <assert.h>
 #include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
-// TODO: [ESP32C5] IDF-8667 remove esp_log.h
+#include "soc/pmu_reg.h"
-#include "esp_log.h"
+#include "hal/regi2c_ctrl.h"
-
+#include "soc/regi2c_saradc.h"
-void bootloader_ana_super_wdt_reset_config(bool enable)
-{
-    // TODO: [ESP32C5] IDF-8667
-    ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
-}
 
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-     // TODO: [ESP32C5] IDF-8667, PM-207
     (void)enable;
 }
+
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+{
+    assert(dref < 8);
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    if (enable) {
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
+        REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
+    } else {
+        REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
+    }
+}

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -93,17 +93,17 @@ static inline void bootloader_hardware_init(void)
 
 static inline void bootloader_ana_reset_config(void)
 {
-    //Enable super WDT reset.
-    bootloader_ana_super_wdt_reset_config(true);
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
+    uint8_t power_glitch_dref = 0;
+    bootloader_power_glitch_reset_config(true, power_glitch_dref);
 }
 
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
     bootloader_hardware_init();
-    // bootloader_ana_reset_config();   //TODO: [ESP32C61] IDF-9260
+    bootloader_ana_reset_config();
     bootloader_super_wdt_auto_feed();
 
 // In RAM_APP, memory will be initialized in `call_start_cpu0`

components/bootloader_support/src/esp32c61/bootloader_soc.c

@@ -7,19 +7,29 @@
 #include <assert.h>
 #include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
-
+#include "soc/pmu_reg.h"
-//TODO: [ESP32C61] IDF-9260, commented in verify code, check
+#include "hal/regi2c_ctrl.h"
-
+#include "soc/regi2c_saradc.h"
-void bootloader_ana_super_wdt_reset_config(bool enable)
-{
-    //C61 doesn't support bypass super WDT reset
-    assert(enable);
-    // lp_analog_peri_reg.h updated, now following registers
-    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
-}
 
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
     (void)enable;
 }
+
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+{
+    assert(dref < 8);
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    if (enable) {
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
+    } else {
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
+    }
+}

components/hal/esp32c5/include/hal/brownout_ll.h

@@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable)
     LP_ANA_PERI.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE;
     // then we can enable or disable if we want the BOD mode1 to reset the system
     LP_ANA_PERI.bod_mode1_cntl.bod_mode1_reset_ena = enable;
-    // Disable the power glitch detect.
-    LP_ANA_PERI.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5);
 }
 
 /**

components/hal/esp32c61/include/hal/brownout_ll.h

@@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable)
     LP_ANA.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE;
     // then we can enable or disable if we want the BOD mode1 to reset the system
     LP_ANA.bod_mode1_cntl.bod_mode1_reset_ena = enable;
-    // Disable the power glitch detect.
-    LP_ANA.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5);
 }
 
 /**

components/soc/esp32c5/include/soc/lp_analog_peri_reg.h

@@ -129,6 +129,11 @@ extern "C" {
 #define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
 #define LP_ANA_ANA_FIB_ENA_S  0
 
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA    0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M  (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V  0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S  2
+
 /** LP_ANA_INT_RAW_REG register
  *  interrpt raw register
  */

components/soc/esp32c5/include/soc/regi2c_saradc.h

@@ -81,3 +81,19 @@
 #define ADC_SARADC2_EN_TOUT_ADDR            0x8
 #define ADC_SARADC2_EN_TOUT_ADDR_MSB        0x2
 #define ADC_SARADC2_EN_TOUT_ADDR_LSB        0x2
+
+#define POWER_GLITCH_DREF_VDET_PERIF         11
+#define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
+#define POWER_GLITCH_DREF_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_DREF_VDET_VDDPST        11
+#define POWER_GLITCH_DREF_VDET_VDDPST_MSB    6
+#define POWER_GLITCH_DREF_VDET_VDDPST_LSB    4
+
+#define POWER_GLITCH_DREF_VDET_XTAL          12
+#define POWER_GLITCH_DREF_VDET_XTAL_MSB      2
+#define POWER_GLITCH_DREF_VDET_XTAL_LSB      0
+
+#define POWER_GLITCH_DREF_VDET_PLL           12
+#define POWER_GLITCH_DREF_VDET_PLL_MSB       6
+#define POWER_GLITCH_DREF_VDET_PLL_LSB       4

components/soc/esp32c61/include/soc/lp_analog_peri_reg.h

@@ -108,6 +108,11 @@ extern "C" {
 #define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
 #define LP_ANA_ANA_FIB_ENA_S  0
 
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA    0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M  (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V  0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S  2
+
 /** LP_ANA_INT_RAW_REG register
  *  need_des
  */

components/soc/esp32c61/include/soc/regi2c_saradc.h

@@ -18,41 +18,39 @@
 #define I2C_SAR_ADC            0X69
 #define I2C_SAR_ADC_HOSTID     0
 
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
 
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
 
 #define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
 #define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
 #define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
 
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
 
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
 
 #define ADC_SAR1_DREF_ADDR  0x2
 #define ADC_SAR1_DREF_ADDR_MSB  0x6
 #define ADC_SAR1_DREF_ADDR_LSB  0x4
 
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
 #define ADC_SAR2_DREF_ADDR  0x5
 #define ADC_SAR2_DREF_ADDR_MSB  0x6
 #define ADC_SAR2_DREF_ADDR_LSB  0x4
 
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define I2C_SARADC_TSENS_DAC 0x6
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define I2C_SARADC_TSENS_DAC_MSB 3
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+#define I2C_SARADC_TSENS_DAC_LSB 0
 
 #define ADC_SARADC_DTEST_RTC_ADDR 0x7
 #define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
@@ -70,10 +68,31 @@
 #define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
 #define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
 
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
 #define ADC_SARADC2_ENCAL_REF_ADDR 0x7
 #define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
 #define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
 
-#define I2C_SARADC_TSENS_DAC 0x6
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define I2C_SARADC_TSENS_DAC_MSB 3
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define I2C_SARADC_TSENS_DAC_LSB 0
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+
+#define POWER_GLITCH_DREF_VDET_PERIF         11
+#define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
+#define POWER_GLITCH_DREF_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_DREF_VDET_VDDPST        11
+#define POWER_GLITCH_DREF_VDET_VDDPST_MSB    6
+#define POWER_GLITCH_DREF_VDET_VDDPST_LSB    4
+
+#define POWER_GLITCH_DREF_VDET_PLLBB         12
+#define POWER_GLITCH_DREF_VDET_PLLBB_MSB      2
+#define POWER_GLITCH_DREF_VDET_PLLBB_LSB      0
+
+#define POWER_GLITCH_DREF_VDET_PLL           12
+#define POWER_GLITCH_DREF_VDET_PLL_MSB       6
+#define POWER_GLITCH_DREF_VDET_PLL_LSB       4