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Merge branch 'bugfix/memprot_wrong_fi_check_v4.3' into 'release/v4.3'

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System/Memprot: Fixed voltage glitching detection logic (v4.3)

See merge request espressif/esp-idf!15412
This commit is contained in:
Martin Vychodil 2021-10-11 03:02:51 +00:00
commit e1b9532848
2 changed files with 102 additions and 95 deletions
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149
components/esp32c3/memprot.c
View File

@ -26,6 +26,8 @@
#include "esp32c3/memprot.h" #include "esp32c3/memprot.h"
#include "riscv/interrupt.h" #include "riscv/interrupt.h"
#include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/ets_sys.h"
#include "esp_fault.h"
#include "soc/cpu.h"
extern int _iram_text_end; extern int _iram_text_end;
@ -99,18 +101,18 @@ void *esp_memprot_get_default_main_split_addr()
uint32_t *esp_memprot_get_split_addr(split_line_t line_type) uint32_t *esp_memprot_get_split_addr(split_line_t line_type)
{ {
switch ( line_type ) { switch ( line_type ) {
case MEMPROT_IRAM0_DRAM0_SPLITLINE: case MEMPROT_IRAM0_DRAM0_SPLITLINE:
return memprot_ll_get_iram0_split_line_main_I_D(); return memprot_ll_get_iram0_split_line_main_I_D();
case MEMPROT_IRAM0_LINE_0_SPLITLINE: case MEMPROT_IRAM0_LINE_0_SPLITLINE:
return memprot_ll_get_iram0_split_line_I_0(); return memprot_ll_get_iram0_split_line_I_0();
case MEMPROT_IRAM0_LINE_1_SPLITLINE: case MEMPROT_IRAM0_LINE_1_SPLITLINE:
return memprot_ll_get_iram0_split_line_I_1(); return memprot_ll_get_iram0_split_line_I_1();
case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE: case MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE:
return memprot_ll_get_dram0_split_line_D_0(); return memprot_ll_get_dram0_split_line_D_0();
case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE: case MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE:
return memprot_ll_get_dram0_split_line_D_1(); return memprot_ll_get_dram0_split_line_D_1();
default: default:
abort(); abort();
} }
} }
@ -397,9 +399,9 @@ pms_world_t esp_memprot_get_violate_world(mem_type_prot_t mem_type)
} }
switch ( world ) { switch ( world ) {
case 0x01: return MEMPROT_PMS_WORLD_0; case 0x01: return MEMPROT_PMS_WORLD_0;
case 0x10: return MEMPROT_PMS_WORLD_1; case 0x10: return MEMPROT_PMS_WORLD_1;
default: return MEMPROT_PMS_WORLD_INVALID; default: return MEMPROT_PMS_WORLD_INVALID;
} }
} }
@ -469,74 +471,81 @@ void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t
void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask) void esp_memprot_set_prot_int(bool invoke_panic_handler, bool lock_feature, void *split_addr, uint32_t *mem_type_mask)
{ {
uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask; //if being debugged check we are not glitched and dont enable Memprot
bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM; if (esp_cpu_in_ocd_debug_mode()) {
bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM; ESP_FAULT_ASSERT(esp_cpu_in_ocd_debug_mode());
} else {
uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t) MEMPROT_ALL : *mem_type_mask;
bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM;
bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM;
if (required_mem_prot == MEMPROT_NONE) { if (required_mem_prot == MEMPROT_NONE) {
return; return;
} }
//disable protection //disable protection
if (use_iram0) {
esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false);
}
if (use_dram0) {
esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false);
}
//panic handling
if (invoke_panic_handler) {
if (use_iram0) { if (use_iram0) {
esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM); esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, false);
} }
if (use_dram0) { if (use_dram0) {
esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM); esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, false);
} }
}
//set split lines (must-have for all mem_types) //panic handling
const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr; if (invoke_panic_handler) {
esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr); if (use_iram0) {
esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr); esp_memprot_set_intr_matrix(MEMPROT_IRAM0_SRAM);
esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr); }
esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr))); if (use_dram0) {
esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE, (void *)(MAP_IRAM_TO_DRAM((uint32_t)line_addr))); esp_memprot_set_intr_matrix(MEMPROT_DRAM0_SRAM);
}
}
//set permissions //set split lines (must-have for all mem_types)
if (required_mem_prot & MEMPROT_IRAM0_SRAM) { const void *line_addr = split_addr == NULL ? esp_memprot_get_default_main_split_addr() : split_addr;
esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true); esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_1_SPLITLINE, line_addr);
esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true); esp_memprot_set_split_line(MEMPROT_IRAM0_LINE_0_SPLITLINE, line_addr);
esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true); esp_memprot_set_split_line(MEMPROT_IRAM0_DRAM0_SPLITLINE, line_addr);
esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false); esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_0_SPLITLINE,
} (void *) (MAP_IRAM_TO_DRAM((uint32_t) line_addr)));
if (required_mem_prot & MEMPROT_DRAM0_SRAM) { esp_memprot_set_split_line(MEMPROT_DRAM0_DMA_LINE_1_SPLITLINE,
esp_memprot_dram_set_pms_area( MEMPROT_DRAM0_PMS_AREA_0, true, false ); (void *) (MAP_IRAM_TO_DRAM((uint32_t) line_addr)));
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true);
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true);
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true);
}
//reenable protection //set permissions
if (use_iram0) { if (required_mem_prot & MEMPROT_IRAM0_SRAM) {
esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM); esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, true, false, true);
esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true); esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, true, false, true);
} esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, true, false, true);
if (use_dram0) { esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, true, true, false);
esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM); }
esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true); if (required_mem_prot & MEMPROT_DRAM0_SRAM) {
} esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_0, true, false);
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, true, true);
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, true, true);
esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, true, true);
}
//lock if required //reenable protection
if (lock_feature) {
esp_memprot_set_split_line_lock();
if (use_iram0) { if (use_iram0) {
esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM); esp_memprot_monitor_clear_intr(MEMPROT_IRAM0_SRAM);
esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM); esp_memprot_set_monitor_en(MEMPROT_IRAM0_SRAM, true);
} }
if (use_dram0) { if (use_dram0) {
esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM); esp_memprot_monitor_clear_intr(MEMPROT_DRAM0_SRAM);
esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM); esp_memprot_set_monitor_en(MEMPROT_DRAM0_SRAM, true);
}
//lock if required
if (lock_feature) {
esp_memprot_set_split_line_lock();
if (use_iram0) {
esp_memprot_set_pms_lock(MEMPROT_IRAM0_SRAM);
esp_memprot_set_monitor_lock(MEMPROT_IRAM0_SRAM);
}
if (use_dram0) {
esp_memprot_set_pms_lock(MEMPROT_DRAM0_SRAM);
esp_memprot_set_monitor_lock(MEMPROT_DRAM0_SRAM);
}
} }
} }
} }

48
components/esp32s2/memprot.c
View File

@ -30,7 +30,6 @@ static const char *TAG = "memprot";
#include "hal/memprot_ll.h" #include "hal/memprot_ll.h"
#include "hal/memprot_peri_ll.h" #include "hal/memprot_peri_ll.h"
#include "esp_fault.h" #include "esp_fault.h"
#include "soc/cpu.h" #include "soc/cpu.h"
extern int _iram_text_end; extern int _iram_text_end;
@ -650,33 +649,32 @@ void esp_memprot_set_prot_peri2(mem_type_prot_t mem_type, uint32_t *split_addr,
void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask) void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask)
{ {
//any IRAM0/DRAM0 enable/disable call applies to all memory modules connected //if being debugged check we are not glitched and dont enable Memprot
uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask; if (esp_cpu_in_ocd_debug_mode()) {
bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM || required_mem_prot & MEMPROT_IRAM0_RTCFAST; ESP_FAULT_ASSERT(esp_cpu_in_ocd_debug_mode());
bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM || required_mem_prot & MEMPROT_DRAM0_RTCFAST; } else {
bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
//disable protection //any IRAM0/DRAM0 enable/disable call applies to all memory modules connected
if (use_iram0) { uint32_t required_mem_prot = mem_type_mask == NULL ? (uint32_t)MEMPROT_ALL : *mem_type_mask;
esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false); bool use_iram0 = required_mem_prot & MEMPROT_IRAM0_SRAM || required_mem_prot & MEMPROT_IRAM0_RTCFAST;
} bool use_dram0 = required_mem_prot & MEMPROT_DRAM0_SRAM || required_mem_prot & MEMPROT_DRAM0_RTCFAST;
if (use_dram0) { bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, false); bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
}
if (use_peri1) {
esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, false);
}
if (use_peri2) {
esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, false);
}
//connect to intr. matrix if not being debugged //disable protection
if (!esp_cpu_in_ocd_debug_mode()) { if (use_iram0) {
esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false);
}
if (use_dram0) {
esp_memprot_intr_ena(MEMPROT_DRAM0_SRAM, false);
}
if (use_peri1) {
esp_memprot_intr_ena(MEMPROT_PERI1_RTCSLOW, false);
}
if (use_peri2) {
esp_memprot_intr_ena(MEMPROT_PERI2_RTCSLOW_0, false);
}
ESP_FAULT_ASSERT(!esp_cpu_in_ocd_debug_mode());
//initialize for specific buses (any memory type does the job)
if (invoke_panic_handler) { if (invoke_panic_handler) {
if (use_iram0) { if (use_iram0) {
esp_memprot_intr_init(MEMPROT_IRAM0_SRAM); esp_memprot_intr_init(MEMPROT_IRAM0_SRAM);