blackbeard420/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf synced 2025-03-10 09:39:10 -04:00
Code Issues Projects Releases Wiki Activity

fix(esp_hw_support): fix bad logic in esp_perip_clk_init

Browse Source
This commit is contained in:
wuzhenghui 2024-04-12 14:08:07 +08:00
parent 052e884f34
commit e7046e2abf
No known key found for this signature in database
GPG Key ID: 3EFEDECDEBA39BB9
2 changed files with 10 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -217,9 +217,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason != RESET_REASON_CPU0_MWDT0 && rst_reason != RESET_REASON_CPU0_MWDT1 \ if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \
&& rst_reason != RESET_REASON_CPU0_SW && rst_reason != RESET_REASON_CPU0_RTC_WDT \ && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \
&& RESET_REASON_CPU0_JTAG) { && (rst_reason != RESET_REASON_CPU0_JTAG)) {
#if CONFIG_ESP_CONSOLE_UART_NUM != 0 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
uart_ll_enable_bus_clock(UART_NUM_0, false); uart_ll_enable_bus_clock(UART_NUM_0, false);
#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 #elif CONFIG_ESP_CONSOLE_UART_NUM != 1
@ -289,8 +289,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#endif #endif
} }
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) { || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
_lp_i2c_ll_enable_bus_clock(0, false); _lp_i2c_ll_enable_bus_clock(0, false);
_lp_uart_ll_enable_bus_clock(0, false); _lp_uart_ll_enable_bus_clock(0, false);
lp_core_ll_enable_bus_clock(false); lp_core_ll_enable_bus_clock(false);

9
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -210,8 +210,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason != RESET_REASON_CPU0_MWDT0 && rst_reason != RESET_REASON_CPU0_MWDT1 \ if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \
&& rst_reason != RESET_REASON_CPU0_SW && rst_reason != RESET_REASON_CPU0_RTC_WDT) { && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \
&& (rst_reason != RESET_REASON_CPU0_JTAG)) {
#if CONFIG_ESP_CONSOLE_UART_NUM != 0 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
uart_ll_enable_bus_clock(UART_NUM_0, false); uart_ll_enable_bus_clock(UART_NUM_0, false);
#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 #elif CONFIG_ESP_CONSOLE_UART_NUM != 1
@ -280,8 +281,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#endif #endif
} }
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \ if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) { || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
_lp_clkrst_ll_enable_rng_clock(false); _lp_clkrst_ll_enable_rng_clock(false);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN); CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN); CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);