From 7b37158ede891b2001505fdbecac5696b46bd9a5 Mon Sep 17 00:00:00 2001 From: morris Date: Sun, 7 Feb 2021 17:18:39 +0800 Subject: [PATCH 1/2] rmt: distinguish group and channel in HAL layer --- components/driver/include/driver/rmt.h | 7 +-- components/driver/rmt.c | 45 ++++++++++--------- components/driver/test/test_rmt.c | 28 ++++++------ components/hal/esp32/include/hal/rmt_ll.h | 28 ++++++------ components/hal/esp32c3/include/hal/rmt_ll.h | 38 ++++++++-------- components/hal/esp32s2/include/hal/rmt_ll.h | 38 ++++++++-------- components/hal/esp32s3/include/hal/rmt_ll.h | 38 ++++++++-------- components/hal/include/hal/rmt_hal.h | 2 +- components/hal/include/hal/rmt_types.h | 2 +- components/hal/rmt_hal.c | 8 ++-- components/soc/esp32/include/soc/soc_caps.h | 13 +++--- components/soc/esp32c3/include/soc/rmt_caps.h | 33 -------------- components/soc/esp32c3/include/soc/soc_caps.h | 15 +++++-- components/soc/esp32s2/include/soc/soc_caps.h | 15 ++++--- components/soc/esp32s3/include/soc/soc_caps.h | 11 ++--- components/soc/include/soc/rmt_periph.h | 2 +- .../test_utils/ref_clock_impl_rmt_pcnt.c | 6 +-- 17 files changed, 159 insertions(+), 170 deletions(-) delete mode 100644 components/soc/esp32c3/include/soc/rmt_caps.h diff --git a/components/driver/include/driver/rmt.h b/components/driver/include/driver/rmt.h index 930aac01ce..ca4734d029 100644 --- a/components/driver/include/driver/rmt.h +++ b/components/driver/include/driver/rmt.h @@ -38,7 +38,7 @@ extern "C" { * @brief Define memory space of each RMT channel (in words = 4 bytes) * */ -#define RMT_MEM_ITEM_NUM SOC_RMT_CHANNEL_MEM_WORDS +#define RMT_MEM_ITEM_NUM SOC_RMT_MEM_WORDS_PER_CHANNEL /** * @brief Data struct of RMT TX configure parameters @@ -384,6 +384,7 @@ esp_err_t rmt_rx_memory_reset(rmt_channel_t channel); /** * @brief Set RMT memory owner. +* @note Setting memroy is only valid for RX channel. * * @param channel RMT channel * @param owner To set when the transmitter or receiver can process the memory of channel. @@ -835,9 +836,9 @@ rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, voi esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh); #endif -#if SOC_RMT_SUPPORT_TX_GROUP +#if SOC_RMT_SUPPORT_TX_SYNCHRO /** -* @brief Add channel into a group (channels in the same group will transmit simultaneously) +* @brief Add channel into a synchronous group (channels in the same group can start transaction simultaneously) * * @param channel RMT channel * diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 74b5e3116b..2e1daf5761 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -60,8 +60,8 @@ static const char *RMT_TAG = "rmt"; #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock)) #define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock)) -#define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_NUM-SOC_RMT_TX_CHANNELS_NUM) -#define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CHANNELS_NUM-1) +#define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP) +#define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1) #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START) #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END) @@ -76,6 +76,7 @@ typedef struct { rmt_tx_end_callback_t rmt_tx_end_callback;// Event called when transmission is ended uint8_t rmt_driver_channels; // Bitmask of installed drivers' channels bool rmt_module_enabled; + uint32_t synchro_channel_mask; // Bitmap of channels already added in the synchronous group } rmt_contex_t; typedef struct { @@ -115,6 +116,7 @@ static rmt_contex_t rmt_contex = { }, .rmt_driver_channels = 0, .rmt_module_enabled = false, + .synchro_channel_mask = 0 }; static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0}; @@ -153,9 +155,9 @@ esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt) RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { - rmt_ll_rx_set_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); + rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); } else { - rmt_ll_tx_set_counter_clock_div(rmt_contex.hal.regs, channel, div_cnt); + rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt); } RMT_EXIT_CRITICAL(); return ESP_OK; @@ -167,9 +169,9 @@ esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt) RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { - *div_cnt = (uint8_t)rmt_ll_rx_get_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); + *div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); } else { - *div_cnt = (uint8_t)rmt_ll_tx_get_counter_clock_div(rmt_contex.hal.regs, channel); + *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel); } RMT_EXIT_CRITICAL(); return ESP_OK; @@ -395,7 +397,7 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk) RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); - rmt_ll_set_counter_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0); + rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0); RMT_EXIT_CRITICAL(); return ESP_OK; } @@ -404,7 +406,7 @@ esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk) { RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); - *src_clk = (rmt_source_clk_t)rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel); + *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel); RMT_EXIT_CRITICAL(); return ESP_OK; } @@ -583,16 +585,16 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #if SOC_RMT_SUPPORT_XTAL // clock src: XTAL_CLK rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000; - rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_XTAL, 0, 0, 0); + rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_XTAL, 0, 0, 0); #elif SOC_RMT_SUPPORT_REF_TICK // clock src: REF_CLK rmt_source_clk_hz = REF_CLK_FREQ; - rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_REF, 0, 0, 0); + rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_REF, 0, 0, 0); #endif } else { // clock src: APB_CLK rmt_source_clk_hz = APB_CLK_FREQ; - rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_APB, 0, 0, 0); + rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_APB, 0, 0, 0); } RMT_EXIT_CRITICAL(); @@ -612,7 +614,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par uint8_t idle_level = rmt_param->tx_config.idle_level; RMT_ENTER_CRITICAL(); - rmt_ll_tx_set_counter_clock_div(dev, channel, clk_div); + rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div); rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt); rmt_ll_tx_reset_pointer(dev, channel); rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en); @@ -648,7 +650,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par uint16_t threshold = rmt_param->rx_config.idle_threshold; RMT_ENTER_CRITICAL(); - rmt_ll_rx_set_counter_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div); + rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div); rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt); rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel)); rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), RMT_MEM_OWNER_HW); @@ -666,7 +668,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #if SOC_RMT_SUPPORT_RX_DEMODULATION rmt_ll_rx_enable_carrier_demodulation(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.rm_carrier); if (rmt_param->rx_config.rm_carrier) { - uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_counter_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz; + uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz; uint32_t duty_high = duty_total * rmt_param->rx_config.carrier_duty_percent / 100; // there could be residual in timing the carrier pulse, so double enlarge the theoretical value rmt_ll_rx_set_carrier_high_low_ticks(dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, (duty_total - duty_high) * 2); @@ -1321,22 +1323,23 @@ esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz) rmt_source_clk_hz = s_rmt_source_clock_hz; #endif if (RMT_IS_RX_CHANNEL(channel)) { - *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); + *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); } else { - *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_counter_clock_div(rmt_contex.hal.regs, channel); + *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel); } RMT_EXIT_CRITICAL(); return ESP_OK; } -#if SOC_RMT_SUPPORT_TX_GROUP +#if SOC_RMT_SUPPORT_TX_SYNCHRO esp_err_t rmt_add_channel_to_group(rmt_channel_t channel) { RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true); - rmt_ll_tx_add_channel_to_group(rmt_contex.hal.regs, channel); - rmt_ll_tx_reset_counter_clock_div(rmt_contex.hal.regs, channel); + rmt_contex.synchro_channel_mask |= (1 << channel); + rmt_ll_tx_add_to_sync_group(rmt_contex.hal.regs, channel); + rmt_ll_tx_reset_channels_clock_div(rmt_contex.hal.regs, rmt_contex.synchro_channel_mask); RMT_EXIT_CRITICAL(); return ESP_OK; } @@ -1345,7 +1348,9 @@ esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel) { RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); - if (rmt_ll_tx_remove_channel_from_group(rmt_contex.hal.regs, channel) == 0) { + rmt_contex.synchro_channel_mask &= ~(1 << channel); + rmt_ll_tx_remove_from_sync_group(rmt_contex.hal.regs, channel); + if (rmt_contex.synchro_channel_mask == 0) { rmt_ll_tx_enable_sync(rmt_contex.hal.regs, false); } RMT_EXIT_CRITICAL(); diff --git a/components/driver/test/test_rmt.c b/components/driver/test/test_rmt.c index 283d6ef0f1..6874d493db 100644 --- a/components/driver/test/test_rmt.c +++ b/components/driver/test/test_rmt.c @@ -12,8 +12,8 @@ #include "test_utils.h" #include "esp_rom_gpio.h" -#define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_NUM-SOC_RMT_TX_CHANNELS_NUM) -#define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CHANNELS_NUM-1) +#define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP) +#define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1) // CI ONLY: Don't connect any other signals to this GPIO #define RMT_DATA_IO (4) // bind signal RMT_SIG_OUT0_IDX and RMT_SIG_IN0_IDX on the same GPIO @@ -112,7 +112,7 @@ TEST_CASE("RMT wrong configuration", "[rmt]") TEST_ASSERT(rmt_config(&wrong_config) == ESP_ERR_INVALID_ARG); wrong_config = correct_config; - wrong_config.channel = SOC_RMT_CHANNELS_NUM; + wrong_config.channel = SOC_RMT_CHANNELS_PER_GROUP; TEST_ASSERT(rmt_config(&wrong_config) == ESP_ERR_INVALID_ARG); wrong_config = correct_config; @@ -180,24 +180,24 @@ TEST_CASE("RMT miscellaneous functions", "[rmt]") TEST_CASE("RMT multiple channels", "[rmt]") { rmt_config_t tx_cfg = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 0); - for (int i = 0; i < SOC_RMT_TX_CHANNELS_NUM; i++) { + for (int i = 0; i < SOC_RMT_TX_CANDIDATES_PER_GROUP; i++) { tx_cfg.channel = i; TEST_ESP_OK(rmt_config(&tx_cfg)); TEST_ESP_OK(rmt_driver_install(tx_cfg.channel, 0, 0)); } - for (int i = 0; i < SOC_RMT_TX_CHANNELS_NUM; i++) { + for (int i = 0; i < SOC_RMT_TX_CANDIDATES_PER_GROUP; i++) { TEST_ESP_OK(rmt_driver_uninstall(i)); } rmt_config_t rx_cfg = RMT_DEFAULT_CONFIG_RX(RMT_DATA_IO, RMT_RX_CHANNEL_ENCODING_START); - for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_NUM; i++) { + for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_PER_GROUP; i++) { rx_cfg.channel = i; TEST_ESP_OK(rmt_config(&rx_cfg)); TEST_ESP_OK(rmt_driver_install(rx_cfg.channel, 0, 0)); } - for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_NUM; i++) { + for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_PER_GROUP; i++) { TEST_ESP_OK(rmt_driver_uninstall(i)); } } @@ -342,12 +342,12 @@ TEST_CASE("RMT NEC TX and RX (Modulation/Demodulation)", "[rmt]") } #endif -TEST_CASE("RMT TX (SOC_RMT_CHANNEL_MEM_WORDS-1) symbols", "[rmt][boundary]") +TEST_CASE("RMT TX (SOC_RMT_MEM_WORDS_PER_CHANNEL-1) symbols", "[rmt][boundary]") { int tx_channel = 0; rmt_setup_testbench(tx_channel, -1, 0); - rmt_item32_t *items = malloc(sizeof(rmt_item32_t) * (SOC_RMT_CHANNEL_MEM_WORDS - 1)); - for (int i = 0; i < SOC_RMT_CHANNEL_MEM_WORDS - 1; i++) { + rmt_item32_t *items = malloc(sizeof(rmt_item32_t) * (SOC_RMT_MEM_WORDS_PER_CHANNEL - 1)); + for (int i = 0; i < SOC_RMT_MEM_WORDS_PER_CHANNEL - 1; i++) { items[i] = (rmt_item32_t) { {{ 200, 1, 200, 0 @@ -355,7 +355,7 @@ TEST_CASE("RMT TX (SOC_RMT_CHANNEL_MEM_WORDS-1) symbols", "[rmt][boundary]") } }; } - TEST_ESP_OK(rmt_write_items(tx_channel, items, SOC_RMT_CHANNEL_MEM_WORDS - 1, 1)); + TEST_ESP_OK(rmt_write_items(tx_channel, items, SOC_RMT_MEM_WORDS_PER_CHANNEL - 1, 1)); free(items); rmt_clean_testbench(tx_channel, -1); } @@ -430,7 +430,7 @@ TEST_CASE("RMT Ping-Pong operation", "[rmt]") { int tx_channel = 0; int rx_channel = RMT_RX_CHANNEL_ENCODING_START + 1; - rmt_item32_t frames[SOC_RMT_CHANNEL_MEM_WORDS * 2]; // send two block data using ping-pong + rmt_item32_t frames[SOC_RMT_MEM_WORDS_PER_CHANNEL * 2]; // send two block data using ping-pong RingbufHandle_t rb = NULL; uint32_t size = sizeof(frames) / sizeof(frames[0]); @@ -471,7 +471,7 @@ TEST_CASE("RMT Ping-Pong operation", "[rmt]") rmt_clean_testbench(tx_channel, rx_channel); } #endif -#if SOC_RMT_SUPPORT_TX_GROUP +#if SOC_RMT_SUPPORT_TX_SYNCHRO static uint32_t tx_end_time0, tx_end_time1; static void rmt_tx_end_cb(rmt_channel_t channel, void *arg) { @@ -483,7 +483,7 @@ static void rmt_tx_end_cb(rmt_channel_t channel, void *arg) } TEST_CASE("RMT TX simultaneously", "[rmt]") { - rmt_item32_t frames[SOC_RMT_CHANNEL_MEM_WORDS]; + rmt_item32_t frames[SOC_RMT_MEM_WORDS_PER_CHANNEL]; uint32_t size = sizeof(frames) / sizeof(frames[0]); int channel0 = 0; int channel1 = 1; diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index e6435f18eb..af7e8b5a2f 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -13,14 +13,14 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" +#ifdef __cplusplus +extern "C" { +#endif + #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -47,26 +47,24 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) dev->apb_conf.fifo_mask = enable; } -static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { dev->conf_ch[channel].conf1.ref_always_on = src; } -static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.ref_always_on; } -static inline void rmt_ll_tx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.ref_cnt_rst = 1; - dev->conf_ch[channel].conf1.ref_cnt_rst = 0; } -static inline void rmt_ll_rx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->conf_ch[channel].conf1.ref_cnt_rst = 1; - dev->conf_ch[channel].conf1.ref_cnt_rst = 0; } static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) @@ -119,23 +117,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel return dev->conf_ch[channel].conf0.mem_size; } -static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->conf_ch[channel].conf0.div_cnt = div; } -static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->conf_ch[channel].conf0.div_cnt = div; } -static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = dev->conf_ch[channel].conf0.div_cnt; return div == 0 ? 256 : div; } -static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = dev->conf_ch[channel].conf0.div_cnt; return div == 0 ? 256 : div; @@ -333,7 +331,7 @@ static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, } //Writes items to the specified TX channel memory with the given offset and writen length. -//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS) +//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) { for (uint32_t i = 0; i < length; i++) { diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index 5e8c64c28a..a323adfbc1 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -13,15 +13,15 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" +#ifdef __cplusplus +extern "C" { +#endif + #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -53,7 +53,7 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) dev->sys_conf.fifo_mask = enable; } -static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) dev->sys_conf.sclk_active = 0; @@ -64,21 +64,24 @@ static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel dev->sys_conf.sclk_active = 1; } -static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->sys_conf.sclk_sel; } -static inline void rmt_ll_tx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); - dev->ref_cnt_rst.val &= ~(1 << channel); } -static inline void rmt_ll_rx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->ref_cnt_rst.val |= channel_mask; +} + +static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << (channel + 2)); - dev->ref_cnt_rst.val &= ~(1 << (channel + 2)); } static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) @@ -135,22 +138,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel return dev->rx_conf[channel].conf0.mem_size; } -static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->tx_conf[channel].div_cnt = div; } -static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->rx_conf[channel].conf0.div_cnt = div; } -static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].div_cnt; } -static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.div_cnt; } @@ -211,15 +214,14 @@ static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) dev->tx_sim.en = enable; } -static inline void rmt_ll_tx_add_channel_to_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } -static inline uint32_t rmt_ll_tx_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); - return dev->tx_sim.val & 0x03; } static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) @@ -468,7 +470,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan } //Writes items to the specified TX channel memory with the given offset and writen length. -//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS) +//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) { for (uint32_t i = 0; i < length; i++) { diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index 608b72e455..0a71250dfc 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -13,14 +13,14 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include "soc/soc_caps.h" #include "soc/rmt_struct.h" +#ifdef __cplusplus +extern "C" { +#endif + #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -52,26 +52,29 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) dev->apb_conf.fifo_mask = enable; } -static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { dev->conf_ch[channel].conf1.ref_always_on = src; } -static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.ref_always_on; } -static inline void rmt_ll_tx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); - dev->ref_cnt_rst.val &= ~(1 << channel); } -static inline void rmt_ll_rx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->ref_cnt_rst.val |= channel_mask; +} + +static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); - dev->ref_cnt_rst.val &= ~(1 << channel); } static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) @@ -121,23 +124,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel return dev->conf_ch[channel].conf0.mem_size; } -static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->conf_ch[channel].conf0.div_cnt = div; } -static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->conf_ch[channel].conf0.div_cnt = div; } -static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = dev->conf_ch[channel].conf0.div_cnt; return div == 0 ? 256 : div; } -static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = dev->conf_ch[channel].conf0.div_cnt; return div == 0 ? 256 : div; @@ -199,15 +202,14 @@ static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) dev->tx_sim.en = enable; } -static inline void rmt_ll_tx_add_channel_to_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } -static inline uint32_t rmt_ll_tx_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); - return dev->tx_sim.val & 0x0F; } static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) @@ -442,7 +444,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan } //Writes items to the specified TX channel memory with the given offset and writen length. -//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS) +//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) { for (uint32_t i = 0; i < length; i++) { diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index 781e664595..afa36b082e 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -13,15 +13,15 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" +#ifdef __cplusplus +extern "C" { +#endif + #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -53,7 +53,7 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) dev->sys_conf.fifo_mask = enable; } -static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) { // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) dev->sys_conf.sclk_active = 0; @@ -64,21 +64,24 @@ static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel dev->sys_conf.sclk_active = 1; } -static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { return dev->sys_conf.sclk_sel; } -static inline void rmt_ll_tx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << channel); - dev->ref_cnt_rst.val &= ~(1 << channel); } -static inline void rmt_ll_rx_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->ref_cnt_rst.val |= channel_mask; +} + +static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { dev->ref_cnt_rst.val |= (1 << (channel + 4)); - dev->ref_cnt_rst.val &= ~(1 << (channel + 4)); } static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) @@ -135,22 +138,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel return dev->rx_conf[channel].conf0.mem_size; } -static inline void rmt_ll_tx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->tx_conf[channel].div_cnt = div; } -static inline void rmt_ll_rx_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { dev->rx_conf[channel].conf0.div_cnt = div; } -static inline uint32_t rmt_ll_tx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].div_cnt; } -static inline uint32_t rmt_ll_rx_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel) +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.div_cnt; } @@ -211,15 +214,14 @@ static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) dev->tx_sim.en = enable; } -static inline void rmt_ll_tx_add_channel_to_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val |= 1 << channel; } -static inline uint32_t rmt_ll_tx_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel) +static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t channel) { dev->tx_sim.val &= ~(1 << channel); - return dev->tx_sim.val & 0x0F; } static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) @@ -468,7 +470,7 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan } //Writes items to the specified TX channel memory with the given offset and writen length. -//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS) +//the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) { for (uint32_t i = 0; i < length; i++) { diff --git a/components/hal/include/hal/rmt_hal.h b/components/hal/include/hal/rmt_hal.h index 0576718e41..49b3f4c670 100644 --- a/components/hal/include/hal/rmt_hal.h +++ b/components/hal/include/hal/rmt_hal.h @@ -64,7 +64,7 @@ void rmt_hal_rx_channel_reset(rmt_hal_context_t *hal, uint32_t channel); * @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it) * @param counter_clk_hz: target counter clock */ -void rmt_hal_tx_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz); +void rmt_hal_tx_set_channel_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz); /** * @brief Set carrier clock for RMT channel diff --git a/components/hal/include/hal/rmt_types.h b/components/hal/include/hal/rmt_types.h index 478629bcc1..28b5bf59a3 100644 --- a/components/hal/include/hal/rmt_types.h +++ b/components/hal/include/hal/rmt_types.h @@ -29,7 +29,7 @@ typedef enum { RMT_CHANNEL_1, /*!< RMT channel number 1 */ RMT_CHANNEL_2, /*!< RMT channel number 2 */ RMT_CHANNEL_3, /*!< RMT channel number 3 */ -#if SOC_RMT_CHANNELS_NUM > 4 +#if SOC_RMT_CHANNELS_PER_GROUP > 4 RMT_CHANNEL_4, /*!< RMT channel number 4 */ RMT_CHANNEL_5, /*!< RMT channel number 5 */ RMT_CHANNEL_6, /*!< RMT channel number 6 */ diff --git a/components/hal/rmt_hal.c b/components/hal/rmt_hal.c index fa29a04a96..7c885784fb 100644 --- a/components/hal/rmt_hal.c +++ b/components/hal/rmt_hal.c @@ -41,11 +41,11 @@ void rmt_hal_rx_channel_reset(rmt_hal_context_t *hal, uint32_t channel) rmt_ll_clear_rx_end_interrupt(hal->regs, channel); } -void rmt_hal_tx_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz) +void rmt_hal_tx_set_channel_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz) { - rmt_ll_tx_reset_counter_clock_div(hal->regs, channel); + rmt_ll_tx_reset_channel_clock_div(hal->regs, channel); uint32_t counter_div = (base_clk_hz + counter_clk_hz / 2) / counter_clk_hz; - rmt_ll_tx_set_counter_clock_div(hal->regs, channel, counter_div); + rmt_ll_tx_set_channel_clock_div(hal->regs, channel, counter_div); } void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty) @@ -72,7 +72,7 @@ uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t { uint32_t len = 0; rmt_ll_rx_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW); - for (len = 0; len < SOC_RMT_CHANNEL_MEM_WORDS; len++) { + for (len = 0; len < SOC_RMT_MEM_WORDS_PER_CHANNEL; len++) { buf[len].val = hal->mem->chan[channel].data32[len].val; if (!(buf[len].val & 0x7FFF)) { break; diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 9ec7679842..9bfea90cbf 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -172,12 +172,13 @@ #define SOC_PCNT_UNIT_CHANNEL_NUM (2) /*-------------------------- RMT CAPS ----------------------------------------*/ -#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */ -#define SOC_RMT_TX_CHANNELS_NUM (8) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CHANNELS_NUM (8) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels (each channel can be configured to either TX or RX) */ -#define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ -#define SOC_RMT_SOURCE_CLK_INDEPENDENT (1) /*!< Can select different source clock for channels */ +#define SOC_RMT_GROUPS (1) /*!< One RMT group */ +#define SOC_RMT_TX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Transmit in each group */ +#define SOC_RMT_RX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Receive in each group */ +#define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */ +#define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory */ +#define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ +#define SOC_RMT_CHANNEL_CLK_INDEPENDENT (1) /*!< Can select different source clock for each channel */ /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 18 diff --git a/components/soc/esp32c3/include/soc/rmt_caps.h b/components/soc/esp32c3/include/soc/rmt_caps.h deleted file mode 100644 index 1004c1f1d5..0000000000 --- a/components/soc/esp32c3/include/soc/rmt_caps.h +++ /dev/null @@ -1,33 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define SOC_RMT_CHANNEL_MEM_WORDS (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_TX_CHANNELS_NUM (2) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CHANNELS_NUM (2) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 8 channels (each channel can be configured to either TX or RX) */ -#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ -#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ -#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ -#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index c5b6503634..e0801af168 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -10,8 +10,6 @@ #define SOC_TWAI_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#include "rmt_caps.h" - /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_PERIPH_NUM 0 @@ -30,7 +28,6 @@ #include "cpu_caps.h" #include "gpio_caps.h" #include "ledc_caps.h" -#include "rmt_caps.h" #include "spi_caps.h" #include "uart_caps.h" #include "rtc_caps.h" @@ -78,6 +75,18 @@ #define SOC_SHA_SUPPORT_SHA256 (1) +/*--------------------------- RMT CAPS ---------------------------------------*/ +#define SOC_RMT_GROUPS (1) /*!< One RMT group */ +#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */ +#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */ +#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ +#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ +#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ +#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ +#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ +#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ + /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (3072) diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index d443e5a3ae..9b4551dc00 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -158,16 +158,17 @@ #define SOC_PCNT_UNIT_CHANNEL_NUM (2) /*-------------------------- RMT CAPS ----------------------------------------*/ -#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_TX_CHANNELS_NUM (4) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CHANNELS_NUM (4) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels (each channel can be configured to either TX or RX) */ +#define SOC_RMT_GROUPS (1) /*!< One RMT group */ +#define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */ +#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */ +#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ +#define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ #define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ -#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ +#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmiting specified number of cycles in loop mode */ +#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ -#define SOC_RMT_SOURCE_CLK_INDEPENDENT (1) /*!< Can select different source clock for channels */ +#define SOC_RMT_CHANNEL_CLK_INDEPENDENT (1) /*!< Can select different source clock for each channel */ /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 22 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index b6a03c4a07..a8483b1562 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -58,14 +58,15 @@ #define SOC_PCNT_UNIT_CHANNEL_NUM (2) /*-------------------------- RMT CAPS ----------------------------------------*/ -#define SOC_RMT_CHANNEL_MEM_WORDS (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_TX_CHANNELS_NUM (4) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CHANNELS_NUM (4) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels (each channel can be configured to either TX or RX) */ +#define SOC_RMT_GROUPS (1) /*!< One RMT group */ +#define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */ +#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */ +#define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */ +#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ #define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ #define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ +#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ #define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ /*-------------------------- RTCIO CAPS --------------------------------------*/ diff --git a/components/soc/include/soc/rmt_periph.h b/components/soc/include/soc/rmt_periph.h index 4f46d9255b..c051889262 100644 --- a/components/soc/include/soc/rmt_periph.h +++ b/components/soc/include/soc/rmt_periph.h @@ -27,7 +27,7 @@ typedef struct { const int tx_sig; const int rx_sig; }; - } channels[SOC_RMT_CHANNELS_NUM]; + } channels[SOC_RMT_CHANNELS_PER_GROUP]; const int irq; const periph_module_t module; } rmt_signal_conn_t; diff --git a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c index 4be72e7db3..88b3793767 100644 --- a/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c +++ b/tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c @@ -77,11 +77,11 @@ void ref_clock_init(void) rmt_ll_enable_drive_clock(s_rmt_hal.regs, true); #if SOC_RMT_SUPPORT_XTAL - rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_BASECLK_XTAL, 39, 0, 0); // XTAL(40MHz), rmt_sclk => 1MHz (40/(1+39)) + rmt_ll_set_group_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_BASECLK_XTAL, 39, 0, 0); // XTAL(40MHz), rmt_sclk => 1MHz (40/(1+39)) #elif SOC_RMT_SUPPORT_REF_TICK - rmt_ll_set_counter_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_BASECLK_REF, 0, 0, 0); // select REF_TICK (1MHz) + rmt_ll_set_group_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_BASECLK_REF, 0, 0, 0); // select REF_TICK (1MHz) #endif - rmt_hal_tx_set_counter_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz + rmt_hal_tx_set_channel_clock(&s_rmt_hal, REF_CLOCK_RMT_CHANNEL, 1000000, 1000000); // counter clock: 1MHz rmt_ll_tx_enable_idle(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); // enable idle output rmt_ll_tx_set_idle_level(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1); // idle level: 1 rmt_ll_tx_enable_carrier_modulation(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true); From efa92cb2043d055f1e627cbbe32c8963629a2d49 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 19 Feb 2021 17:38:03 +0800 Subject: [PATCH 2/2] rmt: support invert RMT signal by GPIO matrix --- components/driver/include/driver/rmt.h | 28 ++++++++++++++++++----- components/driver/rmt.c | 14 ++++++++---- docs/en/api-reference/peripherals/rmt.rst | 3 ++- 3 files changed, 34 insertions(+), 11 deletions(-) diff --git a/components/driver/include/driver/rmt.h b/components/driver/include/driver/rmt.h index ca4734d029..ef9d58107d 100644 --- a/components/driver/include/driver/rmt.h +++ b/components/driver/include/driver/rmt.h @@ -29,6 +29,7 @@ extern "C" { #include "hal/rmt_types.h" #define RMT_CHANNEL_FLAGS_AWARE_DFS (1 << 0) /*!< Channel can work during APB clock scaling */ +#define RMT_CHANNEL_FLAGS_INVERT_SIG (1 << 1) /*!< Invert RMT signal */ /** @cond */ #define RMT_CHANNEL_FLAGS_ALWAYS_ON RMT_CHANNEL_FLAGS_AWARE_DFS /*!< Deprecated name, defined here for compatibility */ @@ -572,17 +573,18 @@ esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en); esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh); /** -* @brief Set RMT pin +* @brief Configure the GPIO used by RMT channel * * @param channel RMT channel -* @param mode TX or RX mode for RMT -* @param gpio_num GPIO number to transmit or receive the signal. +* @param mode RMT mode, either RMT_MODE_TX or RMT_MODE_RX +* @param gpio_num GPIO number, which is connected with certain RMT signal +* @param invert_signal Invert RMT signal physically by GPIO matrix * * @return -* - ESP_ERR_INVALID_ARG Parameter error -* - ESP_OK Success +* - ESP_ERR_INVALID_ARG Configure RMT GPIO failed because of wrong parameter +* - ESP_OK Configure RMT GPIO successfully */ -esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num); +esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal); /** * @brief Configure RMT parameters @@ -903,6 +905,20 @@ __attribute__((deprecated("interrupt should be handled by driver"))); void rmt_clr_intr_enable_mask(uint32_t mask) __attribute__((deprecated("interrupt should be handled by driver"))); +/** +* @brief Set RMT pin +* +* @param channel RMT channel +* @param mode TX or RX mode for RMT +* @param gpio_num GPIO number to transmit or receive the signal. +* +* @return +* - ESP_ERR_INVALID_ARG Parameter error +* - ESP_OK Success +*/ +esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num) +__attribute__((deprecated("use rmt_set_gpio instead"))); + #ifdef __cplusplus } #endif diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 2e1daf5761..12c29dde30 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -528,7 +528,7 @@ esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th return ESP_OK; } -esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num) +esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal) { RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG); @@ -540,15 +540,21 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu if (mode == RMT_MODE_TX) { RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.channels[channel].tx_sig, 0, 0); + esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.channels[channel].tx_sig, invert_signal, 0); } else { RMT_CHECK(RMT_IS_RX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_INPUT); - esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.channels[channel].rx_sig, 0); + esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.channels[channel].rx_sig, invert_signal); } return ESP_OK; } +esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num) +{ + // only for backword compatibility + return rmt_set_gpio(channel, mode, gpio_num, false); +} + static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode) { // RX mode @@ -688,7 +694,7 @@ esp_err_t rmt_config(const rmt_config_t *rmt_param) { rmt_module_enable(); - RMT_CHECK(rmt_set_pin(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num) == ESP_OK, + RMT_CHECK(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG) == ESP_OK, "set gpio for RMT driver failed", ESP_ERR_INVALID_ARG); RMT_CHECK(rmt_internal_config(&RMT, rmt_param) == ESP_OK, diff --git a/docs/en/api-reference/peripherals/rmt.rst b/docs/en/api-reference/peripherals/rmt.rst index ee0d83410f..2fced3f08a 100644 --- a/docs/en/api-reference/peripherals/rmt.rst +++ b/docs/en/api-reference/peripherals/rmt.rst @@ -119,6 +119,7 @@ Common Parameters * Extra miscellaneous parameters for the channel can be set in the **flags**. * When **RMT_CHANNEL_FLAGS_AWARE_DFS** is set, RMT channel will take REF_TICK or XTAL as source clock. The benefit is, RMT channel can continue work even when APB clock is changing. See :doc:`power_management <../system/power_management>` for more information. + * When **RMT_CHANNEL_FLAGS_INVERT_SIG** is set, the driver will invert the RMT signal sending to or receiving from the channel. It just works like an external inverter connected to the GPIO of certain RMT channel. * A **clock divider**, that will determine the range of pulse length generated by the RMT transmitter or discriminated by the receiver. Selected by setting **clk_div** to a value within [1 .. 255] range. The RMT source clock is typically APB CLK, 80Mhz by default. But when **RMT_CHANNEL_FLAGS_AWARE_DFS** is set in **flags**, RMT source clock is changed to REF_TICK or XTAL. @@ -234,7 +235,7 @@ Previously described function :cpp:func:`rmt_config` provides a convenient way t Parameters Common to Transmit and Receive Mode ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* Selection of a GPIO pin number on the input or output of the RMT - :cpp:func:`rmt_set_pin` +* Selection of a GPIO pin number on the input or output of the RMT - :cpp:func:`rmt_set_gpio` * Number of memory blocks allocated for the incoming or outgoing data - :cpp:func:`rmt_set_mem_pd` * Setting of the clock divider - :cpp:func:`rmt_set_clk_div` * Selection of the clock source, note that currently one clock source is supported, the APB clock which is 80Mhz - :cpp:func:`rmt_set_source_clk`