diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index bf99a66c6a..5fd3d4e3a7 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -41,7 +41,6 @@
 #include "soc/assist_debug_reg.h"
 #include "soc/system_reg.h"
 #include "esp32s3/rom/opi_flash.h"
-#include "hal/cache_hal.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rtc.h"
 #include "esp32c3/rom/cache.h"
@@ -99,6 +98,7 @@
 #include "esp_private/sleep_gpio.h"
 #include "hal/wdt_hal.h"
 #include "soc/rtc.h"
+#include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "hal/efuse_ll.h"
 #include "soc/periph_defs.h"
@@ -464,6 +464,11 @@ void IRAM_ATTR call_start_cpu0(void)
     do_multicore_settings();
 #endif
 
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    //cache hal ctx needs to be initialised
+    cache_hal_init();
+#endif
+
     // When the APP is loaded into ram for execution, some hardware initialization behaviors
     // in the bootloader are still necessary
 #if CONFIG_APP_BUILD_TYPE_RAM
diff --git a/components/hal/esp32/cache_hal_esp32.c b/components/hal/esp32/cache_hal_esp32.c
index 33a7b1fb26..b4f48fde26 100644
--- a/components/hal/esp32/cache_hal_esp32.c
+++ b/components/hal/esp32/cache_hal_esp32.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,11 @@
 
 static uint32_t s_cache_status[2];
 
+void cache_hal_init(void)
+{
+    //for compatibility
+}
+
 /**
  * On ESP32, The cache_hal_suspend()/cache_hal_resume() are replacements
  * for Cache_Read_Disable()/Cache_Read_Enable() in ROM.