fix(esp_hw_support): fix p4 OTG phy bad suspend cause high power consumption on sleep

components/esp_hw_support/CMakeLists.txt

@@ -31,6 +31,7 @@ if(NOT non_os_build)
                      "sleep_modem.c"
                      "sleep_modes.c"
                      "sleep_console.c"
+                     "sleep_usb.c"
                      "sleep_gpio.c"
                      "sleep_event.c"
                      "regi2c_ctrl.c"

components/esp_hw_support/include/esp_private/sleep_usb.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
+/**
+ * @brief Backup usb OTG phy bus_clock / stoppclk configuration and
+ *         before light sleep to avoid current leakage
+ */
+void sleep_usb_otg_phy_backup_and_disable(void);
+
+/**
+ * @brief Restore initial usb OTG phy configuration when wakeup from light sleep
+ */
+void sleep_usb_otg_phy_restore(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/linker.lf

@@ -26,6 +26,8 @@ entries:
         pmu_param (noflash)
     if SOC_USB_SERIAL_JTAG_SUPPORTED = y:
         sleep_console (noflash)
+    if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD = y:
+        sleep_usb (noflash)
     if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
         rtc_wdt (noflash_text)
     if PERIPH_CTRL_FUNC_IN_IRAM = y:

components/esp_hw_support/sleep_modes.c

@@ -74,6 +74,7 @@
 #include "esp_private/sleep_console.h"
 #include "esp_private/sleep_cpu.h"
 #include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_usb.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_task_wdt.h"
 #include "esp_private/sar_periph_ctrl.h"
@@ -667,6 +668,11 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s
         // Only avoid USJ pad leakage here, USB OTG pad leakage is prevented through USB Host driver.
         sleep_console_usj_pad_backup_and_disable();
 #endif
+#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
+        if (!(pd_flags & PMU_SLEEP_PD_CNNT)) {
+            sleep_usb_otg_phy_backup_and_disable();
+        }
+#endif
 #if CONFIG_MAC_BB_PD
         mac_bb_power_down_cb_execute();
 #endif
@@ -715,6 +721,11 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
+#endif
+#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
+    if (!(pd_flags & PMU_SLEEP_PD_CNNT)) {
+        sleep_usb_otg_phy_restore();
+    }
 #endif
     sar_periph_ctrl_power_enable();
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL

components/esp_hw_support/sleep_usb.c

@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "esp_private/sleep_usb.h"
+#include "esp_attr.h"
+
+#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
+#include "hal/usb_utmi_ll.h"
+#include "hal/usb_dwc_ll.h"
+
+static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state;
+
+void sleep_usb_otg_phy_backup_and_disable(void)
+{
+    s_usb_utmi_bus_clock_state = _usb_utmi_ll_bus_clock_is_enabled();
+    if (!s_usb_utmi_bus_clock_state) {
+        _usb_utmi_ll_enable_bus_clock(true);
+    }
+    s_usb_utmi_stoppclk_state = usb_dwc_ll_get_stoppclk_st(&USB_DWC_HS);
+    usb_dwc_ll_set_stoppclk(&USB_DWC_HS, true);
+}
+
+void sleep_usb_otg_phy_restore(void)
+{
+    _usb_utmi_ll_enable_bus_clock(true);
+    usb_dwc_ll_set_stoppclk(&USB_DWC_HS, s_usb_utmi_stoppclk_state);
+    if (!s_usb_utmi_bus_clock_state) {
+        _usb_utmi_ll_enable_bus_clock(false);
+    }
+}
+#endif

components/hal/esp32p4/include/hal/usb_dwc_ll.h

@@ -6,8 +6,10 @@
 
 #pragma once
 
+#include <stdlib.h>
 #include <stdint.h>
 #include <stdbool.h>
+#include "esp_attr.h"
 #include "soc/usb_dwc_struct.h"
 #include "hal/usb_dwc_types.h"
 #include "hal/misc.h"
@@ -977,6 +979,17 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem
     qtd->buffer_status_val = 0;
 }
 
+// ---------------------------- Power and Clock Gating Register --------------------------------
+FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop)
+{
+    hw->pcgcctl_reg.stoppclk = stop;
+}
+
+FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw)
+{
+    return hw->pcgcctl_reg.stoppclk;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32p4/include/hal/usb_utmi_ll.h

@@ -50,6 +50,16 @@ FORCE_INLINE_ATTR void _usb_utmi_ll_enable_bus_clock(bool clk_en)
 // HP_SYS_CLKRST.soc_clk_ctrlx and LP_AON_CLKRST.hp_usb_clkrst_ctrlx are shared registers, so this function must be used in an atomic way
 #define usb_utmi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_ll_enable_bus_clock(__VA_ARGS__)
 
+/**
+ * Get the enable status of the USB UTMI PHY bus clock
+ *
+ * @return Return true if USB UTMI PHY bus clock is enabled
+ */
+FORCE_INLINE_ATTR bool _usb_utmi_ll_bus_clock_is_enabled(void)
+{
+    return (HP_SYS_CLKRST.soc_clk_ctrl1.reg_usb_otg20_sys_clk_en && LP_AON_CLKRST.hp_usb_clkrst_ctrl1.usb_otg20_phyref_clk_en);
+}
+
 /**
  * @brief Reset the USB UTMI PHY and USB_DWC_HS controller
  */